CN116187224B

CN116187224B - Process design suite device library and design migration method

Info

Publication number: CN116187224B
Application number: CN202310470937.4A
Authority: CN
Inventors: 汤雅权
Original assignee: Xinyaohui Technology Co ltd
Current assignee: Xinyaohui Technology Co ltd
Priority date: 2023-04-27
Filing date: 2023-04-27
Publication date: 2023-07-18
Anticipated expiration: 2043-04-27
Also published as: CN116187224A

Abstract

The application provides a process design suite device library and a design migration method. The process design kit device library includes: a first device library including a plurality of first devices, predetermined based on a general process recipe and a general process layer; the second device library includes at least one second device, and the structure of the second device library and the second device are configurable to correspond to a specified process recipe and are mappable to a specified process layer. For a process to be developed, providing at least a portion of the process to be developed by the first device library and providing the remainder of the process to be developed by the second device library, the at least a portion of the process to be developed being determined by comparing the process to be developed with a general process. This helps to significantly reduce development and verification cycles.

Description

Process design suite device library and design migration method

Technical Field

The present disclosure relates to the field of computer technologies, and in particular, to a device library of a process design suite and a design migration method.

Background

In chip designs such as large scale mixed signal circuit and analog circuit designs, it is generally necessary to utilize a process design kit (Process Design Kit, PDK) to perform design and verification tasks. However, with the increase of the integration level and design complexity of the integrated circuit, and the development of various new process and new device structures, the development and verification period is also greatly increased. In addition, in the front-end circuit design and the back-end layout design, from one process node to another process node, the design migration is necessary to accelerate the circuit design, and with the improvement of the design complexity and the development of the process, the labor consumption for the design migration is greatly increased.

Therefore, the application provides the process design kit device library and the design migration method, which can effectively reduce the development and verification period of using the process design kit device library, and can effectively reduce the time and resources input in design migration.

Disclosure of Invention

In a first aspect, the present application provides a library of process design kit devices. The process design kit device library includes: a first device library, wherein the first device library comprises a plurality of first devices, the plurality of first devices being predetermined based on a common process recipe and a common process layer; a second device library, wherein the second device library comprises at least one second device, the structure of the second device library and the at least one second device are configurable to correspond to a specified process recipe and are mappable to a specified process layer. Wherein, for a process to be developed, at least a portion of the process to be developed is provided by the first device library of the process design kit device library and the remainder of the process to be developed is provided by the second device library of the process design kit device library, the at least a portion of the process to be developed being determined by comparing the process to be developed with the general process.

With the first aspect of the present application, the decoupling of the generic device library part and the configurable part is achieved by a first device library predetermined based on the generic process recipe and the generic process layer and a second device library configurable to correspond to the specified process recipe and to be mapped to the specified process layer. In this way, the adaptation to new semiconductor devices and new semiconductor processes can be flexibly realized by the configurable part of the process design kit device library, namely the second device library, and meanwhile, the semiconductor devices with a large number of available models and design rules and mature semiconductor processes capable of being applied on a large scale can be fully utilized by the general device library part of the process design kit device library, namely the first device library, so that the development and verification cycle can be greatly reduced.

In a possible implementation manner of the first aspect of the present application, for a design to be migrated, determining the first device library of the process design kit device library and determining the second device library of the process design kit device library by comparing a pre-migration process and a post-migration process corresponding to the design to be migrated, and completing migration of the design to be migrated using the process design kit device library.

In a possible implementation manner of the first aspect of the present application, the plurality of first devices include transistors, contact holes, and interconnection lines applicable to the general process, and the first device library further includes respective electrical characteristics and design rules of the plurality of first devices.

In a possible implementation manner of the first aspect of the present application, the at least one second device includes a basic element applicable to the specified process, and the second device library further includes an electrical characteristic and a design rule of the at least one second device associated with the specified process.

In a possible implementation manner of the first aspect of the present application, the first device library further includes design rules, electrical rules, and layout design verification rules associated with the generic process procedure.

In a possible implementation manner of the first aspect of the present application, the structure of the second device library may further be configured to correspond to a metal layer structure associated with the to-be-developed process.

In a possible implementation manner of the first aspect of the present application, the process design kit device library includes a generic view for showing the first device library and the generic process layer.

In a possible implementation manner of the first aspect of the present application, the at least one portion of the to-be-developed process is a superposition portion between the to-be-developed process and the general-purpose process, and the remaining portion of the to-be-developed process is a non-superposition portion between the to-be-developed process and the general-purpose process.

In a possible implementation manner of the first aspect of the present application, the design to be migrated is a circuit design, and the pre-migration process and the post-migration process are a previous process node and a next process node for the circuit design, respectively.

In a possible implementation manner of the first aspect of the present application, the design to be migrated is a layout design, and the pre-migration process and the post-migration process are respectively a previous process node and a subsequent process node for the layout design.

In one possible implementation manner of the first aspect of the present application, the first device library of the process design kit device library is a reusable part between the pre-migration process and the post-migration process, and the second device library of the process design kit device library is an non-reusable part between the pre-migration process and the post-migration process.

In a possible implementation manner of the first aspect of the present application, the process design kit device library is used for design migration between a plurality of process nodes, and for any immediately adjacent pair of process nodes between the plurality of process nodes, the design migration between the pair of process nodes is completed by comparing a process of a previous process node and a process of a next process node in the pair of process nodes based on the first device library and by configuring the second device library.

In one possible implementation of the first aspect of the present application, at least a portion of the process of a subsequent process node of the pair of process nodes is provided by the first device library of the process design kit device library and the remaining portion of the process of the subsequent process node of the pair of process nodes is provided by the second device library of the process design kit device library.

In a possible implementation manner of the first aspect of the present application, the first device library of the process design kit device library is a reusable part between a process of a previous process node and a process of a subsequent process node of the pair of process nodes, and the second device library of the process design kit device library is an non-reusable part between a process of a previous process node and a process of a subsequent process node of the pair of process nodes.

In a second aspect, embodiments of the present application provide a design migration method. The design migration method comprises the following steps: providing a process design kit device library comprising a first device library and a second device library, wherein the first device library comprises a plurality of first devices, the plurality of first devices being predetermined based on a common process recipe and a common process tier, the second device library comprising at least one second device, the structure of the second device library and the at least one second device being configurable to correspond to and be mappable to a specified process tier, the first device library for providing at least a portion of a process recipe to be developed and the second device library for providing a remaining portion of the process recipe to be developed, the at least a portion of the process recipe to be developed being determined by comparing the process recipe to be developed and the common process recipe; for a design to be migrated, determining the first device library of the process design kit device library and determining the second device library of the process design kit device library by comparing a pre-migration process and a post-migration process corresponding to the design to be migrated; and utilizing the process design suite device library to complete migration of the design to be migrated.

With the second aspect of the present application, the decoupling of the generic device library part and the configurable part is achieved by a first device library predetermined based on the generic process recipe and the generic process layer and a second device library configurable to correspond to the specified process recipe and to be mapped to the specified process layer. In this way, the adaptation to new semiconductor devices and new semiconductor processes can be flexibly realized by the configurable part of the process design kit device library, namely the second device library, and meanwhile, the semiconductor devices with a large number of available models and design rules and mature semiconductor processes capable of being applied on a large scale can be fully utilized by the general device library part of the process design kit device library, namely the first device library, so that the development and verification cycle can be greatly reduced.

In a possible implementation manner of the second aspect of the present application, the design to be migrated is a circuit design, and the pre-migration process and the post-migration process are respectively a previous process node and a subsequent process node for the circuit design.

In a possible implementation manner of the second aspect of the present application, the design to be migrated is a layout design, and the pre-migration process and the post-migration process are respectively a previous process node and a subsequent process node for the layout design.

In one possible implementation manner of the second aspect of the present application, the first device library of the process design kit device library is a reusable part between the pre-migration process and the post-migration process, and the second device library of the process design kit device library is an non-reusable part between the pre-migration process and the post-migration process.

In a possible implementation manner of the second aspect of the present application, the process design kit device library is used for design migration between a plurality of process nodes, and for any immediately adjacent pair of process nodes between the plurality of process nodes, the design migration between the pair of process nodes is completed by comparing a process of a previous process node and a process of a next process node in the pair of process nodes based on the first device library and by configuring the second device library.

In one possible implementation of the second aspect of the present application, at least a portion of the process of a subsequent process node of the pair of process nodes is provided by the first device library of the process design kit device library and the remaining portion of the process of the subsequent process node of the pair of process nodes is provided by the second device library of the process design kit device library.

In a possible implementation manner of the second aspect of the present application, the first device library of the process design kit device library is a reusable part between a process of a previous process node and a process of a subsequent process node of the pair of process nodes, and the second device library of the process design kit device library is an non-reusable part between a process of a previous process node and a process of a subsequent process node of the pair of process nodes.

In a third aspect, embodiments of the present application further provide a computer device, where the computer device includes a memory, a processor, and a computer program stored on the memory and executable on the processor, where the processor implements a method according to any implementation manner of any one of the foregoing aspects, when the processor executes the computer program.

In a fourth aspect, embodiments of the present application also provide a computer-readable storage medium storing computer instructions that, when run on a computer device, cause the computer device to perform a method according to any one of the implementations of any one of the above aspects.

In a fifth aspect, embodiments of the present application also provide a computer program product comprising instructions stored on a computer-readable storage medium, which when run on a computer device, cause the computer device to perform a method according to any one of the implementations of any one of the above aspects.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a library of device of a process design kit according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a design migration based on a library of process design kit devices according to an embodiment of the present application;

FIG. 3 is a schematic flow chart of a design migration method according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a computing device according to an embodiment of the present application.

Detailed Description

Embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

It should be understood that in the description of this application, "at least one" means one or more than one, and "a plurality" means two or more than two. In addition, the words "first," "second," and the like, unless otherwise indicated, are used solely for the purposes of description and are not to be construed as indicating or implying a relative importance or order.

FIG. 1 is a schematic diagram of a library of process design kit devices according to one embodiment of the present application. As shown in fig. 1, the process design kit device library a 100 includes a first device library 110 and a second device library 120. Wherein the first device library 110 comprises a plurality of first devices. First device a112, first device B114, and first device C116 are exemplarily shown in fig. 1. The first device library 110 may include any number of first devices. The first plurality of devices is predetermined based on the common process recipe 130 and the common process layer 132. The second device library 120 includes at least one second device. Second device a122 and second device B124 are exemplarily shown in fig. 1. The second device library 120 may include any number of second devices. The structure of the second device library 120 and the at least one second device (e.g., second device a122 and second device B124) may be configured to correspond to a specified process recipe 140 and may be mapped to a specified process layer 142. Wherein for a process to be developed, at least a portion of the process to be developed is provided by the first device library 110 of the process design kit device library a 100 and a remaining portion of the process to be developed is provided by the second device library 120 of the process design kit device library a 100, the at least a portion of the process to be developed being determined by comparing the process to be developed with the general process 130. The process design kit device library a 100 is used to provide process design kits (Process Design Kit, PDK), which are bridges for communication between chip design companies, foundry and electronic design automation (Electronic design automation, EDA) companies. Generally, the process design kit device library A100 and the provided process design kit contain technical documentation packages for chip design and verification work. In some embodiments, the process design kit contains elements that reflect the basic elements of the manufacturing process, such as transistors, contact holes, interconnect lines, etc. In some embodiments, the contents of the process design suite also include design rule files, electrical rule files, layout level definition files, SPICE simulation models, device layout and period customization parameters, and the like. The process design kit device library a 100 and the provided process design kit are closely related to semiconductor processes, including a set of files describing semiconductor process details for use by the chip design EDA tool. The process design kit provided by the fab is typically used prior to chip production to ensure that the fab is able to produce chips based on the chip design, thereby ensuring the intended functionality and performance of the chips. When a new semiconductor process needs to be developed, for example, a matched process design kit needs to be developed for a process to be developed, wherein a set of document materials reflecting the semiconductor process of a foundry is defined by the language of the foundry, so that the method can be used for physical verification in chip design, and is also a key factor for determining whether chips flow to and from each other. By way of example and not limitation, the library of process design kit devices a 100 and the provided process design kit may contain one or more of the following, including but not limited to: a Device Model (Device Model), a simulation Model file provided by the foundry; symbols for schematic design, wherein parameterized design elements pass simulation verification; component description format (Component Description Format, CDF), attribute description file of the device defining type, name, parameters and parameter call relation function set of the device, device model, view format of the device, etc.; parameterized cells (Parameterized Cell, pcell) describing possible customization methods for transistors and other devices; the technical file is used for designing and verifying a layout and comprises a mapping relation definition of a design data layer and a process layer, an attribute definition of the design data layer, an online design rule, an electrical rule, a display color definition, a graphic format definition and the like; the physical verification rule file comprises a layout verification file and the like.

With continued reference to fig. 1, as described above, the process design kit PDK is closely related to details related to the semiconductor process, and on one hand, the basic elements of the semiconductor manufacturing process, such as transistors, contact holes, interconnection lines, etc., are to be reflected, and on the other hand, information such as design rule files, electrical rule files, layout level definition files, SPICE simulation models, device layout and period customization parameters, etc., are to be reflected. Thus, the process design kit PDK serves as a bridge for communication between the chip design company, foundry, and EDA company, not only to adapt specific semiconductor processes employed by the foundry (e.g., the wafer foundry, the foundry provides document materials reflecting their semiconductor processes, etc.), but also to adapt the relevant characteristics of the EDA tools provided by the EDA company (e.g., the EDA tools developed by the EDA company may have improvements in terms of device models, parameterized units, and verification rules, etc.), and also to take into account the requirements of the chip design company on circuit design, layout design, e.g., to implement specific chip functions, to employ specific devices, or to employ specific semiconductor processes, etc. This means that for newly developed semiconductor processes, for example, for the process to be developed, communication and collaboration between the chip design company, foundry and EDA company need to be comprehensively considered, and the process design suite is also a key factor in the chip manufacturing success or failure as a base stone for the chip design and physical verification links. With the development of semiconductor devices and semiconductor processes, new process steps, new device structures such as metal layer structures, new electrical characteristics of devices, design rules, etc., all of which need to be embodied by a process design kit in the process of chip design development. For example, the process design kit device library a 100 needs to provide technical details in terms of its metal layer structure, electrical characteristics, and associated design rules, physical verification rules for a new semiconductor device, and needs to include technical files describing the associated semiconductor process details for a new semiconductor process, such as a new process recipe. With the increasing scale and design complexity of integrated circuits, it is necessary to design a device library of a suite through a high-quality and high-efficiency process to shorten the period of chip development and verification as much as possible, improve the chip design efficiency and reduce the cost as much as possible. In addition, in the whole process of chip development, the front-end circuit diagram design and the back-end layout design are related, and may also relate to differences in process procedures and differences between different design databases, and sometimes design migration of a process manufacturing level from one process manufacturing node to another process manufacturing node is required, which also depends on a high-quality and high-efficiency process design suite device library to shorten the labor investment and time required for the design migration.

With continued reference to FIG. 1, the process design kit device library A100 includes a first device library 110 and a second device library 120. The plurality of first devices included in the first device library 110 are predetermined based on the general process recipe 130 and the general process layer 132. The structure of the second device library 120 and the at least one second device included in the second device library 120 may be configured to correspond to a specified process recipe 140 and may be mapped to a specified process layer 142. Here, the general process 130 corresponds to a general, common or large-scale mature process used in semiconductor process. The generic process layer 132 corresponds to a metal layer structure, a process fabrication layer, etc. associated with the generic process 130. As mentioned above, the process design kit is closely related to the process and device structure information such as the metal layer structure. Accordingly, the plurality of first devices are predetermined based on the common process 130 and the common process layer 132, which means that the plurality of first devices, for example, the first device a112, etc., are common semiconductor devices corresponding to the common semiconductor process and common device structure information, such as the common process manufacturing layer and the common metal layer structure, etc. Accordingly, the plurality of first devices included in the first device library 110 also reflect the relevant basic elements of the general semiconductor manufacturing process, such as the transistors, contact holes, interconnect lines, etc. associated with the general process steps 130 and the general process layer 132. The plurality of first devices included in the first device library 110 also embody macro-related factors of the general semiconductor manufacturing process, such as design rule files, electrical rule files, layout level definition files, SPICE simulation models, device layout and period customization parameters associated with the general process 130 and the general process layer 132. Therefore, the first device library and the structure thereof are beneficial to quickly using the general device list and the process manufacturing layer information, as well as the device electrical characteristics, the design rules and the like, thereby being beneficial to efficiently and highly-quality building the process design suite device library A100. In contrast, the structure of the second device library 120 and the at least one second device included in the second device library 120 may be configured to correspond to a specified process recipe 140 and may be mapped to a specified process layer 142. The given process 140 may correspond to a relatively less common process, such as a newly developed process or a narrower application, than the generic process 130. The specified process layer 142 corresponds to the metal layer structure, process manufacturing layer, etc. associated with the specified process 140 relative to the generic process layer 132. As mentioned above, the process design kit is closely related to the process and device structure information such as the metal layer structure. Accordingly, the structure of the second device library 120 and the at least one second device comprised by the second device library 120 may be configured to correspond to the specified process 140 and may be mapped to the specified process layer 142, which means that the at least one second device, e.g. the second device a122, is a semiconductor device for the specified process 140, which corresponds to the specified process 140 and device structure information associated with the specified process 140, such as process fabrication layer and metal layer structures, etc. The at least one second device included in the second device library 120 also reflects the transistors, contact holes, interconnects, etc. associated with the given process 140. The structure of second device library 120 and the at least one second device also embody macroscopic factors such as design rule files, electrical rule files, layout level definition files, SPICE simulation models, device layout and period customization parameters associated with a given process recipe 140 and a given process layer 142, and the like. Also, the structure of the second device library 120 and the at least one second device included in the second device library 120 may be configurable, that is, the structure of the second device library 120 and also the at least one second device may be commonly or individually configured so as to correspond to the specified process 140 and be mapped to the specified process layer 142, which means that the specified process 140 and/or the specified process layer 142 may be flexibly changed (e.g., a new semiconductor process or a new process manufacturing layer is introduced, etc.), and then the changes made to the specified process 140 and/or the specified process layer 142 may be reflected by reconfiguring the structure of the second device library 120 and the at least one second device. The first device library 110 may be understood as a generic device library portion of the process design kit device library a 100 and the second device library 120 may be understood as a configurable portion of the process design kit device library a 100. In this manner, decoupling of the generic device library portion and the configurable portion is achieved by the first device library 110 predetermined based on the generic process recipes 130 and the generic process layer 132 and the second device library 120 configurable to correspond to the specified process recipes 140 and mappable to the specified process layer 142. Thus, the adaptation of new semiconductor devices and new semiconductor processes can be flexibly achieved by the configurable portion of the process design kit device library a 100, i.e., the second device library 120, while the semiconductor devices having a large number of available models and design rules and mature, mass-applicable semiconductor processes can be fully utilized by the generic device library portion of the process design kit device library a 100, i.e., the first device library 110, thereby helping to substantially reduce development and verification cycles. Therefore, for a specific process, by dividing and combining the first device library 110 and the second device library 120, the matched process design kit device library a 100 can be quickly and efficiently constructed for chip design and verification using the specific process.

With continued reference to FIG. 1, it should be appreciated that the generic device library portion of the process design kit device library A100, i.e., the first device library 110, is a relative concept with respect to the configurable portion of the process design kit device library A100, i.e., the second device library 120. A particular device or a particular process may be partitioned into the first device library 110 in some business scenarios, but may be partitioned into the second device library 120 in other business scenarios. This may be because in some business scenarios the particular device or the particular process is of a common, generic or mass-application type, but in other business scenarios the particular device or the particular process is of a rare, non-generic or application-wide type. For example, critical devices for high-speed digital communication circuits, such as certain specially designed transistors, may occupy a significant portion of the chip design in a communication-related business scenario (e.g., chip design for communication), such as belonging to a critical chip functional design, which may be suitable for partitioning into the first device library 110, that is, predetermined based on the generic process 130 and the generic process layer 132, which helps to reduce development cycle and cost by utilizing the mature process. However, such a specially designed transistor, in other business scenarios, such as memory related business scenarios (e.g., memory chip design), may occupy only a small portion of the chip design, such as belonging to a relatively minor chip functional design, which may be suitable for partitioning into the second device library 120, i.e., configurable to correspond to a given process recipe 140 and mappable to a given process layer 142, thus facilitating the rapid build-up of a process design kit device library a 100 suitable for a business scenario of a memory chip design using configurable features. In addition, some device models or process iterations are high in frequency and fast in iteration speed, and may be suitable for being divided into the second device library 120, so that the configurable characteristics can be better utilized to better realize the adaptation to new semiconductor devices and new semiconductor processes. Thus, various factors such as the specific chip design objectives, customer requirements, business scenario, and technology iteration speed determine the division between the generic device library portion of the process design kit device library A100, i.e., the first device library 110, and the configurable portion of the process design kit device library A100, i.e., the second device library 120. The process design kit device library a 100 shown in fig. 1 not only implements decoupling of the universal device library portion and the configurable portion, but also can flexibly adjust the division between the universal device library portion and the configurable portion according to specific service scenarios, chip design purposes, customer requirements, service scenarios, technology iteration speeds, and the like, thereby facilitating rapid and efficient construction of the matched process design kit device library a 100.

Continuing with FIG. 1, the division between the generic device library portion, i.e., the first device library 110, of the lower process design kit device library A100 and the configurable portion, i.e., the second device library 120, of the process design kit device library A100 is illustrated with the device capacitance. The first device library 110 may include a device such as a field effect transistor capacitor, for example, the first device a112 shown in fig. 1 may be a field effect transistor capacitor. The field effect transistor refers to a Metal-Oxide-semiconductor field effect transistor (MOSFET), and the field effect transistor capacitor is a capacitor realized based on the MOSFET, and is referred to as a MOS capacitor for short. The field effect transistor capacitor takes a MOSFET as a capacitor, and the principle is that gate oxide between a gate electrode (gate) and a channel of the MOSFET is taken as an insulating medium, the gate electrode is taken as an upper polar plate, and three ends of a source electrode, a drain electrode and a substrate are short-circuited to form a lower polar plate. The field effect transistor capacitor, i.e., the MOS capacitor, and its associated semiconductor process are of a type commonly known, commonly used, or used in large scale applications. Thus, in general, the MOS capacitance is suitably partitioned into the first device library 110, that is, predetermined based on the generic process 130 and the generic process layer 132, which helps to reduce the development cycle and reduce the cost with the mature process. In contrast, metal-Insulator-Metal (MIM) capacitors, also known as MIM capacitors, refer to the use of Metal-Insulator-Metal elements to construct capacitors. The MIM is a sandwich structure consisting of three layers of films of metal, insulator and metal. MIM capacitors are typically composed of a topmost two-layer metal and a middle special metal layer. The MIM capacitor is equivalent to a parallel plate capacitor, the distance between two metal layers at the topmost layer is larger, and the capacitance value of the formed capacitor is very small. The dielectric layer in the middle of the MIM capacitor is thinner, and the formed capacitor density is higher. The MIM capacitor has the characteristics of small parasitic capacitance and high precision. The capacitance value of the MOS capacitor is less deterministic and stable than that of the MIM capacitor, and compared with the MOS capacitor, the MIM capacitor has more accurate capacitance value, and the capacitance value cannot change along with bias voltage change, and is also called as a polar plate capacitor. However, in the related semiconductor process, the MIM capacitor requires additional process and additional mask compared to the MOS capacitor, and also requires the use of a dielectric layer material with a high dielectric constant due to the characteristics of the MIM capacitor. The chip design of the device using the MIM capacitor needs to face problems such as reduced linearity of the integrated capacitor and reduced stability of the linear system. Therefore, by dividing the MOS capacitance into the first device library 110, for example, by assuming that the first device a112 is a MOS capacitance, and dividing the MIM capacitance into the second device library 120, for example, by assuming that the second device a122 is a MIM capacitance, the MOS capacitance can be predetermined based on the general process 130 and the general process layer 132, thereby reducing the development period and reducing the cost by using the mature process; on the other hand, the MIM capacitor can be configured to correspond to a specified process and can be mapped to a specified process layer, so that the electrical characteristic, design rule and related semiconductor process of the device model of the MIM capacitor can be better adapted according to the characteristics and design problems of the MIM capacitor, process optimization for the MIM capacitor can be more flexibly adopted, and finally, a matched process design kit device library A100 can be quickly and efficiently constructed.

With continued reference to fig. 1, the process design kit device library a 100 shown in fig. 1 not only implements decoupling of the generic device library portion and the configurable portion, but also can flexibly adjust the division between the generic device library portion and the configurable portion according to specific service scenarios, chip design purposes, customer requirements, service scenarios, technology iteration speeds, and the like, that is, can perform reconfiguration based on decoupling, that is, decoupling reconfiguration, and is helpful for quickly and efficiently constructing the matched process design kit device library a 100. Thus, for a process to be developed, at least a portion of the process to be developed is provided by the first device library 110 of the process design kit device library a 100 and the remainder of the process to be developed is provided by the second device library 120 of the process design kit device library a 100, the at least a portion of the process to be developed being determined by comparing the process to be developed with the generic process 130. This means that the general process 130 and the first device library 110 in the process design kit device library a 100 shown in fig. 1 can be fully utilized, so that the development period is reduced, the cost is reduced by using the mature process, and meanwhile, the process difference between the process to be developed and the general process 130 is considered, and the second device library 120 in the process design kit device library a 100 shown in fig. 1 is utilized to adapt the process to be developed, so that the process design kit device library a 100 matched with the process to be developed can be constructed quickly and efficiently. And the PDK device library is decoupled into the universal device library and the configurable structure part, the universal device library can be displayed through a universal view, the reconstructed universal device library can be used for rapidly completing the development and verification of the PDK device library of the appointed process, and the development efficiency of the PDK device library is greatly improved through a method of multiplexing and recombining the configurable structure part. Therefore, by using the decoupling reconstruction scheme of the process design kit device library a 100 shown in fig. 1, the development and verification efficiency of the PDK device library can be greatly improved, and meanwhile, the general PDK device library structure is helpful to show different points among different process steps, so that more direct and effective help can be provided in the design migration flow.

With continued reference to fig. 1, the entire flow of chip development involves front-end circuit diagram design and back-end layout design, and may involve differences in process and differences between different design databases, sometimes requiring process-level design migration from one process node to another. Through the process design suite device library a 100 shown in fig. 1, the general device library portion and the configurable portion are decoupled, so that the division between the general device library portion and the configurable portion can be flexibly adjusted according to specific service scenarios, chip design purposes, customer requirements, service scenarios, technology iteration speeds and the like, thereby meeting the requirements of design migration and shortening the labor investment and time required by the design migration.

In one possible implementation, for a design to be migrated, the migration of the design to be migrated is accomplished using the process design kit device library a 100 by comparing a pre-migration process recipe and a post-migration process recipe corresponding to the design to be migrated, determining the first device library 110 of the process design kit device library a 100, and determining the second device library 120 of the process design kit device library a 100. Thus, the design migration requirement can be met, and the labor investment and time required by the design migration can be shortened.

In one possible implementation, the plurality of first devices includes transistors, contact holes, and interconnect lines suitable for the general process 130, and the first device library 110 further includes respective electrical characteristics and design rules of the plurality of first devices. In one possible implementation, the at least one second device includes basic elements applicable to the specified process 140, and the second device library 120 further includes electrical characteristics and design rules of the at least one second device associated with the specified process 140. In one possible implementation, the first device library 110 further includes design rules, electrical rules, layout design verification rules associated with the generic process 130. In one possible implementation, the structure of the second device library 120 may also be configured to correspond to a metal layer structure associated with the process to be developed. Therefore, the decoupling of the universal device library part and the configurable part is realized, and the division between the universal device library part and the configurable part can be flexibly adjusted according to specific business scenes, chip design purposes, customer demands, business scenes, technical iteration speed and the like, so that the matched process design suite device library A100 can be constructed quickly and efficiently.

In one possible implementation, the process design kit device library A100 includes a generic view for showing the first device library 110 and the generic process layer 132. In this way, the first device library 110 and the generic process layer 132 can be better shown with a generic view, which helps to improve development efficiency.

In one possible implementation, the at least a portion of the process to be developed is a superposition between the process to be developed and the general process 130, and the remaining portion of the process to be developed is a non-superposition between the process to be developed and the general process 130. Thus, the device library A100 of the process design kit matched with the process to be developed can be constructed quickly and efficiently.

In one possible implementation, the design to be migrated is a circuit design, and the pre-migration process and the post-migration process are respectively directed to a previous process node and a next process node of the circuit design. Thus, the design migration requirement can be met, and the labor investment and time required by the design migration can be shortened.

In one possible implementation, the design to be migrated is a layout design, and the pre-migration process and the post-migration process are respectively directed to a previous process node and a subsequent process node of the layout design. Thus, the design migration requirement can be met, and the labor investment and time required by the design migration can be shortened.

In one possible implementation, the first device library 110 of the process design kit device library a 100 is a reusable portion between the pre-migration process and the post-migration process, and the second device library 120 of the process design kit device library a 100 is a non-reusable portion between the pre-migration process and the post-migration process. Thus, the design migration requirement can be met, and the labor investment and time required by the design migration can be shortened.

In one possible implementation, the process design kit device library a 100 is used for design migration between a plurality of process nodes, and for any immediately adjacent pair of process nodes between the plurality of process nodes, the design migration between the pair of process nodes is completed by comparing the process of the previous process node with the process of the next process node in the pair based on the first device library 110 and by configuring the second device library 120. In some embodiments, at least a portion of the process of a subsequent process node of the pair of process nodes is provided by the first device library 110 of the process design kit device library a 100 and the remainder of the process of the subsequent process node of the pair of process nodes is provided by the second device library 120 of the process design kit device library a 100. In some embodiments, the first device library 110 of the process design kit device library a 100 is a reusable portion between a process of a previous process node and a process of a subsequent process node of the pair of process nodes, and the second device library 120 of the process design kit device library a 100 is a non-reusable portion between a process of a previous process node and a process of a subsequent process node of the pair of process nodes. Thus, the design migration requirement can be met, and the labor investment and time required by the design migration can be shortened.

FIG. 2 is a schematic diagram of a design migration based on a library of process design kit devices according to an embodiment of the present application. As shown in FIG. 2, the process design kit device library B200 is used for design migration from a first design database 210 to a second design database 212. The process design kit device library B200 includes a first device library and a second device library. The first device library includes a plurality of first devices predetermined based on a general process recipe and a general process layer, and the second device library includes at least one second device, the structure of which and the at least one second device are configurable to correspond to a specific process recipe and are mappable to a specific process layer. The kit device library B200 is designed by a process, the first device library is used for providing at least a part of a process to be developed and the second device library is used for providing the rest of the process to be developed, and the at least a part of the process to be developed is determined by comparing the process to be developed and the general process. The design to be migrated is to be migrated from the first design database 210 to the second design database 212. For the design to be migrated, the first device library of the process design kit device library B200 and the second device library of the process design kit device library B200 are determined by comparing the pre-migration process 220 and the post-migration process 222 corresponding to the design to be migrated. And finally, completing the migration of the design to be migrated by utilizing the process design suite device library B200. It should be appreciated that in some embodiments, the pre-migration process 220 may correspond to one process design kit and the post-migration process 222 may correspond to another process design kit, and that the two process design kits may be integrated to create the library of process design kit device B200. In the whole process of chip development, the front-end circuit diagram design and the back-end layout design are involved, and may also involve differences in the process and differences between different design databases, and sometimes a process-level design migration from one process node to another is required, for example, the first design database 210 to the second design database 212 shown in fig. 2. Here, the first design database 210 may be considered an old design database and associated with the pre-migration process 220, and the second design database 212 may be considered a new design database and associated with the post-migration process 222. Details and technical effects related to the process design kit device library B200 may refer to the process design kit device library a 100 shown in fig. 1, so that the process design kit device library B200, by using decoupling of the general device library portion and the configurable portion, can flexibly adjust the division between the general device library portion and the configurable portion according to specific service scenarios, chip design purposes, customer requirements, service scenarios, technology iteration speeds, and the like, thereby meeting the requirements of design migration and shortening the labor investment and time required by the design migration. Therefore, the process design kit device library B200 shown in fig. 2 can not only complete the design migration of the front-end circuit diagram, but also complete the rapid design migration of the back-end layout design. Further, by adopting the process design kit device library B200 shown in fig. 2, that is, the general PDK device library scheme, the design migration of the circuit diagram and the layout with high quality can be achieved, only the general PDK device library is established on the basis of the PDKs of the plurality of process steps, and by taking fig. 2 as an example, the first device library of the process design kit device library B200 and the second device library of the process design kit device library B200 are determined by comparing the pre-migration process step 220 and the post-migration process step 222 corresponding to the design to be migrated.

Fig. 3 is a flow chart of a design migration method according to an embodiment of the present application. As shown in fig. 3, the design migration method includes the following steps.

Step S310: a process design kit device library is provided comprising a first device library and a second device library, wherein the first device library comprises a plurality of first devices predetermined based on a common process recipe and a common process layer, the second device library comprises at least one second device, the structure of the second device library and the at least one second device are configurable to correspond to and are mappable to a specified process recipe, the first device library is used for providing at least a portion of a process recipe to be developed and the second device library is used for providing a remaining portion of the process recipe to be developed, the at least a portion of the process recipe to be developed is determined by comparing the process recipe to be developed and the common process recipe.

Step S320: for a design to be migrated, determining the first device library of the process design kit device library and determining the second device library of the process design kit device library by comparing a pre-migration process and a post-migration process corresponding to the design to be migrated.

Step S330: and finishing the migration of the design to be migrated by using the process design suite device library.

Referring to the above steps, for a process to be developed, at least a portion of the process to be developed is provided by the first device library of the process design kit device library and the remainder of the process to be developed is provided by the second device library of the process design kit device library, the at least a portion of the process to be developed being determined by comparing the process to be developed and the general process. This means that the general process and the first device library in the process design kit device library can be fully utilized, thereby reducing the development period and reducing the cost by using the mature process, and meanwhile, the process difference between the process to be developed and the general process is considered, and the second device library in the process design kit device library is utilized to adapt to the process to be developed, so that the process design kit device library matched with the process to be developed can be constructed quickly and efficiently. In this manner, decoupling of the generic device library portion and the configurable portion is achieved by a first device library predetermined based on the generic process recipe and the generic process layer and a second device library 120 configurable to correspond to the specified process recipe and to be mapped to the specified process layer. In this way, the adaptation to new semiconductor devices and new semiconductor processes can be flexibly realized by the configurable part of the process design kit device library, namely the second device library, and meanwhile, the semiconductor devices with a large number of available models and design rules and mature semiconductor processes capable of being applied on a large scale can be fully utilized by the general device library part of the process design kit device library, namely the first device library, so that the development and verification cycle can be greatly reduced. Therefore, for a specific process, the matched process design kit device library can be quickly and efficiently constructed by dividing and combining the first device library and the second device library, so as to realize chip design and verification by adopting the specific process. In addition, in the whole process of chip development, the front-end circuit diagram design and the back-end layout design are involved, and the differences in the process and the differences between different design databases may be involved, so that the process manufacturing level design migration is sometimes required from one process node to another process node. The device library of the process design suite utilizes the decoupling of the universal device library part and the configurable part, and the division between the universal device library part and the configurable part can be flexibly adjusted according to specific service scenes, chip design purposes, customer requirements, service scenes, technical iteration speeds and the like, so that the requirements of design migration are met, and the labor investment and time required by the design migration are shortened.

The design migration method shown in fig. 3 provides a design migration method at a process level, and the process design suite device library is applied to design migration among a plurality of process nodes, so that the design migration of a circuit diagram can be rapidly completed on a plurality of process steps, and the layout design migration as convenient as the design migration of the circuit diagram can be rapidly completed on a plurality of process steps.

In one possible implementation, the design to be migrated is a circuit design, and the pre-migration process and the post-migration process are respectively directed to a previous process node and a next process node of the circuit design. Thus, the design migration of the circuit diagram is rapidly completed on a plurality of process steps.

In one possible implementation, the design to be migrated is a layout design, and the pre-migration process and the post-migration process are respectively directed to a previous process node and a subsequent process node of the layout design. Thus, the layout design migration can be rapidly completed on the multi-process.

In one possible implementation, the first device library of the process design kit device library is a reusable portion between the pre-migration process and the post-migration process, and the second device library of the process design kit device library is an non-reusable portion between the pre-migration process and the post-migration process. Thus, the design migration requirement can be met, and the labor investment and time required by the design migration can be shortened.

In one possible implementation, the process design kit device library is used for design migration between a plurality of process nodes, the design migration between the pair of process nodes being accomplished by comparing a process of a previous process node and a process of a subsequent process node of the pair of process nodes for any immediately adjacent pair of process nodes between the plurality of process nodes, based on the first device library and by configuring the second device library. In some embodiments, at least a portion of the process of a subsequent process node of the pair of process nodes is provided by the first device library of the process design kit device library and the remaining portion of the process of the subsequent process node of the pair of process nodes is provided by the second device library of the process design kit device library. In some embodiments, the first device library of the process design kit device library is a reusable portion between a process of a previous process node and a process of a subsequent process node of the pair of process nodes, and the second device library of the process design kit device library is a non-reusable portion between a process of a previous process node and a process of a subsequent process node of the pair of process nodes. Thus, the design migration requirement can be met, and the labor investment and time required by the design migration can be shortened.

Fig. 4 is a schematic structural diagram of a computing device provided in an embodiment of the present application, where the computing device 400 includes: one or more processors 410, a communication interface 420, and a memory 430. The processor 410, communication interface 420, and memory 430 are interconnected by a bus 440. Optionally, the computing device 400 may further include an input/output interface 450, where the input/output interface 450 is connected to an input/output device for receiving parameters set by a user, etc. The computing device 400 can be used to implement some or all of the functionality of the device embodiments or system embodiments described above in the embodiments of the present application; the processor 410 can also be used to implement some or all of the operational steps of the method embodiments described above in the embodiments of the present application. For example, specific implementations of the computing device 400 performing various operations may refer to specific details in the above-described embodiments, such as the processor 410 being configured to perform some or all of the steps of the above-described method embodiments or some or all of the operations of the above-described method embodiments. For another example, in the present embodiment, the computing device 400 may be configured to implement some or all of the functions of one or more components of the apparatus embodiments described above, and the communication interface 420 may be configured to implement communication functions and the like necessary for the functions of the apparatuses, components, and the processor 410 may be configured to implement processing functions and the like necessary for the functions of the apparatuses, components.

It should be appreciated that the computing device 400 of fig. 4 may include one or more processors 410, and that the processors 410 may cooperatively provide processing power in a parallelized connection, a serialized connection, a serial-parallel connection, or any connection, or that the processors 410 may constitute a processor sequence or processor array, or that the processors 410 may be separated into primary and secondary processors, or that the processors 410 may have different architectures such as heterogeneous computing architectures. In addition, the computing device 400 shown in FIG. 4, the associated structural and functional descriptions are exemplary and not limiting. In some example embodiments, computing device 400 may include more or fewer components than shown in fig. 4, or combine certain components, or split certain components, or have a different arrangement of components.

The processor 410 may have various specific implementations, for example, the processor 410 may include one or more of a central processing unit (central processing unit, CPU), a graphics processor (graphic processing unit, GPU), a neural network processor (neural-network processing unit, NPU), a tensor processor (tensor processing unit, TPU), or a data processor (data processing unit, DPU), which are not limited in this embodiment. Processor 410 may also be a single-core processor or a multi-core processor. Processor 410 may be comprised of a combination of a CPU and hardware chips. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (programmable logic device, PLD), or a combination thereof. The PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (field-programmable gate array, FPGA), general-purpose array logic (generic array logic, GAL), or any combination thereof. The processor 410 may also be implemented solely with logic devices incorporating processing logic, such as an FPGA or digital signal processor (digital signal processor, DSP) or the like. The communication interface 420 may be a wired interface, which may be an ethernet interface, a local area network (local interconnect network, LIN), etc., or a wireless interface, which may be a cellular network interface, or use a wireless local area network interface, etc., for communicating with other modules or devices.

The memory 430 may be a nonvolatile memory such as a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically Erasable EPROM (EEPROM), or a flash memory. Memory 430 may also be volatile memory, which may be random access memory (random access memory, RAM) used as external cache. By way of example, and not limitation, many forms of RAM are available, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous DRAM (SLDRAM), and direct memory bus RAM (DR RAM). Memory 430 may also be used to store program code and data such that processor 410 invokes the program code stored in memory 430 to perform some or all of the operational steps of the method embodiments described above, or to perform corresponding functions in the apparatus embodiments described above. Moreover, computing device 400 may contain more or fewer components than shown in FIG. 4, or may have a different configuration of components.

The bus 440 may be a peripheral component interconnect express (peripheral component interconnect express, PCIe) bus, or an extended industry standard architecture (extended industry standard architecture, EISA) bus, a unified bus (Ubus or UB), a computer quick link (compute express link, CXL), a cache coherent interconnect protocol (cache coherent interconnect for accelerators, CCIX), or the like. The bus 440 may be divided into an address bus, a data bus, a control bus, and the like. The bus 440 may include a power bus, a control bus, a status signal bus, and the like in addition to a data bus. But is shown with only one bold line in fig. 4 for clarity of illustration, but does not represent only one bus or one type of bus.

The method and the device provided in the embodiments of the present application are based on the same inventive concept, and because the principles of solving the problems by the method and the device are similar, the embodiments, implementations, examples or implementation of the method and the device may refer to each other, and the repetition is not repeated. Embodiments of the present application also provide a system that includes a plurality of computing devices, each of which may be structured as described above. The functions or operations that may be implemented by the system may refer to specific implementation steps in the above method embodiments and/or specific functions described in the above apparatus embodiments, which are not described herein.

Embodiments of the present application also provide a computer-readable storage medium having stored therein computer instructions which, when executed on a computer device (e.g., one or more processors), may implement the method steps in the above-described method embodiments. The specific implementation of the processor of the computer readable storage medium in executing the above method steps may refer to specific operations described in the above method embodiments and/or specific functions described in the above apparatus embodiments, which are not described herein again.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. The present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Embodiments of the present application may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The present application may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied therein. The computer program product includes one or more computer instructions. When loaded or executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.). Computer readable storage media can be any available media that can be accessed by a computer or data storage devices, such as servers, data centers, etc. that contain one or more collections of available media. Usable media may be magnetic media (e.g., floppy disks, hard disks, tape), optical media, or semiconductor media. The semiconductor medium may be a solid state disk, or may be a random access memory, flash memory, read only memory, erasable programmable read only memory, electrically erasable programmable read only memory, register, or any other form of suitable storage medium.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. Each flow and/or block of the flowchart and/or block diagrams, and combinations of flows and/or blocks in the flowchart and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiment of the application can be sequentially adjusted, combined or deleted according to actual needs; the modules in the system of the embodiment of the application can be divided, combined or deleted according to actual needs. Such modifications and variations of the embodiments of the present application are intended to be included herein, if they fall within the scope of the claims and their equivalents.

Claims

1. A library of process design kit devices, the library comprising:

a first device library, wherein the first device library comprises a plurality of first devices, the plurality of first devices being predetermined based on a common process recipe and a common process layer;

a second device library, wherein the second device library comprises at least one second device, the structure of the second device library and the at least one second device are configurable to correspond to a specified process recipe and are mappable to a specified process layer,

Wherein for a process to be developed, providing at least a portion of the process to be developed by the first device library of the process design kit device library and providing a remaining portion of the process to be developed by the second device library of the process design kit device library, the at least a portion of the process to be developed being determined by comparing the process to be developed with the generic process,

said at least a portion of said process to be developed being a portion of overlap between said process to be developed and said general process, said remaining portion of said process to be developed being a portion of misalignment between said process to be developed and said general process,

the general process is different from the specified process.

2. The process design kit device library of claim 1, wherein for a design to be migrated, the migration of the design to be migrated is accomplished using the process design kit device library by comparing a pre-migration process and a post-migration process corresponding to the design to be migrated, determining the first device library of the process design kit device library, and determining the second device library of the process design kit device library.

3. The process design kit device library of claim 1, wherein the plurality of first devices comprise transistors, contact holes, interconnect lines adapted for the common process, the first device library further comprising respective electrical characteristics and design rules of the plurality of first devices.

4. The process design kit device library of claim 1, wherein the at least one second device comprises a base element suitable for the specified process, the second device library further comprising electrical characteristics and design rules of the at least one second device associated with the specified process.

5. The process design kit device library of claim 1, wherein the first device library further comprises design rules, electrical rules, layout design verification rules associated with the generic process.

6. The process design kit device library of claim 1, wherein the structure of the second device library is further configurable to correspond to a metal layer structure associated with the process to be developed.

7. The process design kit device library of claim 1, wherein the process design kit device library comprises a generic view for displaying the first device library and the generic process layer.

8. The library of claim 2, wherein the design to be migrated is a circuit design, and the pre-migration process and the post-migration process are for a previous process node and a next process node of the circuit design, respectively.

9. The process design kit device library of claim 2, wherein the design to be migrated is a layout design, and the pre-migration process and the post-migration process are directed to a previous process node and a subsequent process node of the layout design, respectively.

10. The process design kit device library of claim 2, wherein the first device library of the process design kit device library is a reusable portion between the pre-migration process and the post-migration process, and the second device library of the process design kit device library is a non-reusable portion between the pre-migration process and the post-migration process.

11. The process design kit device library of claim 1, wherein the process design kit device library is configured for design migration between a plurality of process nodes, wherein for any immediately adjacent pair of process nodes between the plurality of process nodes, the design migration between the pair of process nodes is accomplished by comparing a process of a previous process node to a process of a subsequent process node of the pair of process nodes based on the first device library and by configuring the second device library.

12. The process design kit device library of claim 11, wherein at least a portion of the process of a subsequent process node of the pair of process nodes is provided by the first device library of the process design kit device library and the remainder of the process of the subsequent process node of the pair of process nodes is provided by the second device library of the process design kit device library.

13. The process design kit device library of claim 12, wherein the first device library of the process design kit device library is a reusable portion between a process of a previous process node and a process of a subsequent process node of the pair of process nodes, and the second device library of the process design kit device library is an non-reusable portion between a process of a previous process node and a process of a subsequent process node of the pair of process nodes.

14. A design migration method, characterized in that the design migration method comprises:

providing a process design kit device library comprising a first device library and a second device library, wherein the first device library comprises a plurality of first devices, the plurality of first devices being predetermined based on a common process recipe and a common process tier, the second device library comprising at least one second device, the structure of the second device library and the at least one second device being configurable to correspond to and be mappable to a specified process tier, the first device library for providing at least a portion of a process recipe to be developed and the second device library for providing a remaining portion of the process recipe to be developed, the at least a portion of the process recipe to be developed being determined by comparing the process recipe to be developed and the common process recipe;

For a design to be migrated, determining the first device library of the process design kit device library and determining the second device library of the process design kit device library by comparing a pre-migration process and a post-migration process corresponding to the design to be migrated; and

utilizing the process design suite device library to complete the migration of the design to be migrated,

the general process is different from the specified process.

15. The design migration method of claim 14, wherein the design to be migrated is a circuit design, and the pre-migration process and the post-migration process are respectively for a previous process node and a next process node of the circuit design.

16. The method of claim 14, wherein the design to be migrated is a layout design, and the pre-migration process and the post-migration process are respectively directed to a previous process node and a next process node of the layout design.

17. The design migration method of claim 14, wherein the first device library of the process design kit device library is a reusable portion between the pre-migration process and the post-migration process, and the second device library of the process design kit device library is an non-reusable portion between the pre-migration process and the post-migration process.

18. The design migration method of claim 14, wherein the process design kit device library is used for design migration between a plurality of process nodes, wherein for any immediately adjacent pair of process nodes between the plurality of process nodes, the design migration between the pair of process nodes is accomplished by comparing a process of a previous process node with a process of a subsequent process node of the pair of process nodes based on the first device library and by configuring the second device library.

19. The design migration method of claim 18, wherein at least a portion of the process of a subsequent process node of the pair of process nodes is provided by the first device library of the process design kit device library and the remainder of the process of the subsequent process node of the pair of process nodes is provided by the second device library of the process design kit device library.

20. The design migration method of claim 19, wherein the first device library of the process design kit device library is a reusable portion between a process of a previous process node and a process of a subsequent process node of the pair of process nodes, and the second device library of the process design kit device library is an non-reusable portion between a process of a previous process node and a process of a subsequent process node of the pair of process nodes.