CN116185131A - Clock synchronization circuit and tester - Google Patents

Clock synchronization circuit and tester Download PDF

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Publication number
CN116185131A
CN116185131A CN202310202999.7A CN202310202999A CN116185131A CN 116185131 A CN116185131 A CN 116185131A CN 202310202999 A CN202310202999 A CN 202310202999A CN 116185131 A CN116185131 A CN 116185131A
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China
Prior art keywords
clock
module
signal
frequency
time sequence
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Pending
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CN202310202999.7A
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Chinese (zh)
Inventor
黄辉蓝
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Hangzhou Changchuan Technology Co Ltd
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Hangzhou Changchuan Technology Co Ltd
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Priority to CN202310202999.7A priority Critical patent/CN116185131A/en
Publication of CN116185131A publication Critical patent/CN116185131A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The application discloses clock synchronization circuit and test machine, wherein, clock synchronization circuit includes: the clock fanout module is used for fanning out the time base clock signals to form a first clock signal and a second clock signal; the frequency-reducing module is connected with the clock fan-out module and is used for performing frequency-reducing processing on the first clock signal to form a synchronous trigger signal; the time sequence matching adjustment module is connected with the clock fan-out module and used for performing time sequence matching adjustment on the second clock signal to form a time base signal with a preset time sequence constraint relation with the synchronous trigger signal. The circuit establishes a preset time sequence constraint relation between two paths of clock signals generated by fan-out of the clock fan-out module by utilizing the frequency reducing module and the time sequence matching adjustment module, so that clock synchronization at the receiving end of each daughter board card can be realized under the condition that the time base signals are not required to be frequency-doubled particularly high. The large-scale circuit design of the logic device is not needed, the special complex time sequence programming is not needed, and the material cost and the labor cost are greatly reduced.

Description

Clock synchronization circuit and tester
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a clock synchronization circuit and a tester.
Background
The prior clock synchronization technology adopts a general logic chip to send clock signals to each daughter board card. Because the delay deviation among all channels of the logic chip is controlled to be hundreds of picoseconds, strict alignment is difficult to be carried out, and therefore, the issued time base signal (TimeBase) and the synchronous trigger signal (SyncTrigger) clear signals can only realize nanosecond synchronization.
In order to increase the synchronization accuracy, only the frequency of the time base signal can be increased. However, the frequency of the time base signal has an upper limit for the output end and the receiving end, so that the precision cannot reach less than 1 nanosecond. Meanwhile, time base signals and synchronous trigger signals issued to all the daughter boards by the clock board are not in strict time sequence constraint relation, so that the synchronous trigger signals synchronously trigger time points of zero clearing of the counter, all the daughter boards cannot be unified, the problem of clock cycle crossing exists, and the precision depends on the frequency of the time base signals.
In addition, the jitter performance of the time base signal sent out through the logic chip is seriously deteriorated. The circuit scale of the general logic chip is huge, so the material cost is high. Meanwhile, the general logic chip needs to be subjected to simulation programming, so that the labor cost is high.
Disclosure of Invention
The purpose of the application is to provide a clock synchronization circuit and a testing machine so as to avoid clock synchronization by adopting a logic chip.
According to a first aspect of embodiments of the present application, there is provided a clock synchronization circuit, the circuit comprising:
the clock fanout module is used for fanning out the time base clock signals to form a first clock signal and a second clock signal;
the frequency-reducing module is connected with the clock fan-out module and is used for performing frequency-reducing processing on the first clock signal to form a synchronous trigger signal;
the time sequence matching adjustment module is connected with the clock fan-out module and used for performing time sequence matching adjustment on the second clock signal to form a time base signal with a preset time sequence constraint relation with the synchronous trigger signal.
In some alternative embodiments of the present application, the frequency of the first clock signal and the frequency of the second clock signal are the same, and the phase difference between the first clock signal and the second clock signal is constant;
the preset time sequence constraint relation is as follows: the frequency of the time base signal is an integer multiple of the frequency of the synchronization trigger signal, and the rising edge of the synchronization trigger signal is different from the rising edge of the time base signal by half a period of the time base signal.
In some optional embodiments of the present application, the clock synchronization circuit further comprises:
the first driving module is connected with the frequency-reducing module and is used for driving the synchronous trigger signal to the target board card;
the second driving module is connected with the time sequence matching adjustment module and used for driving the time base signal to the target board card.
In some alternative embodiments of the present application, the target board card includes a receiving chip; the receiving chip is used for synchronously counting according to the synchronous trigger signal and the time base signal.
In some optional embodiments of the present application, the target board card further includes an integer counter and a fractional counter; the integer counter and the decimal counter are respectively connected with a receiving chip, and the receiving chip is specifically used for increasing a first threshold value on the integer counter and clearing the decimal counter when receiving the rising edge of the synchronous trigger signal; the receiving chip is specifically further configured to increment a second threshold on the fractional counter when the rising edge of the time-base signal is received, until the rising edge of the synchronization trigger signal is received again, and zero-clearing the fractional counter.
In some alternative embodiments of the present application, the wires between the first drive module and the target board card are equal in length to the wires between the second drive module and the target board card.
In some optional embodiments of the present application, the target board card is a plurality of; the wires between the first driving module and the target boards are equal in length, and the wires between the second driving module and the target boards are equal in length.
In some alternative embodiments of the present application, the first driving module and the second driving module are both low-skew buffers, and the clock offset of the first driving module is the same as the clock offset of the second driving module.
In some optional embodiments of the present application, the clock fan-out module is a clock fan-out buffer, the down-conversion module is a frequency divider, and the timing matching adjustment module is a delay compensator.
According to a second aspect of embodiments of the present application, there is provided a testing machine comprising: the clock synchronization circuit of any one of the embodiments of the first aspect.
The technical scheme of the application has the following beneficial technical effects:
the circuit establishes the preset time sequence constraint relation between the two paths of clock signals generated by the fan-out of the clock fan-out module by utilizing the frequency reducing module and the time sequence matching adjustment module, so that clock synchronization at the receiving end of each daughter board card can be realized under the condition that the time base signals are not required to be frequency-doubled particularly high. The large-scale circuit design of the logic device is not needed, special complex time sequence programming is not needed, and the material cost and the labor cost are low.
Drawings
FIG. 1 is a schematic diagram of a clock synchronization circuit in an exemplary embodiment of the present application;
FIG. 2 is a schematic diagram of a clock synchronization circuit in another exemplary embodiment of the present application;
FIG. 3 is a diagram of alignment of a synchronization trigger signal with a time-based signal in an exemplary embodiment of the present application;
fig. 4 is a schematic diagram of a clock synchronization circuit in another exemplary embodiment of the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present application. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present application.
A layer structure schematic diagram according to an embodiment of the present application is shown in the drawings. The figures are not drawn to scale, wherein certain details may be exaggerated and some details may be omitted for clarity. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
It will be apparent that the embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
In the description of the present application, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In addition, the technical features described below in the different embodiments of the present application may be combined with each other as long as they do not collide with each other.
The clock synchronization circuit and the testing machine provided by the embodiment of the application are described in detail below by means of specific embodiments and application scenes thereof with reference to the accompanying drawings.
As shown in fig. 1, in a first aspect of the embodiments of the present application, there is provided a clock synchronization circuit, the circuit including: the device comprises a clock fan-out module, a frequency reducing module and a time sequence matching adjustment module; the clock fanout module is used for fanning out time base clock signals to form a first clock signal and a second clock signal; the frequency-reducing module is connected with the clock fan-out module and is used for performing frequency-reducing processing on the first clock signal to form a synchronous trigger signal; the time sequence matching adjustment module is connected with the clock fan-out module and is used for performing time sequence matching adjustment on the second clock signal to form a time base signal with a preset time sequence constraint relation with the synchronous trigger signal.
The connection relation between each unit and each module in this embodiment includes: the receiving end of the Clock fan-out module is used for receiving a Time-based Clock signal (Time_Base_clock), the output end of the Clock fan-out module is respectively connected with the input end of the frequency-reducing module and the input end of the Time sequence matching adjustment module, and the output ends of the frequency-reducing module and the Time sequence matching adjustment module can be directly or indirectly connected to each daughter board card.
The signal transmission flow of this embodiment includes: the time base clock signal is divided into two paths of clock signals, namely a first clock signal and a second clock signal through a clock fan-out module, wherein the first clock signal and the second clock signal can be identical and slightly different under the condition of not influencing the establishment of a preset time sequence constraint relation, and then the first clock signal enters a frequency reducing module for frequency reducing processing to form a synchronous trigger signal which is used for synchronously triggering zero clearing of a timer; the second clock signal enters a Time sequence matching adjustment module to carry out Time sequence matching adjustment, and a Time Base signal (Time_Base) output by the Time sequence matching adjustment module and a synchronous trigger signal (SyncTrigger) form a preset Time sequence constraint relation.
The circuit establishes the preset time sequence constraint relation between the two paths of clock signals generated by the fan-out of the clock fan-out module by utilizing the frequency reducing module and the time sequence matching adjustment module, so that clock synchronization at the receiving end of each daughter board card can be realized under the condition that the time base signals are not required to be frequency-doubled particularly high. The large-scale circuit design of the logic device is not needed, special complex time sequence programming is not needed, and the material cost and the labor cost are low.
In some embodiments, the first clock signal and the second clock signal are the same frequency, and the phase difference between the first clock signal and the second clock signal is constant; the preset time sequence constraint relation is that the frequency of the time base signal is an integral multiple of the frequency of the synchronous trigger signal, and the rising edge of the synchronous trigger signal is different from the rising edge of the time base signal by half a period of the time base signal, which can be seen in fig. 3.
As an example, the phase difference of the first clock signal and the second clock signal remains constant and is less than 100ps.
According to the preset time sequence constraint relation of the embodiment, clocks of receiving ends of all the daughter boards can be accurately synchronized.
As shown in fig. 2, in some embodiments, the clock synchronization circuit further comprises: a first drive module and a second drive module; the first driving module is connected with the frequency-reducing module and is used for driving the synchronous trigger signal to the target board card; the second driving module is connected with the time sequence matching adjustment module and is used for driving the time base signal to the target board card.
In this embodiment, the down conversion module is indirectly connected to the target board through the first driving module, and the timing matching adjustment module is also indirectly connected to the target board through the second driving module. In the embodiment, the input end of the first driving module is connected with the output end of the frequency reducing module, and the output end of the first driving module is connected with the target board; the input end of the second driving module is connected with the output end of the time sequence matching adjustment module, and the output end of the second driving module is connected with the target board card. The first driving modules can be the same or slightly adjusted according to actual needs.
In some embodiments, as shown in FIG. 4, the target board includes a receiving chip; the receiving chip is used for synchronously counting according to the synchronous trigger signal and the time base signal.
In this embodiment, the target board is only provided with the receiving chip, and no additional logic chip is required. The embodiment does not adopt logic chip output and can maintain the jitter performance of the time base signal clock. The large-scale circuit design of the logic device is not needed, special complex time sequence programming is not needed, and the material cost and the labor cost are low.
In some embodiments, referring still to FIG. 4, the target board further includes an integer counter and a fractional counter; the integer counter and the decimal counter are respectively connected with a receiving chip, and the receiving chip is specifically used for increasing a first threshold value on the integer counter and clearing the decimal counter when receiving the rising edge of the synchronous trigger signal; the receiving chip is specifically further configured to increment a second threshold on the fractional counter when the rising edge of the time-based signal is received, until the rising edge of the synchronization trigger signal is received again, and zero clearing the fractional counter.
In this embodiment, the first threshold and the second threshold may be set according to actual needs, and may be 1, 2, 5, or the like. Illustratively, as shown in fig. 3, after the receiving chip receives the rising edge of the synchronous trigger signal each time, 1 is added to the integer counter, and then the decimal counter is cleared; and adding 1 to the decimal counter after the receiving chip receives the rising edge of the Time Base signal (Time_Base) each Time until the rising edge of the Time Base signal comes, and performing zero clearing operation of the decimal counter. According to this principle, a counter is continuously accumulated, thereby realizing synchronous counting. The clock synchronization is realized by means of rising edge alignment of clocks without depending on clock count density, and the accuracy of clock synchronization control can reach within 100 picoseconds.
As shown in fig. 4, in the embodiment of the present application, the number of target boards is 1 or more, and when the number of target boards is 1, the wires between the first driving module and the target boards are equal in length to the wires between the second driving module and the target boards. In another embodiment, when there are multiple target boards, the wires between the first driving module and the multiple target boards are equal in length, and the wires between the second driving module and the multiple target boards are equal in length, so that phases of time base signals received by the target boards are aligned, phases of synchronous trigger signals received by the target boards are aligned, and therefore a preset time sequence constraint relation between the synchronous trigger signals and the time base signals is kept on the target boards.
As an example, the time base signals received by each target board are phase aligned, remain constant and less than 100ps; the phase alignment of the synchronous trigger signals received by each target board card is kept constant and less than 100ps.
In this embodiment, the length of the wiring can be controlled according to the actual design through the board wiring.
As an example, the target board card may include, but is not limited to, a digital board card, a power board card, an analog board card, a radio frequency board card, and the like.
In some embodiments, the clock offset of the first driving module is the same as the clock offset of the second driving module, and the same clock offset can ensure that the synchronous trigger signal and the time base signal reaching each target board card always keep the same preset time sequence constraint relation; the first driving module and the second driving module are both low-skew buffers, and in this embodiment, clock offset caused by the device itself can be greatly reduced by using the low-skew buffers.
By way of example, clock skew between output channels of a low skew buffer is less than 30 picoseconds, and clock synchronization control accuracy can be achieved to within 30 picoseconds.
As an example, the clock fanout module is a clock fanout buffer; the clock skew between the output channels of the clock fanout buffer is less than 100 picoseconds.
In some embodiments, the down conversion module is a frequency divider and the timing matching adjustment module is a delay compensator.
In the embodiment, the time sequence constraint is established only by adopting the frequency divider and the delay compensator, the output of a logic chip is not adopted, the clock synchronization can be realized without particularly high frequency multiplication of the time base signal, and the jitter performance of the time base signal can be maintained.
In a second aspect of embodiments of the present application, there is provided a testing machine comprising: the clock synchronization circuit of any one of the embodiments of the first aspect.
The testing machine provided in the embodiment of the present application can implement each process implemented by the above clock synchronization circuit embodiment, and in order to avoid repetition, a description is omitted here.
The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those of ordinary skill in the art without departing from the spirit of the present application and the scope of the claims, which are also within the protection of the present application.

Claims (10)

1. A clock synchronization circuit, comprising:
the clock fanout module is used for fanning out the time base clock signals to form a first clock signal and a second clock signal;
the frequency-reducing module is connected with the clock fan-out module and is used for performing frequency-reducing processing on the first clock signal to form a synchronous trigger signal;
the time sequence matching adjustment module is connected with the clock fan-out module and is used for performing time sequence matching adjustment on the second clock signal to form a time base signal with a preset time sequence constraint relation with the synchronous trigger signal.
2. The clock synchronization circuit of claim 1, wherein a frequency of the first clock signal and a frequency of the second clock signal are the same, and a phase difference of the first clock signal and the second clock signal is constant;
the preset time sequence constraint relation is as follows: the frequency of the time base signal is an integer multiple of the frequency of the synchronization trigger signal, and the rising edge of the synchronization trigger signal is different from the rising edge of the time base signal by half a period of the time base signal.
3. The clock synchronization circuit according to claim 1 or 2, further comprising:
the first driving module is connected with the frequency-reducing module and is used for driving the synchronous trigger signal to a target board card;
and the second driving module is connected with the time sequence matching adjustment module and used for driving the time base signal to the target board card.
4. The clock synchronization circuit of claim 3, wherein the target board card comprises a receiving chip;
the receiving chip is used for synchronously counting according to the synchronous trigger signal and the time base signal.
5. The clock synchronization circuit of claim 4, wherein the target board card further comprises an integer counter and a fractional counter; the integer counter and the decimal counter are respectively connected with the receiving chip, and the receiving chip is specifically used for increasing a first threshold value on the integer counter and clearing the decimal counter when the rising edge of the synchronous trigger signal is received; the receiving chip is specifically further configured to increment a second threshold on the fractional counter when the rising edge of the time-base signal is received, until the rising edge of the synchronization trigger signal is received again, and zero-clearing the fractional counter.
6. The clock synchronization circuit of claim 3, wherein the trace between the first drive module and the target board is of equal length as the trace between the second drive module and the target board.
7. The clock synchronization circuit of claim 3, wherein the target board card is a plurality of;
the wires between the first driving module and the plurality of target boards are equal in length, and the wires between the second driving module and the plurality of target boards are equal in length.
8. The clock synchronization circuit of claim 3, wherein the first driver module and the second driver module are both low skew buffers, and wherein the clock skew of the first driver module is the same as the clock skew of the second driver module.
9. The clock synchronization circuit of claim 1 or 2, wherein the clock fanout module is a clock fanout buffer, the down-conversion module is a frequency divider, and the timing matching adjustment module is a delay compensator.
10. A test machine, comprising: the clock synchronization circuit of any one of claims 1-9.
CN202310202999.7A 2023-02-24 2023-02-24 Clock synchronization circuit and tester Pending CN116185131A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310202999.7A CN116185131A (en) 2023-02-24 2023-02-24 Clock synchronization circuit and tester

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310202999.7A CN116185131A (en) 2023-02-24 2023-02-24 Clock synchronization circuit and tester

Publications (1)

Publication Number Publication Date
CN116185131A true CN116185131A (en) 2023-05-30

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310202999.7A Pending CN116185131A (en) 2023-02-24 2023-02-24 Clock synchronization circuit and tester

Country Status (1)

Country Link
CN (1) CN116185131A (en)

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