CN111628753A - Clock phase alignment method and circuit for high-speed serial transceiver - Google Patents
Clock phase alignment method and circuit for high-speed serial transceiver Download PDFInfo
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Abstract
A clock phase alignment method and circuit for a high speed serial transceiver. The method comprises the following steps of 1: sampling a parallel clock signal of a channel to be processed in N reference clock signal periods to obtain N sampling results, wherein the sampling results are first numerical values or second numerical values, and N is greater than 1; step 2: determining a counting result according to the number of first numerical values in the N sampling results; and step 3: adjusting the phase of the parallel clock signals for multiple times, and repeating the step 1 and the step 2 after each adjustment to obtain multiple counting results with the numerical values from 0 to N; and 4, step 4: drawing a relation curve of the delay time and the corresponding counting result; and 5: according to the delay time corresponding to the rising edge or the falling edge of the relation curve, phase adjustment is carried out on the parallel clock signals; step 6: and repeating the steps 1 to 5 for other channels to be processed. The scheme provided by the invention has the advantages of low resource consumption and high precision, and each channel can flexibly adjust the time delay according to the requirement after the alignment is finished.
Description
Technical Field
The present invention relates to the field of high-speed serial transceivers, and more particularly, to a clock phase alignment method and circuit for a high-speed serial transceiver.
Background
FPGAs are large integrators of digital circuits, and can generate a variety of digital pulses through their large number of general-purpose input/output pins. However, due to the limitations of the global clock speed of FPGAs, the clock speed of this direct pulse generation approach has long been limited to 400MHz to below 500 MHz. With the increasing field of application of high-speed pulses with clock speeds exceeding 1GHz, high-speed serial transceivers integrated with FPGAs have been targeted for generating such high-speed pulses.
Referring to fig. 1, a schematic diagram of a multi-channel high-speed serial transceiver is shown. The high-speed serial transceiver transmits the parallel data bit by bit at a higher clock speed in a serial manner at a transmitting party, and converts the data into the parallel data after receiving the data bit by bit at a receiving party, so that the communication speed is greatly improved. At present, the speed and the channel number of a high-speed serial transceiver integrated in an FPGA chip are both greatly improved. Taking the product of sailing corporation as an example, the high-end FPGA chips, such as the ultra scale series, have been able to provide GTY transceivers with line rates of over 100 channels up to 32.75Gb/s, while multi-channel GTX transceivers of over 10G/s have also become popular in many of the lower-end products. In addition, the existing high-speed serial transceivers integrate phase interpolation, and can achieve picosecond-level adjustment precision. The characteristics of high speed and multiple channels are matched with the characteristic of high adaptability of the FPGA, so that the high-speed serial transceiver integrated in the FPGA is applied to more and more fields except data communication.
The core part of the data transmitting end of the high-speed serial transceiver is a high-speed parallel-serial converter which serializes the coded parallel data and transmits the serialized data. The parallel-serial converter is divided into a parallel input side and a serial output side, and clocks on the two sides are respectively a parallel clock signal (XCLK) and a serial clock Signal (SCLK). SCLK is typically multiplied by a low frequency clock signal (REFCLK) through a Phase Locked Loop (PLL). Since SCLK is typically very high in frequency, it is not typically shared between multiple high-speed serial transceivers, but rather is used independently of each other. XCLK is typically a division of SCLK with a definite phase relationship between them. In addition to SCLK and XCLK, each high speed serial transceiver typically also has a clock signal (txuscrclk 2), also generated by REFCLK through a clock management unit similar to a PLL, for transmitting parallel data to the high speed serial transceiver. Since multiple PLLs are separated and each PLL is not locked at the same time, and the frequency dividers are not started to operate at the same time, the XCLK between different channels has random phase difference at the time of power-up.
For typical serial communications, each channel can be operated independently, and the random phase difference described above is not a problem. However, in the field of high-speed pulse generation, pulses of multiple channels are generally required to be added together in a certain form, so that the problem of phase alignment among the multiple channels needs to be solved, and the time deviation among the channels meets very strict limits. For example, in a high-speed quantum key distribution experiment, a plurality of high-speed serial transceivers are needed to generate high-speed pulse patterns of a plurality of channels to respectively drive a plurality of lasers or electro-optical modulators and then to obtain multi-amplitude and multi-phase modulated optical signals through beam combination, or high-speed pulse signals generated by the plurality of high-speed serial transceivers are firstly combined into a multi-amplitude electrical pulse signal and then to drive one laser or electro-optical modulator. In a quantum key distribution system with repetition frequencies above 1GHz, the time skew between the individual participating serial transceiver channels cannot exceed 10 ps.
The existing phase alignment methods still have some drawbacks. For example, the company sailing offers a built-in multi-channel auto-alignment function for the FPGA produced by the company sailing, which forcibly aligns XCLK of all channels to a rising edge, but the alignment precision is poor and it is not flexible to adjust the phase difference between the channels as required. H.B Xie et al propose a scheme for achieving multi-channel alignment using a Time To Digital Converter (TDC). According to the scheme, firstly, a high-precision TDC is built by using logic resources in the FPGA, then the TDC is used for measuring the time difference between each channel and a main channel, and then the phase of each channel is moved through a phase interpolator to compensate the time difference. The scheme has high precision, but needs to realize the high-precision TDC in the FPGA, and has the disadvantages of complex realization and more occupied resources.
It can be seen that how to provide a phase alignment circuit that has less resource consumption, high precision, and simple deployment, and can flexibly adjust the delay according to the requirement after the alignment of each channel is completed, has become a technical problem to be solved in the art.
Disclosure of Invention
The invention aims to provide a clock phase alignment method and a clock phase alignment circuit for a high-speed serial transceiver, so as to reduce resource consumption, improve alignment precision, reduce deployment difficulty and enable each channel to flexibly adjust delay as required after alignment is finished.
To achieve the above object, the present invention provides a clock phase alignment method for a high-speed serial transceiver, comprising:
step 1: sampling a parallel clock signal of one channel to be processed of the high-speed serial transceiver in N reference clock signal periods to obtain N sampling results, wherein the sampling results are first numerical values or second numerical values, the reference clock signal and the parallel clock signal are homologous clock signals, the reference clock signal period is an integral multiple of the parallel clock signal period, and N > 1;
step 2: determining a counting result according to the number of first numerical values in the N sampling results;
and step 3: adjusting the phase of the parallel clock signal for multiple times so as to add different delay time to the parallel clock signal, and repeating the step 1 and the step 2 after each adjustment so as to obtain a plurality of counting results with the numerical values from 0 to N, wherein each adjustment corresponds to different delay time;
and 4, step 4: drawing a relation curve of the delay time and the corresponding counting result;
and 5: according to the delay time corresponding to the rising edge or the falling edge of the relation curve, carrying out phase adjustment on the parallel clock signals so as to align the rising edge of the parallel clock signals of the channels with the rising edge of the reference clock signal;
step 6: and repeating the steps 1 to 5 for other channels to be processed so as to align the rising edges of the parallel clock signals of the channels.
In an embodiment, before step 1, the method further includes:
judging whether a buffer area exists between the parallel clock signal of the channel and the clock signal of the data coding circuit in the high-speed serial transceiver;
when a buffer is present, the phase of the parallel clock signals is adjusted until the value of the half-full indicator bit of the buffer changes from 0 to 1 for the first time.
In one embodiment, the delay time corresponding to the midpoint of the rising edge or the falling edge of the relationship curve is selected to perform phase adjustment on the parallel clock signals.
In one embodiment, the delay time corresponding to the rising edge or the falling edge of the relationship curve is determined by linear fitting or spline fitting.
In an embodiment, the counting result is cleared after each completion of step 2.
In another embodiment, after step 6, the method further comprises:
determining a fixed delay time difference between each channel, and performing phase adjustment on the parallel clock signals of each channel according to the fixed delay time difference when the channels are powered on each time so as to remove the fixed delay time difference;
or repeating the steps 1 to 5 for the output pulse signals of the respective channels to remove the fixed delay time difference.
The present invention also provides a clock phase alignment circuit for a high speed serial transceiver, comprising:
the first D flip-flop is used for sampling a parallel clock signal of one channel to be processed of the high-speed serial transceiver under the driving of a reference clock signal and outputting a sampling result, and is used for eliminating a metastable state, the sampling result is a first value or a second value, the reference clock signal and the parallel clock signal are homologous clock signals, and the period of the reference clock signal is an integral multiple of the period of the parallel clock signal;
the counter is electrically connected with the first D trigger and is used for receiving N sampling results obtained by the first D trigger in N reference clock signal periods, determining the number of first numerical values in the N sampling results and outputting a counting result;
and the phase shifter is used for adjusting the phase of the parallel clock signal for multiple times so as to add different delay time to the parallel clock signal, so that the counter outputs multiple counting results with the numerical values from 0 to N, and after a relation curve of the delay time and the corresponding counting result is obtained, the phase of the parallel clock signal is adjusted according to the delay time corresponding to the rising edge or the falling edge of the relation curve, so that the rising edge of the parallel clock signal of the channel is aligned with the rising edge of the reference clock signal.
In an embodiment, between the first D flip-flop and the counter, further comprising:
and a second D flip-flop for eliminating the metastable state.
In one embodiment, the method further comprises:
and the controller is electrically connected with the counter and used for controlling the counter to clear the counting result every N reference clock signal periods.
In another embodiment, when signals of multiple channels need to be added together to synthesize one channel of signal, the first D flip-flop is further configured to sample an output pulse signal of each channel, and the phase shifter is further configured to adjust a phase of the output pulse signal of each channel, so as to eliminate a fixed delay time difference between the channels.
The technical scheme provided by the invention can be seen that the alignment position is searched by adopting a counting rate counting method, so that the alignment precision is higher, the alignment error is far lower than the establishment holding time of the used FPGA and the random jitter of the related clock, and compared with the existing method adopting an FPGA built-in alignment circuit, the capability of continuously adjusting the delay of each channel according to the requirement is reserved by adopting the scheme provided by the invention.
Drawings
In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments described in the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a multi-channel high-speed serial transceiver;
FIG. 2 is a flow chart of a clock phase alignment method according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of a clock phase alignment circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of controlling phase alignment according to counting results by a computer;
fig. 5 is a graph of delay time versus count results obtained in a particular embodiment.
Detailed Description
The technical solutions of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments, it should be understood that these embodiments are merely illustrative of the present invention and are not intended to limit the scope of the present invention, and various equivalent modifications of the present invention by those skilled in the art after reading the present invention fall within the scope of the present invention defined by the appended claims.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
Referring to fig. 2, a clock phase alignment method for a high-speed serial transceiver includes:
step 1: in N reference clock signal periods, sampling a parallel clock signal of one channel to be processed of the high-speed serial transceiver to obtain N sampling results, wherein the sampling results are first numerical values or second numerical values, the reference clock signal and the parallel clock signal are homologous clock signals, the reference clock signal period is an integral multiple of the parallel clock signal period, and N > 1.
Specifically, the parallel clock signals of the channels may be sampled by D flip-flops, and the value of the sampling result is 0 or 1. For example, when the rising edge of the reference clock signal (txuscrclk 2) is aligned with the low level of the parallel clock signal (XCLK), each sample result is 0; when the rising edge of TXUSRCLK2 is aligned with the high level of XCLK, each sample result is a 1; when the rising edge of TXUSRCLK2 approaches the edge of XCLK, the sampling result is a random number of 0 and 1.
Step 2: and determining a counting result according to the number of the first numerical values in the N sampling results.
Specifically, the number of the N sampling results with a value of 1 may be counted to obtain a counting result.
In addition, after the step 2 is completed, the method also comprises the step of clearing the counting result.
And step 3: and adjusting the phase of the parallel clock signal for multiple times so as to add different delay time to the parallel clock signal, and repeating the step 1 and the step 2 after each adjustment so as to obtain a plurality of counting results with the numerical values from 0 to N, wherein each adjustment corresponds to different delay time.
Specifically, since the parallel clock signal (XCLK) is divided by the serial clock Signal (SCLK) such that the phase of XCLK changes with the change of the phase of SCLK, the phase of SCLK can be changed by a phase interpolator in the FPGA to adjust the phase of XCLK. Of course, the adjustment of the XCLK phase may also be achieved by a separate phase interpolator or phase shifter.
And 4, step 4: and drawing a relation curve of the delay time and the corresponding counting result.
Specifically, after a plurality of counting results with numerical values from 0 to N are obtained, a relationship curve between the delay time and the corresponding counting result is obtained by a method such as linear fitting or spline fitting.
And 5: and adjusting the phase of the parallel clock signal according to the delay time corresponding to the rising edge or the falling edge of the relation curve so as to align the rising edge of the parallel clock signal of the channel with the rising edge of the reference clock signal.
Specifically, the middle point of the rising edge or the falling edge of the relationship curve, that is, the delay time corresponding to the count result of 0.5N, may be selected to perform phase adjustment on the parallel clock signal.
Step 6: and repeating the steps 1 to 5 for other channels to be processed, so that the parallel clock signals of all the channels are aligned with the rising edge of the same reference clock signal, and the rising edges of the parallel clock signals of all the channels are aligned.
It can be seen that the present scheme can determine whether the edges of XCLK and TXUSRCLK2 are aligned by whether the D flip-flop samples a 0 or a 1. There are two factors that affect the alignment accuracy: the first factor is the random jitter (jitter) of the clock signal; the second factor is the setup hold time of the D flip-flop, which also makes the sampling result uncertain when the two clock edges are close. According to the scheme, by means of a method for counting a plurality of counting results, the uncertain factors can be averaged, and therefore the time precision of alignment is greatly improved.
In addition, before step 1, the following steps can be further included:
and judging whether a buffer area exists between the parallel clock signal of the channel and the clock signal of the data coding circuit in the high-speed serial transceiver.
When a buffer is present, the phase of the parallel clock signals is adjusted until the value of the half-full indicator bit of the buffer changes from 0 to 1 for the first time.
Further, after the above processing steps, there may still be a time difference between the data output by the channels, where the time difference is derived from the wiring difference between the channels and the routing difference in the FPGA, but the time difference is fixed and will not change with the system restart. In order to remove this fixed delay time difference, after step 6, the following steps may be further included:
and measuring by using a high-performance oscilloscope to determine a fixed delay time difference between the channels, and performing phase adjustment on the parallel clock signals of the channels according to the fixed delay time difference when the channels are powered on every time so as to remove the fixed delay time difference.
In another embodiment, when signals of multiple channels need to be added together to synthesize a single signal, the synthesized signal may be led back to the FPGA, and the XCLK sampled before may be replaced by the led-back signal. Each time the signal of one lane is turned on and the signals of the other lanes are set to low (0), then the same scan count, etc., alignment steps are performed as before, aligning the returned signal edge to the rising edge of TXUSRCLK 2. After these steps are performed for all channels in sequence, the superimposed signals will perform the phase alignment function. This procedure eliminates not only the random phase difference at each power-up, but also the fixed delay time difference between the channels, and no longer requires the fixed delay time difference to be measured by a high performance oscilloscope.
The present invention also provides a clock phase alignment circuit for a high speed serial transceiver, the circuit comprising:
the first D flip-flop is used for sampling a parallel clock signal of one channel to be processed of the high-speed serial transceiver under the driving of a reference clock signal and outputting a sampling result, and is used for eliminating a metastable state, the sampling result is a first value or a second value, the reference clock signal and the parallel clock signal are homologous clock signals, and the period of the reference clock signal is an integral multiple of the period of the parallel clock signal.
And the counter is electrically connected with the first D trigger and is used for receiving N sampling results obtained by the first D trigger in N reference clock signal periods, determining the number of first numerical values in the N sampling results and outputting a counting result.
And the phase shifter is used for adjusting the phase of the parallel clock signal for multiple times so as to add different delay time to the parallel clock signal, so that the counter outputs multiple counting results with the numerical values from 0 to N, and after a relation curve of the delay time and the corresponding counting result is obtained, the phase of the parallel clock signal is adjusted according to the delay time corresponding to the rising edge or the falling edge of the relation curve, so that the rising edge of the parallel clock signal of the channel is aligned with the rising edge of the reference clock signal.
Specifically, the phase shifter may be implemented using a separate phase interpolator, the counter may be implemented using a separate counter chip, and the D flip-flop may be implemented using a separate D flip-flop.
In addition, referring to the circuit structure diagram shown in fig. 3, a second D flip-flop may be further included between the first D flip-flop and the counter, for eliminating the metastable state. And the controller is connected with the counter and used for controlling the counter to clear the counting result every N reference clock signal periods. The phase locked loop and frequency divider of fig. 3 may be implemented by devices integrated within a high speed serial transceiver.
Referring to fig. 4, a phase value adjusted to the parallel clock signal is determined by outputting the counting result to a computer, and after the phase value is determined, the phase value is output so that the phase shifter adjusts the parallel clock signal according to the phase value.
In one embodiment, the method further comprises:
and the oscilloscope is used for measuring the fixed delay time difference of each channel to be processed.
In one embodiment, the method further comprises:
and the data fitting module is used for fitting the relation curve to determine the delay time corresponding to the rising edge or the falling edge of the relation curve.
In another embodiment, when signals of different channels need to be superimposed to synthesize one signal, the synthesized signal can be led back to the FPGA by using the circuit in the previous embodiment, and the XCLK sampled in the previous circuit is replaced by the led-back signal. The signal of one channel is opened and the signals of other channels are set to be low level (0) at a time, then the output pulse signal of the opened channel is sampled by the first D flip-flop, the phase of the output pulse signal of the channel is adjusted by the phase shifter, and therefore the same scanning counting and other alignment steps are carried out, and the returned signal edge is aligned to the rising edge of TXSRCLK 2. After the above processing is sequentially completed for all channels, the signals obtained after the superposition will complete the phase alignment function. This procedure eliminates not only the random phase difference at each power-up, but also the fixed delay time difference between the channels, and no longer requires the fixed delay time difference to be measured by an oscilloscope.
An embodiment of the present invention further provides a high-speed serial transceiver, which includes the clock phase alignment circuit.
An embodiment of the present invention further provides an FPGA, which includes the clock phase alignment circuit.
An embodiment of the present invention further provides an FPGA, which includes the high-speed serial transceiver.
In a specific embodiment, the serial clock signal SCLK is 5GHz, the parallel clock signal XCLK is 312.5MHz, the adjustment step size of the phase shifter is 1.5625 picoseconds (ps), and the relationship curve between the delay time and the counting result obtained by the phase alignment circuit provided by the present invention is as shown in fig. 5, and as can be seen from fig. 5, the point corresponding to the counting result of 0.5N in the curve is (565.8809,500000), so that the phase adjustment is performed on the parallel clock signal according to the delay time 565.8809 picoseconds.
The above embodiments in the present specification are all described in a progressive manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment is described with emphasis on being different from other embodiments.
The above description is only a few embodiments of the present invention, and although the embodiments of the present invention are described above, the above description is only for the convenience of understanding the technical scheme of the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method of clock phase alignment for a high speed serial transceiver, comprising:
step 1: sampling a parallel clock signal of one channel to be processed of the high-speed serial transceiver in N reference clock signal periods to obtain N sampling results, wherein the sampling results are first numerical values or second numerical values, the reference clock signal and the parallel clock signal are homologous clock signals, the reference clock signal period is an integral multiple of the parallel clock signal period, and N > 1;
step 2: determining a counting result according to the number of first numerical values in the N sampling results;
and step 3: adjusting the phase of the parallel clock signal for multiple times so as to add different delay time to the parallel clock signal, and repeating the step 1 and the step 2 after each adjustment so as to obtain a plurality of counting results with the numerical values from 0 to N, wherein each adjustment corresponds to different delay time;
and 4, step 4: drawing a relation curve of the delay time and the corresponding counting result;
and 5: according to the delay time corresponding to the rising edge or the falling edge of the relation curve, carrying out phase adjustment on the parallel clock signals so as to align the rising edge of the parallel clock signals of the channels with the rising edge of the reference clock signal;
step 6: and repeating the steps 1 to 5 for other channels to be processed so as to align the rising edges of the parallel clock signals of the channels.
2. The method of claim 1, further comprising, prior to step 1:
judging whether a buffer area exists between the parallel clock signal of the channel and the clock signal of the data coding circuit in the high-speed serial transceiver;
when a buffer is present, the phase of the parallel clock signals is adjusted until the value of the half-full indicator bit of the buffer changes from 0 to 1 for the first time.
3. The method of claim 1, further comprising, after step 6:
determining a fixed delay time difference between each channel, and performing phase adjustment on the parallel clock signals of each channel according to the fixed delay time difference when the channels are powered on each time so as to remove the fixed delay time difference;
or repeating the steps 1 to 5 for the output pulse signals of the respective channels to remove the fixed delay time difference.
4. The method of claim 1, wherein the delay time corresponding to the midpoint of the rising edge or the falling edge of the relationship curve is selected to perform the phase adjustment on the parallel clock signals.
5. The method according to claim 1, wherein the delay time corresponding to the rising edge or the falling edge of the relationship curve is determined by linear fitting or spline fitting.
6. The method of claim 1, wherein the count result is cleared after each completion of step 2.
7. A clock phase alignment circuit for a high speed serial transceiver, comprising:
the first D flip-flop is used for sampling a parallel clock signal of one channel to be processed of the high-speed serial transceiver under the driving of a reference clock signal and outputting a sampling result, and is used for eliminating a metastable state, the sampling result is a first value or a second value, the reference clock signal and the parallel clock signal are homologous clock signals, and the period of the reference clock signal is an integral multiple of the period of the parallel clock signal;
the counter is electrically connected with the first D trigger and is used for receiving N sampling results obtained by the first D trigger in N reference clock signal periods, determining the number of first numerical values in the N sampling results and outputting a counting result;
and the phase shifter is used for adjusting the phase of the parallel clock signal for multiple times so as to add different delay time to the parallel clock signal, so that the counter outputs multiple counting results with the numerical values from 0 to N, and after a relation curve of the delay time and the corresponding counting result is obtained, the phase of the parallel clock signal is adjusted according to the delay time corresponding to the rising edge or the falling edge of the relation curve, so that the rising edge of the parallel clock signal of the channel is aligned with the rising edge of the reference clock signal.
8. The circuit of claim 7, further comprising, between the first D flip-flop and the counter:
and a second D flip-flop for eliminating the metastable state.
9. The circuit of claim 7, further comprising:
and the controller is electrically connected with the counter and used for controlling the counter to clear the counting result every N reference clock signal periods.
10. The circuit of claim 7, wherein when signals of multiple channels need to be added together to synthesize a single signal, the first D flip-flop is further configured to sample an output pulse signal of each channel, and the phase shifter is further configured to adjust a phase of the output pulse signal of each channel to eliminate a fixed delay time difference between the channels.
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| CN116795765A (en) * | 2023-08-29 | 2023-09-22 | 芯耀辉科技有限公司 | Data alignment method and device for high-speed data transmission |
| CN116795765B (en) * | 2023-08-29 | 2023-12-08 | 芯耀辉科技有限公司 | Data alignment method and device for high-speed data transmission |
| CN116954306A (en) * | 2023-09-20 | 2023-10-27 | 芯动微电子科技(珠海)有限公司 | Clock phase shifting method and device |
| CN116954306B (en) * | 2023-09-20 | 2024-01-02 | 芯动微电子科技(珠海)有限公司 | Clock phase shifting method and device |
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