CN116169214A - Display panel packaging system and packaging method - Google Patents

Display panel packaging system and packaging method Download PDF

Info

Publication number
CN116169214A
CN116169214A CN202310311604.7A CN202310311604A CN116169214A CN 116169214 A CN116169214 A CN 116169214A CN 202310311604 A CN202310311604 A CN 202310311604A CN 116169214 A CN116169214 A CN 116169214A
Authority
CN
China
Prior art keywords
display panel
sensing information
display
substrate
pixel circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310311604.7A
Other languages
Chinese (zh)
Inventor
纪彦廷
林凯俊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AU Optronics Corp
Original Assignee
AU Optronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AU Optronics Corp filed Critical AU Optronics Corp
Publication of CN116169214A publication Critical patent/CN116169214A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L21/603—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving the application of pressure, e.g. thermo-compression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67121—Apparatus for making assemblies not otherwise provided for, e.g. package constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Control Of El Displays (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

The invention discloses a display panel packaging system and a packaging method. The display panel packaging system comprises a display panel, a jointing device, a testing device and a controller. The display panel comprises a plurality of pixel circuits and a substrate. The substrate is provided with a plurality of wires which are matched with the pixel circuits and are used for providing electric connection of the pixel circuits. The bonding apparatus is used for applying pressure to bond the pixel circuits to the substrate to form a display array on the substrate. The testing device is electrically coupled to the display array. The test device is used for testing the display array and receiving the sensing information from the display array. The controller is coupled to the bonding apparatus and the testing apparatus. During the bonding of the display panel, the controller controls the bonding apparatus according to the sensing information to adjust the pressure applied to the display panel.

Description

Display panel packaging system and packaging method
Technical Field
The present invention relates to a system and a method, and more particularly, to a system and a method for packaging a display panel.
Background
When the existing display panel is produced, the control paths which possibly generate defects in each pixel circuit are often required to be detected one by one, so that the detection flow is repeated and complicated. Finally, the whole panel is lightened after the bonding, and whether the bonding process is damaged or other undetected defective pixel circuits are detected. Thereby lengthening the required production time of the display panel as a whole.
Disclosure of Invention
The invention provides a display panel packaging system and a packaging method, which can sense a pixel circuit in real time during bonding.
The display panel packaging system comprises a display panel, a jointing device, a testing device and a controller. The display panel comprises a plurality of pixel circuits and a substrate. The substrate is provided with a plurality of wires which are matched with the pixel circuits and are used for providing electric connection of the pixel circuits. The bonding apparatus is used for applying pressure to bond the pixel circuits to the substrate to form a display array on the substrate. The testing device is electrically coupled to the display array. The test device is used for testing the display array and receiving the sensing information from the display array. The controller is coupled to the bonding apparatus and the testing apparatus. During the bonding of the display panel, the controller controls the bonding apparatus according to the sensing information to adjust the pressure applied to the display panel.
The packaging method of the invention can be used for display panels. The display panel comprises a plurality of pixel circuits and a substrate. The substrate is provided with a plurality of wires formed by matching with the pixel circuits so as to provide electric connection of the pixel circuits. The packaging method comprises applying pressure to bond the pixel circuit to the substrate to form a display array on the substrate; testing the display array and receiving sensing information by the display array; and adjusting the pressure applied to the display panel according to the sensing information during the bonding process of the display panel.
Based on the above, the display panel packaging system and the packaging method of the present invention can perform sensing while the pixel circuits are bonded to adjust the bonding pressure. Further, after the bonding operation of the display array is completed, a test may be further performed for each display pixel to mark the defective pixel circuit for subsequent elimination.
Drawings
FIG. 1 is a schematic block diagram of a display panel packaging system according to the present invention;
FIG. 2 is a schematic diagram of a testing apparatus for testing pixel circuits to obtain sensing information according to an embodiment of the present invention;
FIG. 3 is a flow chart of a packaging method according to an embodiment of the invention;
FIG. 4 is a perspective view of a pixel circuit with horizontal offset according to an embodiment of the invention;
FIG. 5 is a schematic diagram of a defective pixel circuit according to an embodiment of the invention.
Symbol description
1: display panel packaging system
10: controller for controlling a power supply
11: joining apparatus
12: test equipment
13: display panel
50: watch (watch)
120: probe with a probe tip
130: display array
131: substrate board
C1: capacitance device
D1: diode
Din: displaying data
DX: distance of
EM: laser signal
P1 to P3: control path
PX: pixel circuit
RST: reset signal
S30-S32: step (a)
SC: scanning signal
Sc_r: scanning reset signal
SI: sensing information
T1 to T5: transistor with a high-voltage power supply
VDD: operating voltage
VR1, VR2: reference voltage
VSS: ground voltage
Detailed Description
Fig. 1 is a schematic block diagram of a display panel packaging system 1 according to the present invention. The display panel packaging system 1 includes a controller 10, a bonding apparatus (bonding) 11, a test apparatus (tester) 12, and a display panel 13. In general, the display panel 13 includes a plurality of pixel circuits PX and a substrate (not shown in fig. 1) for carrying the pixel circuits PX. Patterned wires formed in cooperation with the pixel circuits PX are disposed on the substrate to provide electrical connection of the pixel circuits PX. The bonding apparatus 11 may apply pressure to bond the pixel circuits PX to the substrate, and form the display array 130 on the substrate. The testing device 12 is electrically coupled to the display array 130, and the testing device 12 can be used for testing the display array 130 and receiving the corresponding sensing information SI from the display array 130. The controller 10 is coupled to the bonding apparatus 11 and the testing apparatus 12, and the controller 10 can control the bonding apparatus 12 according to the sensing information SI to adjust the pressure applied to the display panel 13 during the bonding process of the display panel 13.
Specifically, since the patterned wires formed in cooperation with the pixel circuits PX are provided on the substrate of the display panel 13, each pixel circuit PX needs to be bonded to a corresponding position of each pixel circuit PX by the bonding apparatus 11, and each pixel circuit PX can be driven to display in the display array 130 through the patterned wires. In the process of bonding the pixel circuits PX, the bonding apparatus 11 bonds the pixel circuits PX by applying a pressure to the pixel circuits PX, and an excessive or insufficient pressure may cause a difference in electrical connection between the pixel circuits PX and the substrate, thereby generating a scratch defect (mura) on the display panel 13 and affecting the display quality of the display panel 13.
In some embodiments, the display panel packaging system 1 may improve the display quality of the display panel 13 by providing the bonding apparatus 11 and the testing apparatus 12 in cooperation with the bonding of the display panel 13. Specifically, the display panel packaging system 1 may perform a test on the pixel circuits PX under bonding by the test device 12 to obtain the corresponding sensing information SI when the bonding device 11 bonds the pixel circuits PX to the substrates. Thus, the controller 10 of the display panel packaging system 1 can control the bonding apparatus 11 according to the sensing information SI, so that the bonding apparatus 11 performs bonding of the display panel 13 with an appropriate pressing force.
Fig. 2 is a schematic diagram of a test apparatus 12 for testing a pixel circuit PX to obtain sensing information SI according to an embodiment of the present invention. In detail, the test apparatus 12 includes a probe 120 or a probe card (probe card). The test device 12 may be directly contacted to a pad (pad) of the display panel 13 through the probe 120 to perform signal transmission with each pixel circuit PX in the display array 130, and implement the test of the display array 130.
In some embodiments, the pixel circuit PX includes transistors T1 to T5, a capacitor C1, and a diode D1. The transistors T1 and T2 and the diode D1 are sequentially connected in series between the operating voltage VDD and the ground voltage VSS. The transistor T1 may be controlled by the laser signal EM to be turned on (conductor) or off (cutoff) to selectively supply current to drive the diode D1.
The transistors T3 to T5 and the capacitor C1 of the pixel circuit PX may form control paths P1 to P3, and control the driving of the diode D1 in combination with the transistors T1 and T2. Mainly, the image display of the pixel circuit PX is controlled by the control path P2. The control path P2 includes a transistor T4 coupled to the gate of the transistor T2, and the transistor T4 receives the display data Din at one end and provides the display data Din to the gate of the transistor T2 according to the control of the scan signal SC. Further, a capacitor C1 of the pixel circuit PX is coupled between the gate and the source of the transistor T2, and can be used to store the display data Din provided through the control path P2. In this way, the pixel circuit PX can store the display data in the capacitor C1 through the control path P2, and accordingly control the driving current flowing through the transistor T2, so that the diode D1 generates the display luminance corresponding to the display data Din.
In order to maintain the display quality, the control paths P1 and P3 respectively coupled to the two ends of the capacitor C1 can be used to reset the voltage across the capacitor C1. In detail, the control path P1 includes a transistor T3 coupled to the upper plate of the capacitor C1 and the gate of the transistor T2. The transistor T3 is controlled by the scan reset signal sc_r, and selectively provides the reference voltage VR1 to the upper plate of the capacitor C1 and the gate of the transistor T2. In addition, the control path P3 includes a transistor T5 coupled to the lower plate of the capacitor C1, the source of the transistor T2, and the anode of the diode D1. The transistor T5 is controlled by the reset signal RST to selectively provide the reference voltage VR1 to the upper plate of the capacitor C1 and the node between the transistor T2 and the diode D1.
Therefore, if the pixel circuit PX performs an ideal display operation according to control, it is necessary to rely on that all the control paths P1 to P3 are ideally connected. When excessive or excessive pressure is applied during the bonding process, the control paths P1 to P3 are not operated normally, and defective pixel circuits PX are generated.
In some embodiments, the test device 12 may detect the control paths P1-P3 in the pixel circuits PX by testing the pads for the incoming reference signal VR1, the display data Din, and the reference signal VR2 to the pixel circuits PX, respectively. However, in this embodiment, it takes time to perform multiple determinations for a single pixel circuit PX to confirm whether the connection of the control paths P1 to P3 is ideal, and it is not possible to eliminate the abnormal coupling between the transistors T1 and T2 and the diode D1.
In some embodiments, the test apparatus 12 may perform the test only for the pad that the ground voltage VSS is input to the pixel circuit PX. Specifically, any one of the control paths P1 to P3 is abnormal, which affects the driving current received by the diode D1 and causes abnormal display of the display pixel PX. Therefore, the test device 12 can perform a single test on the pad of the pixel circuit PX to which the ground voltage VSS is applied, rather than performing separate and multiple tests on the control paths P1-P3, so as to effectively determine whether the connection structure of the pixel circuit PX is abnormal, including the connection of the control paths P1-P3, and even the transistors T1 and T2 and the diode D1 connected in series. Therefore, by testing the pad of the display panel 13 receiving the ground voltage VSS and receiving the sensing information SI, it is possible to quickly and effectively evaluate whether the pixel circuit PX is defective or not.
Of course, the pixel circuit PX shown in fig. 2 is only one example of various embodiments, and is used to illustrate the defect cause and the effective detection mode in the pixel circuit PX, and should not be construed as limiting the embodiment of the pixel circuit PX. Those skilled in the art will recognize that various modifications and variations of the pixel circuit PX can be made according to different design requirements, and the invention is also applicable to various embodiments of the pixel circuit PX.
Fig. 3 is a flowchart of a packaging method according to an embodiment of the invention. The packaging method is applicable to, for example, the display panel packaging system 1 of fig. 1.
In step S30, the bonding apparatus 11 may apply pressure on the pixel circuits PX to bond the pixel circuits PX to corresponding positions of the substrate. In this way, the patterned conductive lines on the substrate may be connected to the corresponding nodes in each pixel circuit PX, so as to provide data transmission for the pixel circuits PX during the display operation.
In step S31, while the bonding apparatus 11 presses down and bonds the pixel circuits PX on the substrate by providing pressure, the testing apparatus 12 may perform a test on the display array 130 and receive the sensing information SI by the display array 130. Specifically, the test apparatus 12 may sense the display pixels PX through the pads of the display array 130 receiving the ground voltage VSS, and receive the sensing information SI.
In step S32, the controller 10 of the display panel packaging system 1 may control the bonding apparatus 11 according to the sensing information SI to adjust the pressure applied by the bonding apparatus 11. In detail, the joining apparatus 11 may gradually increase the pressure applied thereto over time during the joining process. The test device 12 can continuously monitor the display pixels PX in the display array 130 in real time during the bonding process of increasing pressure, and provide the sensed sensing information to the controller 10, so that the controller 10 can adjust the pressure applied by the bonding device 11 according to the intensity of the sensing information SI.
In some embodiments, during the increasing process of the pressure applied by the bonding apparatus 11, the controller 10 may determine whether the intensity of the sensing information SI falls within a preset intensity range, thereby determining whether the pressure applied by the bonding apparatus 11 is suitable for bonding the pixel circuit PX on the substrate of the display panel 13, so that the pixel circuit PX has a good electrical connection with the patterned conductive line on the substrate to perform the display operation of the display array 130. In detail, since the test device 12 tests the pixel circuit PX by providing the ground voltage VSS to the pad of the display array 130, the test device 12 can receive the magnitude of the current flowing through the diode D1 of the pixel circuit PX and provide it as the sensing information SI to the controller 10. In this way, the controller 10 can determine whether the magnitude of the current flowing through the diode D1 in the pixel circuit PX falls within the predetermined current range. When the controller determines that the intensity of the sensing information SI (i.e., the magnitude of the current flowing through the diode D1 in the pixel circuit PX) falls within the preset intensity range, the controller 10 may control the bonding apparatus 10 to record the magnitude of the pressure and suspend the increase of the pressure. Further, the controller 10 performs the bonding of the other pixel circuits PX with the recorded pressure. In this way, the display panel packaging system 1 can obtain a proper pressure value by monitoring the bonding process of the display pixels PX, so as to bond the entire display array 130.
In some embodiments, the controller 10 may, for example, monitor the bonding process of one or more pixel circuits PX to obtain one or more recorded pressure values, and control the bonding of the overall display array 130 with an average of the one or more recorded pressure values.
However, in the display panel packaging system 1, the process of adjusting the pressure value by monitoring the bonding process is improved in that the vertical offset between the pixel circuit PX and the substrate is made such that the vertical distance between the pixel circuit PX and the substrate can be fixed. But in some cases, there may also be a horizontal offset between the pixel circuits PX and the substrate.
Fig. 4 is a perspective view of a pixel circuit PX with a horizontal offset according to an embodiment of the present invention. In the present embodiment, the pixel circuit PX is disposed on the substrate 131 and horizontally offset from the predetermined setting position thereof by a distance DX, so that the contact area between the pixel circuit PX and the connection structure disposed on the substrate 131 becomes smaller, which results in a change of the resistance of the pixel circuit PX, thereby affecting the display operation.
In some embodiments, the packaging method shown in fig. 3 may further perform the inspection for each pixel circuit PX after step S32, that is, after the bonding operation of the entire display array 130 is completed with the recorded pressure.
In detail, after the pixel circuits PX are bonded to the substrate, the controller 10 may test each pixel circuit PX of the display array to obtain the sensing information SI corresponding to each pixel circuit. Further, the controller 10 may compare the intensity of the sensing information SI with a preset intensity range, and mark the pixel circuits PX corresponding to the sensing information not falling within the preset intensity range.
Fig. 5 is a schematic diagram of a table 50 of defective pixel circuits PX according to an embodiment of the present invention. The table 50 shows the different defect types, as well as the display data provided and the measured intensity of the sensed information SI when detected. As can be seen from the table 50, the controller 10 may, for example, compare the measured current value with a preset current range and mark the pixel circuits PX which do not fall within the preset current range as defective pixel circuits PX. These defects may be caused by the variation of the resistance of the current connection structure inside the pixel circuit PX due to the horizontal or vertical offset between the pixel circuit PX and the substrate, and thus the driving current flowing through the internal diode D1 of the pixel circuit PX with these defects is too large or too small. Therefore, the controller 10 compares the intensity of the sensing information SI with the preset intensity range, determines the sensing information SI with the excessive or insufficient intensity of the sensing information SI as abnormal, and marks the pixel circuits PX corresponding to the sensing information SI, so as to facilitate the subsequent replacement repair.
Since the display panel packaging system 1 and the packaging method perform the test of each pixel circuit PX after the bonding operation of the display array 130 is completed, the operation sequence may take the offset that may be caused by the bonding operation to each pixel circuit PX into consideration. Compared with the prior art that the test of each pixel circuit PX is performed before the bonding operation, the test of the pixel circuits PX is arranged after the bonding operation, and the defective pixel circuits PX in the display panel 13 due to various causes can be detected by only one test operation, so as to avoid repeated detection.
In summary, the display panel packaging system and the packaging method of the present invention can sense the pixel circuits while bonding to adjust the bonding pressure. Further, after the bonding operation of the display array is completed, a test may be further performed for each display pixel to mark the defective pixel circuit for subsequent elimination.

Claims (10)

1. A display panel packaging system, comprising:
a display panel, comprising:
a plurality of pixel circuits; and
the substrate is provided with a plurality of wires which are matched with the pixel circuits and are used for providing electric connection of the pixel circuits;
bonding means (bonding) for bonding the pixel circuits to the substrate by applying pressure to form a display array on the substrate;
the testing equipment is electrically coupled to the display array and used for testing the display array and receiving sensing information from the display array; and
and the controller is coupled with the jointing equipment and the testing equipment, and controls the jointing equipment according to the sensing information in the jointing process of the display panel so as to adjust the pressure applied to the display panel.
2. The display panel packaging system of claim 1, wherein the pressure applied to the display panel by the bonding apparatus increases during bonding of the display panel.
3. The display panel packaging system of claim 2, wherein the controller determines whether the intensity of the sensing information falls within a predetermined intensity range during the increasing of the pressure,
when the controller judges that the intensity of the sensing information falls into the preset intensity range, the controller controls the jointing equipment to record and pause the gradual increase of the pressure, and the pixel circuits are jointed to the substrate by the recorded pressure.
4. The display panel packaging system of claim 1, wherein after the pixel circuits are bonded to the substrate, the controller tests the display array to obtain the sensing information corresponding to each pixel circuit, and marks the pixel circuit corresponding to the sensing information when the intensity of the sensing information does not fall within a predetermined intensity range.
5. The display panel packaging system of claim 1, wherein the test device is a pad receiving a ground voltage from the display array to receive the sensing information.
6. A packaging method is used for a display panel, the display panel comprises a substrate and a plurality of pixel circuits, the substrate is provided with a plurality of wires which are matched with the pixel circuits and are used for providing electric connection of the pixel circuits, and the packaging method comprises the following steps:
applying pressure to bond the pixel circuits to the substrate to form a display array on the substrate;
testing the display array and receiving sensing information by the display array; and
during the bonding process of the display panel, the pressure applied to the display panel is adjusted according to the sensing information.
7. The packaging method of claim 6, comprising:
during the bonding of the display panels, the pressure applied to the display panels is controlled to be increased.
8. The packaging method of claim 6, comprising:
in the increasing process of the pressure, judging whether the intensity of the sensing information falls into a preset intensity range,
when the intensity of the sensing information is judged to fall into the preset intensity range, the increasing of the pressure is recorded and stopped, and the pixel circuits are connected to the substrate by the recorded pressure.
9. The packaging method of claim 7, further comprising:
after the pixel circuits are bonded to the substrate, the display array is tested to obtain the sensing information corresponding to each pixel circuit, and the pixel circuit corresponding to the sensing information is marked when the intensity of the sensing information does not fall into a preset intensity range.
10. The packaging method of claim 6, further comprising receiving a ground voltage from the display array and receiving the sensing information from the display panel.
CN202310311604.7A 2022-11-16 2023-03-28 Display panel packaging system and packaging method Pending CN116169214A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW111143747A TW202423272A (en) 2022-11-16 2022-11-16 Display panel packaging system and a packaging method
TW111143747 2022-11-16

Publications (1)

Publication Number Publication Date
CN116169214A true CN116169214A (en) 2023-05-26

Family

ID=86422112

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310311604.7A Pending CN116169214A (en) 2022-11-16 2023-03-28 Display panel packaging system and packaging method

Country Status (2)

Country Link
CN (1) CN116169214A (en)
TW (1) TW202423272A (en)

Also Published As

Publication number Publication date
TW202423272A (en) 2024-06-01

Similar Documents

Publication Publication Date Title
KR100818563B1 (en) Method of testing for display panel and the device thereof
CN101847357A (en) Display panel, display device and test method thereof
JPH0472552A (en) Thin film transistor base and method and device for inspecting it
KR102103840B1 (en) System and method of testing organic light emitting display device capable of testing automatically contact between probe and pad
JP2005043783A (en) Device for inspecting liquid crystal display panel, and method for inspecting liquid crystal panel
CN116169214A (en) Display panel packaging system and packaging method
JPH1184420A (en) Liquid crystal display device, array substrate test method and tester for array substrate
CN115938255A (en) Display detection device, detection method and detection system
US7518601B2 (en) Array substrate and display apparatus and method for manufacturing display apparatus
CN100354918C (en) Flat display apparatus and flat display apparatus testing method
WO2017168530A1 (en) Inspection method and inspection system for wiring path of substrate
US20020180467A1 (en) Inspection method and inspection apparatus for semiconductor circuit
KR102303929B1 (en) Inspection equipment for inspecting micro-led
KR20210142966A (en) Substrate inspection device
KR102070056B1 (en) System and method of testing organic light emitting display device
JP2002310933A (en) Apparatus and method for inspection of circuit board as well as electro-optical element
CN221406750U (en) Display panel and display testing device
CN114994511B (en) Bonding tester, bonding testing method and bonding testing device
KR101904550B1 (en) A System and Method for Inspection of Electrical Circuits
JP4585344B2 (en) Circuit board inspection apparatus and circuit board inspection method
KR100671342B1 (en) Apparatus and method for inspecting electricity-driven device
JPH087349B2 (en) Liquid crystal display panel inspection device and inspection method thereof
KR20090068602A (en) Apparatus for electrical die sorting, method for measuring planarity of needle
KR20070109357A (en) Liquid crystal display panel testing device and testing method thereof
KR20170009212A (en) Probe unit for image display pannel inspection

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination