CN116165523B - Integrated circuit multi-chip joint test method and device - Google Patents
Integrated circuit multi-chip joint test method and device Download PDFInfo
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- CN116165523B CN116165523B CN202310462571.6A CN202310462571A CN116165523B CN 116165523 B CN116165523 B CN 116165523B CN 202310462571 A CN202310462571 A CN 202310462571A CN 116165523 B CN116165523 B CN 116165523B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2896—Testing of IC packages; Test features related to IC packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
Abstract
The application discloses an integrated circuit multi-chip joint test method and device, wherein a traditional display packaging unit is split into a first display packaging subunit containing an LED chip and a second display packaging subunit containing a unit control chip, and detection is respectively carried out to reduce the replacement cost of dead pixels. The piezoelectric effect through piezoceramics layer detects first demonstration encapsulation subunit, and whole testing process only need aim at press the back observe the LED chip whether light can, easy operation has improved detection efficiency greatly. And each control pin of the unit control chip in the second display packaging subunit is detected through the same LED wafer block, so that the detection efficiency is also improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a method and an apparatus for testing multiple chips of an integrated circuit.
Background
In order to improve the production efficiency and the production yield of the Micro-LED display, a person skilled in the art thinks that the red, green and blue LED chips and the unit control chip are packaged in the same display packaging unit, and in the subsequent display production process, only the display packaging units are required to be arranged on corresponding circuit boards one by one.
Before the display packaging units are welded on the circuit board, the display packaging units need to be detected one by one, and as the display packaging units are integrated with more elements, whether the display packaging units are faulty or not can only be judged, and whether the fault causes come from the LED chips or the unit control chips is difficult to judge. When a defective pixel is found, the whole display packaging unit needs to be replaced, and the replacement cost for the defective pixel is high.
Disclosure of Invention
The present invention is directed to a method and apparatus for integrated circuit multi-chip joint testing, which can improve the above-mentioned problems.
Embodiments of the present application are implemented as follows:
in a first aspect, the present application provides a method for integrated circuit multi-chip joint testing, comprising:
s1, providing a first display packaging subunit and a second display packaging subunit, wherein the first display packaging subunit comprises a first circuit board and at least one LED chip arranged on the first circuit board, and the second display packaging subunit comprises a second circuit board and a unit control chip arranged on the second circuit board;
s2, providing a first testing device, wherein the first testing device comprises a first substrate and a piezoelectric ceramic layer welded on the first substrate;
s3, the first display packaging subunit is contacted with the first testing device, and the first display packaging subunit is extruded towards the first testing device to detect whether the first display packaging subunit is qualified or not;
s4, providing a second testing device, wherein the second testing device comprises a second substrate and an LED wafer block welded on the second substrate;
s5, the second display packaging subunit is contacted with the second testing device, so that each control pin and each power pin of the unit control chip are respectively contacted with two poles of the LED wafer block, and driving signals are input to the scanning line pins and the data line pins of the unit control chip to detect whether the second display packaging subunit is qualified or not.
It can be appreciated that the application provides an integrated circuit multi-chip joint test method, in which a traditional display packaging unit is split into a first display packaging subunit containing an LED chip and a second display packaging subunit containing a unit control chip, and the detection is performed respectively to reduce the replacement cost of dead pixels. The piezoelectric effect through piezoceramics layer detects first demonstration encapsulation subunit, and whole testing process only need aim at press the back observe the LED chip whether light can, easy operation has improved detection efficiency greatly. And each control pin of the unit control chip in the second display packaging subunit is detected through the same LED wafer block, so that the detection efficiency is also improved.
In an alternative embodiment of the present application, in the first display package subunit, the LED chips are disposed on a front surface of the first circuit board, a first groove is disposed on a back surface of the first circuit board, a driving contact pad connected to a negative electrode of each LED chip is disposed in the first groove, and a non-first groove area on the back surface of the first circuit board is disposed with a positive electrode contact pad connected to a positive electrode of each LED chip;
in the second display packaging subunit, a boss matched with the first groove is formed in the center of the front surface of the second circuit board, the unit control chip is arranged on the back surface of the second circuit board, control contact discs corresponding to the driving contact discs are arranged on the boss, the control contact discs are respectively connected with the control pins of the unit control chip, and a power contact disc corresponding to the positive electrode contact disc is arranged in a non-boss area of the front surface of the second circuit board, wherein at least one power contact disc is connected with the power pins of the unit control chip; and the back surface of the second circuit board is also provided with a power electrode connected with each power contact pad, a grounding electrode connected with a grounding pin, a scanning line electrode connected with the scanning line pin and a signal line electrode connected with the data line pin.
Optionally, the inner side wall of the first groove is provided with a first magnet, and the outer side wall of the boss is provided with a second magnet with magnetism opposite to that of the first magnet.
It will be appreciated that the provision of the first and second magnets is to facilitate the incorporation of the first and second display package subunits such that the first recess and boss can be more easily and effectively aligned.
In an alternative embodiment of the present application, the method further comprises:
s6, providing a display circuit board;
s7, selecting the qualified second display packaging subunit, and welding a power electrode, a ground electrode, a scanning line electrode and a signal line electrode of the second display packaging subunit on corresponding electrode pads on the display circuit board;
s8, selecting the qualified first display packaging subunit, and covering the first groove of the first display packaging subunit with the boss of the corresponding second display packaging subunit;
and S9, respectively welding each driving contact pad on the corresponding control contact pad, and welding the positive contact pad on the corresponding power contact pad.
It can be understood that after the first display packaging subunit and the second display packaging subunit are correspondingly welded, the unit control chip can correspondingly control the lighting time and the brightness of each LED chip through each control pin, so that the first display packaging subunit and the second display packaging subunit are combined into a complete display packaging unit.
In an optional embodiment of the present application, in the first test device, the first substrate is a metal substrate, a first metal layer and a second metal layer are respectively disposed on two opposite side surfaces of the piezoelectric ceramic layer, the first metal layer is welded to the first substrate, a cross-sectional dimension of the piezoelectric ceramic layer is smaller than the first groove, and a height of the piezoelectric ceramic layer is smaller than or equal to a depth of the first groove.
The step S3 comprises the following steps:
s31, covering the corresponding piezoelectric ceramic layer by the first groove of the first display packaging subunit to be tested, so that the positive electrode contact plate is contacted with the first substrate while the driving contact plates are contacted with the second metal layer;
s32, extruding the first display packaging subunit towards the first testing device to enable the piezoelectric ceramic layer to deform to generate a piezoelectric effect;
and S33, judging that the first display packaging subunit is qualified when all the LED chips in the first display packaging subunit are lighted, and judging that the first display packaging subunit is unqualified when all the LED chips in the first display packaging subunit are not lighted.
It can be understood that when the first display package subunit is detected, the first display package subunit is pressed towards the first testing device, so that the piezoelectric ceramic layer deforms to form charges on the surface, and the LED chip is lightened through the positive electrode contact pad connected with the positive electrode of the LED chip and the driving contact pads connected with the negative electrode of the LED chip respectively. If the first display packaging subunit has an LED chip which is not lightened, the first display packaging subunit can be judged to be a dead pixel, and the first display packaging subunit is replaced. The piezoelectric effect through piezoceramics layer detects first demonstration encapsulation subunit, and whole testing process only need aim at press the back observe the LED chip whether light can, easy operation has improved detection efficiency greatly.
In an optional embodiment of the present application, in the second testing device, a second groove matched with the boss is formed on the second substrate, a third metal layer is formed on the surface provided with the second groove, a first electrode and a second electrode are disposed on two opposite side surfaces of the LED wafer block, the first electrode is welded on the third metal layer, and the sum of the thickness of the LED wafer block and the thickness of the boss is greater than or equal to the depth of the second groove.
The step S5 comprises the following steps:
inserting the boss of the second display packaging subunit to be tested into the corresponding second groove, so that the power contact pad is contacted with the third metal layer while each control contact pad is contacted with the second electrode;
driving signals are input to scanning line pins and data line pins of the unit control chip, and each control pin is sequentially controlled to drive the LED wafer blocks to light;
and judging that the second display packaging subunit is qualified under the condition that the LED wafer block is lightened, and judging that the second display packaging subunit is unqualified under the condition that the LED wafer block is not lightened.
It will be appreciated that upon detection of the second display package subunit, the power contact pads of the second display package subunit are brought into contact with the first electrodes of the LED die paddle and the respective control contact pads are brought into contact with the second electrodes of the LED die paddle; and then, driving signals are input to the scanning line pins and the data line pins of the unit control chip through the probes, and each control pin is controlled to drive the LED wafer blocks to light in sequence. In this process, if the LED wafer block does not respond to the driving signal output by the probe and is not turned on, it may be determined that the second display package subunit is not qualified. And each control pin of the unit control chip in the second display packaging subunit is detected through the same LED wafer block, so that the detection efficiency is also improved.
In a second aspect, the present application provides an integrated circuit multi-chip combined test device for detecting the first display package subunit according to any one of the first aspects, the integrated circuit multi-chip combined test device including a first substrate and a piezoelectric ceramic layer soldered on the first substrate; the first substrate is a metal substrate, a first metal layer and a second metal layer are respectively arranged on the surfaces of two opposite sides of the piezoelectric ceramic layer, the first metal layer is welded to the first substrate, the section size of the piezoelectric ceramic layer is smaller than that of the first groove, and the height of the piezoelectric ceramic layer is smaller than or equal to the depth of the first groove.
In a third aspect, the present application provides another integrated circuit multi-chip combined test apparatus for detecting the second display package subunit according to any one of the first aspects, the integrated circuit multi-chip combined test apparatus including a second substrate and an LED wafer block soldered on the second substrate; the LED chip comprises a first substrate, a second substrate, a first metal layer, a second metal layer, a first electrode and a second electrode, wherein the first metal layer is arranged on the surface of the first substrate, the second metal layer is arranged on the surface of the second substrate, the second metal layer is matched with the boss, the first electrode and the second electrode are arranged on the surfaces of two opposite sides of the LED chip, the first electrode is welded on the third metal layer, and the sum of the thickness of the LED chip and the thickness of the boss is larger than or equal to the depth of the second groove.
Advantageous effects
The application provides an integrated circuit multi-chip joint test method, which divides a traditional display packaging unit into a first display packaging subunit containing an LED chip and a second display packaging subunit containing a unit control chip, and detects the first display packaging subunit and the second display packaging subunit respectively so as to reduce the replacement cost of dead pixels.
When the first display packaging subunit is detected, the first display packaging subunit is extruded towards the first testing device, so that the piezoelectric ceramic layer deforms to form charges on the surface, and the LED chip is lightened through a positive electrode contact disc connected with the positive electrode of the LED chip and each driving contact disc connected with the negative electrode of the LED chip. If the first display packaging subunit has an LED chip which is not lightened, the first display packaging subunit can be judged to be a dead pixel, and the first display packaging subunit is replaced. The piezoelectric effect through piezoceramics layer detects first demonstration encapsulation subunit, and whole testing process only need aim at press the back observe the LED chip whether light can, easy operation has improved detection efficiency greatly.
When the second display packaging subunit is detected, the power contact pad of the second display packaging subunit is contacted with the first electrode of the LED wafer block, and each control contact pad is contacted with the second electrode of the LED wafer block; and then, driving signals are input to the scanning line pins and the data line pins of the unit control chip through the probes, and each control pin is controlled to drive the LED wafer blocks to light in sequence. In this process, if the LED wafer block does not respond to the driving signal output by the probe and is not turned on, it may be determined that the second display package subunit is not qualified. And each control pin of the unit control chip in the second display packaging subunit is detected through the same LED wafer block, so that the detection efficiency is also improved.
In order to make the above objects, features and advantages of the present application more comprehensible, alternative embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered limiting the scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a display formed by an arrangement of display packaging units in the prior art;
FIG. 2 is a schematic diagram showing a structure of a package unit according to the prior art
FIG. 3 is a schematic structural view of a first display package subunit provided herein;
FIG. 4 is a schematic structural view of a second display package subunit provided herein;
FIG. 5 is a schematic diagram of a detection scenario of a first display package subunit;
FIG. 6 is a schematic diagram of a detection scenario of a second display package subunit;
fig. 7 and 8 are schematic mounting diagrams of qualified first and second display package subunits.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the preparation process of Micro-LED displays, red, green and blue LED chips are required to be transferred onto a display backboard one by one, which clearly requires a high-precision transfer technology and high time cost. In order to improve the production efficiency and the production yield of the Micro-LED display, a person skilled in the art thinks that the red, green and blue LED chips and the unit control chip are packaged in the same display packaging unit, and in the subsequent display production process, only the display packaging units are required to be arranged on corresponding circuit boards one by one.
As shown in fig. 1, the installation of each pixel unit can be completed only by transferring and arranging each display packaging unit 2 onto the display backboard 1, red, green and blue LED chips are not required to be transferred onto the display backboard 1 one by one, the precision requirement on the transfer technology is reduced, and the production efficiency and the production yield are improved. As shown in fig. 2, the driving chip 3 in the display packaging unit 2 receives a control signal of the control circuit 4 on the display back plate 1 through the scan line pins and the data line pins, and drives the red, green and blue LED chips in the display packaging unit 2 through the respective control pins according to the control signal.
Before the display packaging units are welded on the circuit board, the display packaging units need to be detected one by one, and as the display packaging units are integrated with more elements, whether the display packaging units are faulty or not can only be judged, and whether the fault causes come from the LED chips or the unit control chips is difficult to judge. When a defective pixel is found, the whole display packaging unit needs to be replaced, and the replacement cost for the defective pixel is high.
In order to solve the above-mentioned problems, the present application provides a method for testing multiple chips of an integrated circuit, which includes the following steps.
S1, providing a first display packaging subunit and a second display packaging subunit, wherein the first display packaging subunit comprises a first circuit board and at least one LED chip arranged on the first circuit board, and the second display packaging subunit comprises a second circuit board and a unit control chip arranged on the second circuit board.
The first display package subunit 10 shown in fig. 3 includes a first circuit board 11 and three LED chips 121, 122 and 123 disposed on the first circuit board 11, the LED chips being disposed on a front surface of the first circuit board 11, a back surface of the first circuit board 11 being provided with a first groove 13, driving contact pads 141, 142 and 143 connected to negative electrodes of the respective LED chips being disposed within the first groove 13, and non-first groove areas on the back surface of the first circuit board 11 being provided with positive electrode contact pads 151 and 152 connected to positive electrodes of the respective LED chips.
The second display package sub-unit 20 shown in fig. 4 includes a second circuit board 21 and a unit control chip 22 disposed on the second circuit board 21. In the figure, the unit control chip 22 includes 6 pins, which are sequentially from left to right: a power supply pin 221, a first control pin 222, a second control pin 223, a third control pin 224, a scan line pin 225, a data line pin 226, and a ground pin 227. A boss 23 matched with the first groove 13 is formed in the center of the front surface of the second circuit board 21, the unit control chip 22 is arranged on the back surface of the second circuit board, control contact pads 241, 242 and 243 corresponding to the driving contact pads are arranged on the boss 23, the control contact pads are respectively connected with the control pins of the unit control chip 22, the power contact pads 251 and 252 corresponding to the positive contact pads 151 and 152 are arranged in the non-boss area of the front surface of the second circuit board, and the power contact pad 251 is connected with the power pin 221 of the unit control chip 22; the second circuit board is also provided on the back surface thereof with a power electrode 261 connected with the power contact pad 251, a power electrode 262 connected with the power contact pad 252, a ground electrode 263 connected with the ground pin 227, a scan line electrode 264 connected with the scan line pin 225, and a signal line electrode 265 connected with the data line pin 226.
As shown in fig. 3 and 4, the inner side wall of the first groove 13 is provided with a first magnet 16, and the outer side wall of the boss 27 is provided with a second magnet 27 opposite to the first magnet 16 in magnetism. It will be appreciated that the provision of the first and second magnets is to facilitate the incorporation of the first and second display package subunits such that the first recess and boss can be more easily and effectively aligned.
S2, providing a first testing device, wherein the first testing device comprises a first substrate and a piezoelectric ceramic layer welded on the first substrate.
The first testing device 30 shown in fig. 5 includes a first substrate 31 and a piezoelectric ceramic layer 32 welded on the first substrate 31, wherein the first substrate 31 is a metal substrate, a first metal layer 321 and a second metal layer 322 are respectively disposed on two opposite side surfaces of the piezoelectric ceramic layer 32, the first metal layer 321 is welded on the first substrate 31, the cross-sectional dimension of the piezoelectric ceramic layer 32 is smaller than the first groove 13, and the height of the piezoelectric ceramic layer 32 is smaller than or equal to the depth of the first groove 13.
S3, contacting the first display packaging subunit with a first testing device, and extruding the first display packaging subunit towards the direction of the first testing device to detect whether the first display packaging subunit is qualified or not.
As shown in fig. 5, step S3 specifically includes:
s31, covering the corresponding piezoelectric ceramic layer with the first groove of the first display packaging subunit to be tested, so that the positive electrode contact plate is contacted with the first substrate while each driving contact plate is contacted with the second metal layer.
S32, extruding the first display packaging subunit towards the direction of the first testing device, so that the piezoelectric ceramic layer deforms to generate a piezoelectric effect.
S33, judging that the first display packaging subunit is qualified when all the LED chips in the first display packaging subunit are lighted, and judging that the first display packaging subunit is unqualified when all the LED chips in the first display packaging subunit are not lighted.
It can be understood that when the first display package subunit is detected, the first display package subunit is pressed toward the first testing device, so that the piezoelectric ceramic layer deforms to form charges on the surface, and the LED chip is lightened through the positive electrode contact pad connected with the positive electrode of the LED chip and the driving contact pads connected with the negative electrode of the LED chip respectively. If the first display packaging subunit has an LED chip which is not lightened, the first display packaging subunit can be judged to be a dead pixel, and the first display packaging subunit is replaced. The piezoelectric effect through piezoceramics layer detects first demonstration encapsulation subunit, and whole testing process only need aim at press the back observe the LED chip whether light can, easy operation has improved detection efficiency greatly.
S4, providing a second testing device, wherein the second testing device comprises a second substrate and an LED wafer block welded on the second substrate.
The second testing device 40 shown in fig. 6 includes a second substrate 41 and an LED wafer block 42 soldered on the second substrate 41. The second substrate 41 is provided with a second groove 43 matched with the boss 23, a third metal layer 44 is formed on the surface provided with the second groove 43, the surfaces of two opposite sides of the LED wafer block 42 are provided with a first electrode 421 and a second electrode 422, the first electrode 421 is welded on the third metal layer 44, and the sum of the thickness of the LED wafer block 42 and the thickness of the boss 23 is greater than or equal to the depth of the second groove 43.
S5, the second display packaging subunit is contacted with the second testing device, so that each control pin and each power pin of the unit control chip are respectively contacted with two poles of the LED wafer block, and driving signals are input to the scanning line pins and the data line pins of the unit control chip to detect whether the second display packaging subunit is qualified or not.
The step S5 specifically comprises the following steps:
s51, inserting the boss of the second display packaging subunit to be tested into the corresponding second groove, so that the power contact plate is contacted with the third metal layer while each control contact plate is contacted with the second electrode.
S52, driving signals are input to the scanning line pins and the data line pins of the unit control chip, and each control pin is controlled to drive the LED wafer blocks to light.
And S53, judging that the second display packaging subunit is qualified when the LED wafer block is lighted, and judging that the second display packaging subunit is unqualified when the LED wafer block is unlit.
When the second display packaging subunit is detected, the power contact pad of the second display packaging subunit is contacted with the first electrode of the LED wafer block, and each control contact pad is contacted with the second electrode of the LED wafer block; and then, driving signals are input to the scanning line pins and the data line pins of the unit control chip through the probes, and each control pin is controlled to drive the LED wafer blocks to light in sequence. In this process, if the LED wafer block does not respond to the driving signal output by the probe and is not turned on, it may be determined that the second display package subunit is not qualified. And each control pin of the unit control chip in the second display packaging subunit is detected through the same LED wafer block, so that the detection efficiency is also improved.
It can be appreciated that the application provides an integrated circuit multi-chip joint test method, in which a traditional display packaging unit is split into a first display packaging subunit containing an LED chip and a second display packaging subunit containing a unit control chip, and the detection is performed respectively to reduce the replacement cost of dead pixels. The piezoelectric effect through piezoceramics layer detects first demonstration encapsulation subunit, and whole testing process only need aim at press the back observe the LED chip whether light can, easy operation has improved detection efficiency greatly. And each control pin of the unit control chip in the second display packaging subunit is detected through the same LED wafer block, so that the detection efficiency is also improved.
In an alternative embodiment of the present application, the method further comprises:
s6, providing a display circuit board.
And S7, selecting a qualified second display packaging subunit, and welding a power electrode, a grounding electrode, a scanning line electrode and a signal line electrode of the second display packaging subunit on corresponding electrode pads on the display circuit board.
As shown in fig. 7, the power supply electrodes 261 and 262 of the acceptable second display package subunit 20 are soldered to the corresponding electrode pads 51 and 52 of the display circuit board 50; the ground electrode 263 is welded on the electrode pad 53 corresponding to the display circuit board 50; the scan line electrode 264 and the signal line electrode 265 are soldered to the corresponding electrode pads 54 and 55 of the display circuit board 50, respectively.
S8, selecting a qualified first display packaging subunit, and covering a boss of a corresponding second display packaging subunit by a first groove of the first display packaging subunit.
And S9, respectively welding each driving contact pad on a corresponding control contact pad, and welding the positive contact pad on a corresponding power contact pad.
As shown in fig. 8, each driving contact pad of the first display package subunit 10 is welded to a corresponding control contact pad of the second display package subunit 20, and the positive contact pad is welded to a corresponding power contact pad.
It can be understood that after the first display packaging subunit and the second display packaging subunit are correspondingly welded, the unit control chip can correspondingly control the lighting time and the brightness of each LED chip through each control pin, so that the first display packaging subunit and the second display packaging subunit are combined into a complete display packaging unit.
The terms "first," "second," "the first," or "the second," as used in various embodiments of the present disclosure, may modify various components without regard to order and/or importance, but these terms do not limit the corresponding components. The above description is only configured for the purpose of distinguishing an element from other elements. For example, the first user device and the second user device represent different user devices, although both are user devices. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.
When an element (e.g., a first element) is referred to as being "coupled" (operatively or communicatively) to "another element (e.g., a second element) or" connected "to another element (e.g., a second element), it is understood that the one element is directly connected to the other element or the one element is indirectly connected to the other element via yet another element (e.g., a third element). In contrast, it will be understood that when an element (e.g., a first element) is referred to as being "directly connected" or "directly coupled" to another element (a second element), then no element (e.g., a third element) is interposed therebetween.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the element defined by the phrase "comprising one … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element, and furthermore, elements having the same name in different embodiments of the present application may have the same meaning or may have different meanings, a particular meaning of which is to be determined by its interpretation in this particular embodiment or by further combining the context of this particular embodiment.
The above description is only illustrative of the principles of the technology being applied to alternative embodiments of the present application. It will be appreciated by persons skilled in the art that the scope of the invention referred to in this application is not limited to the specific combinations of features described above, but it is intended to cover other embodiments in which any combination of features described above or equivalents thereof is possible without departing from the spirit of the invention. Such as the above-described features and technical features having similar functions (but not limited to) disclosed in the present application are replaced with each other.
The words "if", as used herein, may be interpreted as "at … …" or "at … …" or "in response to a determination" or "in response to a detection", depending on the context. Similarly, the phrase "if determined" or "if detected (stated condition or event)" may be interpreted as "when determined" or "in response to determination" or "when detected (stated condition or event)" or "in response to detection (stated condition or event), depending on the context.
The above description is only illustrative of the principles of the technology being applied to alternative embodiments of the present application. It will be appreciated by persons skilled in the art that the scope of the invention referred to in this application is not limited to the specific combinations of features described above, but it is intended to cover other embodiments in which any combination of features described above or equivalents thereof is possible without departing from the spirit of the invention. Such as the above-described features and technical features having similar functions (but not limited to) disclosed in the present application are replaced with each other.
The foregoing is merely an alternative embodiment of the present application and is not intended to limit the present application, and various modifications and variations may be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
Claims (5)
1. A method for integrated circuit multi-chip joint testing, comprising:
s1, providing a first display packaging subunit and a second display packaging subunit, wherein the first display packaging subunit comprises a first circuit board and at least one LED chip arranged on the first circuit board, and the second display packaging subunit comprises a second circuit board and a unit control chip arranged on the second circuit board;
s2, providing a first testing device, wherein the first testing device comprises a first substrate and a piezoelectric ceramic layer welded on the first substrate;
s3, the first display packaging subunit is contacted with the first testing device, and the first display packaging subunit is extruded towards the first testing device to detect whether the first display packaging subunit is qualified or not;
s4, providing a second testing device, wherein the second testing device comprises a second substrate and an LED wafer block welded on the second substrate;
s5, enabling the second display packaging subunit to be in contact with the second testing device, enabling each control pin and each power pin of the unit control chip to be in contact with two poles of the LED wafer block respectively, and inputting driving signals to the scanning line pins and the data line pins of the unit control chip to detect whether the second display packaging subunit is qualified or not;
in the first display packaging subunit, the LED chips are disposed on the front surface of the first circuit board, a first groove is disposed on the back surface of the first circuit board, a driving contact pad connected with the negative electrode of each LED chip is disposed in the first groove, and a positive electrode contact pad connected with the positive electrode of each LED chip is disposed in a non-first groove area on the back surface of the first circuit board;
in the second display packaging subunit, a boss matched with the first groove is formed in the center of the front surface of the second circuit board, the unit control chip is arranged on the back surface of the second circuit board, control contact discs corresponding to the driving contact discs are arranged on the boss, the control contact discs are respectively connected with the control pins of the unit control chip, and a power contact disc corresponding to the positive electrode contact disc is arranged in a non-boss area of the front surface of the second circuit board, wherein at least one power contact disc is connected with the power pins of the unit control chip; the back surface of the second circuit board is also provided with a power electrode connected with each power contact pad, a grounding electrode connected with a grounding pin, a scanning line electrode connected with the scanning line pin and a signal line electrode connected with the data line pin;
in the first test device, the first substrate is a metal substrate, a first metal layer and a second metal layer are respectively arranged on the surfaces of two opposite sides of the piezoelectric ceramic layer, the first metal layer is welded on the first substrate, the section size of the piezoelectric ceramic layer is smaller than that of the first groove, and the height of the piezoelectric ceramic layer is smaller than or equal to the depth of the first groove;
in the second testing device, a second groove matched with the boss is formed in the second substrate, a third metal layer is formed on the surface provided with the second groove, a first electrode and a second electrode are arranged on the surfaces of two opposite sides of the LED wafer block, the first electrode is welded on the third metal layer, and the sum of the thickness of the LED wafer block and the thickness of the boss is greater than or equal to the depth of the second groove;
after the first display packaging subunit and the second display packaging subunit are correspondingly welded, the unit control chip can correspondingly control the lighting time and the brightness of each LED chip through each control pin, so that the first display packaging subunit and the second display packaging subunit are combined into a complete display packaging unit.
2. The integrated circuit multi-chip joint test method of claim 1, wherein,
further comprises:
s6, providing a display circuit board;
s7, selecting the qualified second display packaging subunit, and welding a power electrode, a ground electrode, a scanning line electrode and a signal line electrode of the second display packaging subunit on corresponding electrode pads on the display circuit board;
s8, selecting the qualified first display packaging subunit, and covering the first groove of the first display packaging subunit with the boss of the corresponding second display packaging subunit;
and S9, respectively welding each driving contact pad on the corresponding control contact pad, and welding the positive contact pad on the corresponding power contact pad.
3. The integrated circuit multi-chip joint test method of claim 2, wherein,
the inner side wall of the first groove is provided with a first magnet, and the outer side wall of the boss is provided with a second magnet with magnetism opposite to that of the first magnet.
4. The integrated circuit multi-chip joint test method of claim 1, wherein,
the step S3 comprises the following steps:
s31, covering the corresponding piezoelectric ceramic layer by the first groove of the first display packaging subunit to be tested, so that the positive electrode contact plate is contacted with the first substrate while the driving contact plates are contacted with the second metal layer;
s32, extruding the first display packaging subunit towards the first testing device to enable the piezoelectric ceramic layer to deform to generate a piezoelectric effect;
and S33, judging that the first display packaging subunit is qualified when all the LED chips in the first display packaging subunit are lighted, and judging that the first display packaging subunit is unqualified when all the LED chips in the first display packaging subunit are not lighted.
5. The integrated circuit multi-chip joint test method of claim 1, wherein,
the step S5 comprises the following steps:
inserting the boss of the second display packaging subunit to be tested into the corresponding second groove, so that the power contact pad is contacted with the third metal layer while each control contact pad is contacted with the second electrode;
driving signals are input to scanning line pins and data line pins of the unit control chip, and each control pin is sequentially controlled to drive the LED wafer blocks to light;
and judging that the second display packaging subunit is qualified under the condition that the LED wafer block is lightened, and judging that the second display packaging subunit is unqualified under the condition that the LED wafer block is not lightened.
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