CN116155389A - Optical module debugging system and method - Google Patents
Optical module debugging system and method Download PDFInfo
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- CN116155389A CN116155389A CN202310175580.7A CN202310175580A CN116155389A CN 116155389 A CN116155389 A CN 116155389A CN 202310175580 A CN202310175580 A CN 202310175580A CN 116155389 A CN116155389 A CN 116155389A
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- H—ELECTRICITY
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
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Abstract
The invention discloses an optical module debugging system and method, wherein the system comprises: the system comprises an upper computer, a switching module and an optical module, wherein the optical module comprises an MCU unit and at least one slave chip; the upper computer is used for outputting an upper computer instruction, the upper computer instruction is transmitted to the MCU unit through the switching module, the MCU unit is used for copying the upper computer instruction in real time and outputting a follow-up upper computer instruction to any slave chip at the same time, and the follow-up upper computer instruction is executed by any slave chip; any slave chip is also used for outputting a chip feedback instruction, the chip feedback instruction is transmitted to the MCU unit, the MCU unit is also used for copying the chip feedback instruction in real time, and simultaneously outputting a following feedback instruction to the switching module, and the switching module transmits the following feedback instruction to the upper computer. The system and the method for debugging have universality and low cost, and the flying lead is not required to be used, so that the damage to the optical module is avoided.
Description
Technical Field
The invention relates to the technical field of optical module debugging, in particular to an optical module debugging system and method.
Background
In the application of emerging internet technologies such as big data, cloud computing, artificial intelligence and the like, in order to meet the requirement of high-speed transmission of huge amounts of data, an optical communication technology is generally used, and an optical module realizes a data receiving and transmitting function in a photoelectric conversion mode and is one of key devices in the optical communication field.
In order to realize the photoelectric conversion function, a plurality of chips such as an MCU (micro control Unit), a laser driver, a photoelectric detector, a limiting amplifier, a digital signal processor and the like are arranged in the optical module, when the optical module is normally used, the MCU controls other chips mainly through I2C (Inter-Integrated circuit) communication, namely, an I2C pin of the MCU is connected to an I2C pin of other chips through a circuit, at the moment, the MCU is used as a host computer, the other chips are used as a slave computer, and the MCU reads and writes data of the other chips through an I2C communication protocol. In the optical module production process, after the module assembly is completed, since the electrical parameters of each chip are not optimal application values, each chip needs to be debugged to determine the optimal application values of each electrical parameter. Usually, each manufacturer of the chip provides its own host software and a transfer module for the user to directly and continuously measure the chip parameters. However, since each chip is already packaged on the circuit board of the optical module, the current debugging mainly adopts a flying lead mode, specifically, one ends of two wires are respectively welded on the I2C pins of the chip, the other ends of the two wires are respectively correspondingly spliced on the switching module, and the switching module is connected to a computer provided with upper computer software, so that relevant electric parameters of each chip can be debugged in real time when the optical module performs simulation work. However, due to the repeatability of debugging, the chip I2C pins are required to be welded and the flying leads are required to be removed for a plurality of times, the method is time-consuming and labor-consuming, the high-frequency performance of the optical module circuit board is easy to be reduced, and the circuit board is scrapped when serious.
On the one hand, the MCU can not directly receive the modulation parameters from the switching module so as to modify the electrical parameters of each chip, and only fly line debugging can be adopted, but the fly line debugging mode is low in efficiency, the performance of the circuit board is affected, and a large amount of waste and high cost are caused. On the other hand, if the MCU is to receive parameters from the transfer module, the transfer module of each manufacturer needs to be processed separately to receive, process (package) and send different types of data to the chip, so that the decoding and programming workload is large, and the labor and time cost are high.
Disclosure of Invention
The invention provides an optical module debugging system and method, which are used for solving the problems that the optical module is frequently debugged by using a flying wire in the related technology, the damage is caused to the optical module, and the decoding programming workload is large because an MCU and a switching module cannot be directly matched for application.
In order to solve the above problems, an embodiment of an aspect of the present invention provides an optical module debugging system, including:
the system comprises an upper computer, a switching module and an optical module, wherein the optical module comprises an MCU unit and at least one slave chip;
the MCU unit is electrically connected with the switching module and any slave chip and is communicated with the switching module through an I2C protocol; the upper computer is connected with the switching module through a serial bus to carry out serial port communication;
The upper computer is used for outputting an upper computer instruction, the upper computer instruction is transmitted to the MCU unit through the switching module, the MCU unit is used for copying the upper computer instruction in real time and outputting a following upper computer instruction to any slave chip at the same time, and any slave chip executes the following upper computer instruction;
any slave chip is further used for outputting a chip feedback instruction, the chip feedback instruction is transmitted to the MCU unit, the MCU unit is further used for copying the chip feedback instruction in real time, and simultaneously outputting a following feedback instruction to the switching module, and the switching module transmits the following feedback instruction to the upper computer.
Optionally, the upper computer instruction and the chip feedback instruction each include periodic and/or aperiodic level signals, and the level signals include high level signals and/or low level signals.
Optionally, the MCU unit includes a first data pin, a first clock pin, a second data pin, a second clock pin; any slave chip comprises a third data pin and a third clock pin; the switching module comprises a fourth data pin and a fourth clock pin;
The first data pin is electrically connected with the fourth data pin, the first clock pin is electrically connected with the fourth clock pin, the second data pin is electrically connected with the third data pin, and the second clock pin is electrically connected with the third clock pin.
Optionally, when the upper computer outputs a control instruction, the level signal of the second data pin replicates the level signal of the first data pin;
and when the upper computer receives the following feedback instruction, the level signal of the first data pin replicates the level signal of the second data pin.
In order to solve the above problems, an embodiment of the present invention provides an optical module debugging method, which is implemented based on the optical module debugging system according to any embodiment of the present invention, and the optical module debugging method includes the following steps:
detecting a level signal of a first clock pin of the MCU unit;
when the level signal of the first clock pin is at a low level, judging whether the MCU unit and the slave chip are in a release state, if not, the MCU unit copies the chip feedback instruction in real time and simultaneously outputs a following feedback instruction to the switching module; returning to the step of detecting the level signal of the first clock pin of the MCU unit;
If yes, judging whether the MCU unit and the upper computer are in a release state, if not, the MCU unit replicates the upper computer instruction in real time, simultaneously outputs the upper computer instruction to any slave chip, returns to the step of detecting the level signal of the first clock pin of the MCU unit, and if yes, maintains the release state between the MCU unit and the upper computer, between the MCU unit and the slave chip, returns to the step of detecting the level signal of the first clock pin of the MCU unit.
Optionally, when the level signal of the first clock pin is at a high level, judging whether the MCU unit and the slave chip are in a release state, if so, setting the MCU unit and the upper computer to be in a release state;
if not, the MCU unit copies the upper computer instruction in real time, and outputs the upper computer instruction to any slave chip at the same time, and returns to the step of detecting the level signal of the first clock pin of the MCU unit.
Optionally, when the level signal of the first clock pin is at a low level, determining whether the MCU unit and the slave chip are in a released state includes:
Detecting a level signal of a second data pin of the MCU unit;
when the level signal of the second data pin is at a high level, the MCU unit and the slave chip are in a release state;
when the level signal of the second data pin is at a low level, the MCU unit and the slave chip are in an unreleased state.
Optionally, when the MCU unit and the slave chip are in a release state, determining whether the MCU unit and the upper computer are in a release state includes:
detecting a level signal of a first data pin of the MCU unit;
when the level signal of the first data pin is at a high level, the MCU unit and the slave chip are in a release state;
when the level signal of the first data pin is at a low level, the MCU unit and the slave chip are in an unreleased state.
Optionally, when the level signal of the first clock pin is at a high level, determining whether the MCU unit and the slave chip are in a released state includes:
detecting a level signal of a second data pin of the MCU unit;
when the level signal of the second data pin is at a high level, the MCU unit and the slave chip are in a release state;
When the level signal of the second data pin is at a low level, the MCU unit and the slave chip are in an unreleased state.
Optionally, when the level signal of the second data pin is at a high level, the level signal of the first data pin is set at a high level.
The embodiment of the invention also provides an optical module debugging method which is realized based on the optical module debugging system and comprises the following steps:
initially detecting a level signal of a first clock pin of the MCU unit;
if the first detected level signal of the first clock pin is low level, setting the level signal of the second clock pin to be low level, the level signal of the first data pin to be high level and the level signal of the second data pin to be high level at the same time;
detecting the level signal of the first clock pin again;
if the level signal of the first clock pin detected again is low level, further detecting the level signal of the second data pin;
if the level signal of the second data pin is low level, setting the level signal of the first data pin to be low level, and returning to the step of detecting the level signal of the first clock pin again;
If the level signal of the second data pin is high level, further detecting the level signal of the first data pin;
if the level signal of the first data pin is low level, setting the level signal of the second data pin to be low level, and returning to the step of detecting the level signal of the first clock pin again;
if the level signal of the first data pin is high level, setting the level signal of the second data pin to be high level and the first data pin to be high level at the same time, and returning to the step of detecting the level signal of the first clock pin again;
and if the level signal of the first clock pin detected again is at a high level, ending.
Optionally, the method further comprises:
if the level signal of the first clock pin detected for the first time is high level, setting the level signal of the second clock pin of the MCU unit to be high level;
then detecting a level signal of a second data pin of the MCU unit;
if the level signal of the second data pin is high level, setting the level signal of the first data pin of the MCU unit to be high level, and detecting the level signals of the first clock pin and the first data pin again;
If the level signal of the second data pin is low level, detecting the level signals of the first clock pin and the first data pin again;
if the detected level signal of the first clock pin is high level again, the detected level signal of the first data pin is duplicated by the level signal of the second data pin;
and if the level signal of the first clock pin detected again is at a low level, ending.
According to the optical module debugging system and method provided by the embodiment of the invention, the system comprises: the system comprises an upper computer, a switching module and an optical module, wherein the optical module comprises an MCU unit and at least one slave chip; the MCU unit is electrically connected with the switching module and any slave chip and is communicated with the switching module through an I2C protocol; the upper computer is connected with the switching module through a serial bus to carry out serial port communication; the upper computer is used for outputting an upper computer instruction, the upper computer instruction is transmitted to the MCU unit through the switching module, the MCU unit is used for copying the upper computer instruction in real time and outputting a follow-up upper computer instruction to any slave chip at the same time, and the follow-up upper computer instruction is executed by any slave chip; any slave chip is also used for outputting a chip feedback instruction, the chip feedback instruction is transmitted to the MCU unit, the MCU unit is also used for copying the chip feedback instruction in real time, and simultaneously outputting a following feedback instruction to the switching module, and the switching module transmits the following feedback instruction to the upper computer. Therefore, the MCU unit directly copies the instruction, signals output by the upper computer can be efficiently and stably transmitted to the slave chip, and signals output by the slave chip can be transmitted to the upper computer, so that a flying wire is not required, the damage to an optical module is avoided, and the debugging system and method have universality and low cost.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of an optical module debugging system according to an embodiment of the present invention;
fig. 2 is a flowchart of an optical module debugging method according to an embodiment of the present invention;
FIG. 3 is a flow chart of an optical module debugging method according to an embodiment of the present invention;
fig. 4 is a flowchart of an optical module debugging method according to another embodiment of the present invention;
fig. 5 is a flowchart of an optical module debugging method according to another embodiment of the present invention;
fig. 6 is a flowchart of an optical module debugging method according to still another embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Fig. 1 is a schematic structural diagram of an optical module debugging system according to an embodiment of the present invention. As shown in fig. 1, the optical module debugging system includes:
the system comprises an upper computer 5, a switching module 4 and an optical module, wherein the optical module comprises an MCU unit 1 and at least one slave chip (2, 3);
the MCU unit 1 is electrically connected with the switching module 4 and the MCU unit 1 is electrically connected with any slave chip (2, 3) and is communicated with the slave chip through an I2C protocol; the upper computer 5 is connected with the switching module 1 through a serial bus to carry out serial port communication;
the upper computer 5 is used for outputting an upper computer instruction, the upper computer instruction is transmitted to the MCU unit 1 through the switching module 4, the MCU unit 1 is used for copying the upper computer instruction in real time, and simultaneously outputting a follow-up upper computer instruction to any slave chip (2, 3), and any slave chip (2, 3) executes the follow-up upper computer instruction;
any slave chip (2, 3) is also used for outputting a chip feedback instruction, the chip feedback instruction is transmitted to the MCU unit 1, the MCU unit 1 is also used for copying the chip feedback instruction in real time, and simultaneously outputting a following feedback instruction to the switching module 4, and the switching module 4 transmits the following feedback instruction to the upper computer 5.
It should be noted that only two slave chips (2, 3) are shown in fig. 1, and in some examples, the slave chips (2, 3) may be plural, and the kind and number are not particularly limited.
The principle of the debugging system is as follows: the upper computer 5 is provided with a computer control interface which can be operated by a user, the user can operate the upper computer 5 to send a control instruction to acquire or modify the internal data of the slave chips (2, 3), the switching module 4 is connected with the upper computer 5 through a serial bus (USB), the switching module 4 is in communication transmission with the upper computer 5 through the serial bus, and the switching module 4 is electrically connected with a communication pin of the optical module so as to realize communication between the switching module 4 and the optical module. In the debugging process, the upper computer 5 outputs an upper computer instruction, the upper computer instruction is transmitted to the switching module 4 through a serial bus, the switching module 4 communicates with the MCU unit 1, the upper computer instruction is transmitted to the MCU unit 1, the MCU unit 1 duplicates the upper computer instruction and outputs a follow-up upper computer instruction, the communication is transmitted to each slave chip (2, 3), and the slave chips (2, 3) determine the type of the upper computer instruction based on the follow-up upper computer instruction and execute the follow-up upper computer instruction. After the slave chips (2, 3) execute the following upper computer instruction, a chip feedback instruction is also output, and similarly, the slave chips (2, 3) communicate with the MCU unit 1, the MCU unit 1 copies the chip feedback instruction, outputs the following feedback instruction to the switching module 4, the switching module 4 carries out serial communication with the upper computer 1, and finally the upper computer 1 reads the following feedback instruction.
Therefore, the MCU unit directly copies the instruction, signals output by the upper computer can be efficiently and stably transmitted to the slave chips (2 and 3), and signals output by the slave chips (2 and 3) can be transmitted to the upper computer without using flying wires, so that the damage to an optical module is avoided, and the debugging system and method have universality and low cost.
Optionally, as shown in fig. 1, the MCU unit 1 includes a first data pin 121, a first clock pin 122, a second data pin 111, and a second clock pin 112; any slave chip (2, 3) comprises a third data pin (211, 311), a third clock pin (212, 312); the switching module 4 comprises a fourth data pin 411 and a fourth clock pin 412; the first data pin 121 is electrically connected to the fourth data pin 411, the first clock pin 122 is electrically connected to the fourth clock pin 412, the second data pin 111 is electrically connected to the third data pin (211, 311), and the second clock pin 112 is electrically connected to the third clock pin (212, 312). Specifically, the optical module further comprises a circuit board, the MCU unit 1 and the slave chips (2, 3) are welded to the circuit board, circuit wires and golden fingers are arranged on the circuit board, the second data pins are electrically connected with the third data pins through the circuit wires, and the second clock pins are electrically connected with the third clock pins through the circuit wires; the first data pin and the first clock pin are electrically connected with the golden finger through circuit wires, and during debugging, the fourth data pin and the fourth clock pin are electrically connected with the golden finger, namely, the first data pin 121 and the fourth data pin 411 are electrically connected, and the first clock pin 122 and the fourth clock pin 412 are electrically connected. The upper computer instruction and the chip feedback instruction both comprise periodic and/or aperiodic level signals, and the level signals comprise high level signals and/or low level signals. When the upper computer 5 outputs a control instruction, the level signal of the second data pin 111 replicates the level signal of the first data pin 121; when the upper computer 5 receives the following feedback instruction, the level signal of the first data pin 121 replicates the level signal of the second data pin 111.
For example, with continued reference to fig. 1, taking the slave chip as two examples, the optical module at least includes an MCU unit 1, a first chip 2 and a second chip 3, where the MCU unit 1 communicates with the first chip 2 and the second chip 3 through I2C, specifically, the MCU unit 1 includes at least an internal communication pin 11, the first chip 2 is provided with a first communication pin 21, the second chip 3 is provided with a second communication pin 31, the first communication pin 21 and the second communication pin 31 are correspondingly connected to the internal communication pin 11 through circuit traces respectively, specifically, the internal communication pin 11 includes a second data pin 111 and a second clock pin 112, the first communication pin 21 includes a first third data pin 211 and a first third clock pin 212, the second communication pin 31 includes a second third data pin 311 and a second third clock pin 312, the first third data pin 211 is connected to the second data pin 111 through circuit traces, the second third data pin 311 is connected to the second data pin 111 through circuit traces, and the first third clock pin 212 is connected to the second clock pin 112 through circuit traces, and the first communication pin 31 is connected to the second chip 1 and the second clock pin 112 through the second clock pin 3. The MCU unit 1 further comprises an external communication pin 12, the external communication pin 12 being in particular a first data pin 121 and a first clock pin 122. The switching module 4 includes a fourth communication pin 41, the fourth communication pin 41 includes a fourth data pin 411 and a fourth clock pin 412, the first data pin 121 is connected to the fourth data pin 411 through a golden finger, and the first clock pin 122 is connected to the fourth clock pin 412 through a golden finger. Wherein, establish the electric connection between each communication pin to realize the communication between switching module 4 and MCU unit 1.
It is understood that the upper computer instruction output by the upper computer 5 may be a control instruction. The control command of the upper computer 5 is transmitted to the external communication pin 12 of the MCU unit 1 through the switching module 4, and the control command consists of periodic and/or aperiodic high-level signals and/or low-level signals. The MCU unit 1 detects the level signal state of the control command through the external communication pin 12, and controls the internal communication pin 11 to generate a following control command according to the following logic, and the following control command is transmitted to the chip through the internal communication pin 11. The level signal state of the following control instruction completely replicates the level signal state of the control instruction, that is, the high level signal of the control instruction is confirmed by the MCU unit 1 through the external communication pin 12, the MCU unit 1 controls the internal communication pin 11 to generate the following high level signal, the low level signal of the control instruction is confirmed by the MCU unit 1 through the external communication pin 12, and the MCU unit 1 controls the internal communication pin 11 to generate the following low level signal.
In some embodiments, the control instruction output by the upper computer 5 includes an address instruction, and the address instruction includes a debug chip address. The first chip 2 and the second chip 3 can determine the instruction type according to the level signal combination form of the following control instruction, if the first chip 2 and the second chip 3 are identified as the address instruction, the debug chip address is matched with the self address, and if the debug chip address is matched with the self address, the slave chip enters a debug state and can continuously receive the following control instruction and execute the following control instruction. The slave chip executing the following control instruction comprises issuing a feedback instruction to the MCU unit 1 and/or modifying the slave chip data. The feedback instruction is composed of a periodic and/or aperiodic high-level signal and/or a low-level signal. Likewise, the MCU unit 1 detects the level signal state of the feedback command through the internal communication pin 11, thereby controlling the external communication pin 12 to generate the following feedback command. The level signal state following the feedback command completely replicates the level signal state of the feedback command. The host computer 5 receives the following feedback instruction through the switching module 4 to acquire the state information of the slave chip.
The control command, the following control command, the feedback command and the following feedback command are all composed of a data command and a clock command at the same time, the data command is transmitted between data pins, namely an SDA line in FIG. 1, and the clock command is transmitted between clock pins, namely an SCL line in FIG. 1.
In some embodiments, the control instructions further include write instructions and read instructions, wherein the write instructions include write data instructions transferred from the first data pin 121 to the second data pin 111 and write-in Zhong Zhiling transferred from the first clock pin 122 to the second clock pin 112, and the read instructions include data read instructions transferred from the first data pin 121 to the second data pin 111 and read clock instructions transferred from the first clock pin 122 to the second clock pin 112. The write command and the read command consist of periodic and/or aperiodic high-level signals and/or low-level signals. Correspondingly, the following control instruction correspondingly comprises a following writing instruction and a following reading instruction, and the following writing instruction and the following reading instruction are transmitted to the communication pins of the slave chips (2 and 3) through the internal communication pin 11 of the MCU unit 1. The following write command and the following read command are composed of periodic and/or aperiodic high-level signals and/or low-level signals, the level signal state of the following write command completely replicates the level signal state of the write command, and the level signal state of the following read command completely replicates the level signal state of the read command.
In some embodiments, the feedback instruction includes a chip confirm instruction and an information instruction, the slave chip (2, 3) in the debug state determines the instruction type according to the level signal combination form of the following control instruction, if the read-in instruction is identified, the data of the slave chip (2, 3) is modified, and the chip confirm instruction is immediately sent to the MCU unit 1; if the read command is identified, the slave chip (2, 3) transmits a chip confirmation command and an information command to the MCU unit 1. Accordingly, the follow feedback instruction includes a follow confirm instruction and a follow information instruction. The following confirmation instruction and the following information instruction are transmitted to the upper computer 5 through the switching module 4, and the upper computer 5 can acquire the state information of the slave chips (2 and 3). Further, the control instruction further includes an upper computer confirmation instruction, and the upper computer 5 sends the upper computer confirmation instruction after receiving the information instruction.
It should be noted that, in the above process, the MCU unit 1 does not perform processing such as integrating and analyzing the control command, only separately confirms each level signal and copies the output level signal, which is equivalent to establishing a "direct" connection between the external communication pin 12 and the internal communication pin 11 to directly transfer the level signal, i.e. the MCU unit 1 is used as a "virtual flying wire", so as to realize direct debugging of the chip, and compared with the process of processing the control command, the efficiency of sending the control command to the chip is significantly improved. After the upper computer 5 sends the control command, the MCU unit 1 only detects the level to generate the following control command, i.e. copy the level from outside to inside, and the slave chips (2, 3) can confirm the command type from the combined form of the level signals after receiving the following control command (i.e. the slave chips (2, 3) themselves are the type of the command after integrating, analyzing and other processes on the control command), so as to generate the feedback command, and at this time, the MCU unit 1 needs to copy the level from inside to outside.
According to the I2C communication protocol, the upper computer 5 serves as a host, the chips (2, 3) serve as slaves, and after the host sends a control command, the slaves generate a feedback command each time they receive the control command of the host, so that the MCU unit 1 serves as an intermediate transmission medium, and needs to detect the level states of the internal communication pins and the external communication pins in real time, and determine the following (copying) direction of the command, so as to meet the standard timing requirement of the I2C communication protocol. Specifically, as shown in fig. 2 to 6, the logic of the replica level in the MCU unit 1 is as follows:
first detecting a level signal of a first clock pin 122 of the MCU unit 1; if the first clock pin 122 level signal detected for the first time is high, then high level following logic is entered. Under the high level following logic, firstly determining whether a release state is between the MCU unit 1 and the slave chips (2, 3) (according to an I2C protocol, the release state refers to that a clock line and a data line are both in a high level state, namely the data line is in an idle state and no signal transmission exists), if so, enabling a level signal of a first data pin to copy a level signal of a second data pin, namely the MCU unit 1 sets the first data pin to be in a high level, and further keeping a release state between an upper computer 5 and the MCU unit 1; if not in the released state, the level signal of the second data pin 111 replicates the level signal of the first data pin 121, i.e. the MCU unit 1 replicates the upper computer instruction and generates the following upper computer instruction, mainly for write operations.
Specifically, as shown in fig. 5, if the level signal of the first clock pin 122 detected for the first time is at a high level, the level signal of the second clock pin 112 of the MCU unit 1 is set at a high level; detecting a level signal of the second data pin 111 of the MCU unit 1; if the level signal of the second data pin 111 is high, the level signal of the first data pin 121 of the MCU unit 1 is set to high, and then the level signals of the first data pin 121 and the first clock pin 122 are detected again; if the level signal of the second data pin 111 is low, the level signals of the first data pin 121 and the first clock pin 122 are directly detected again; if the level signal of the first clock pin 122 detected again is at the high level, the level signal of the second data pin 111 replicates the detected level signal of the first data pin 121; if the level signal of the first clock pin 122 detected again is low, it ends.
If the first clock pin 122 level signal detected for the first time is low, then a low level follower logic is entered. In the low level following logic, the release states between the upper computer 5 and the MCU unit 1 and between the MCU unit 1 and the slave chips (2 and 3) are set firstly, and then whether the release state is set successfully or not is judged by respectively detecting the level states of the second data pin and the first data pin of the MCU unit, so that the following direction of the instruction is judged.
Specifically, as shown in fig. 6, if the first clock pin 122 level signal detected for the first time is at a low level, the second clock pin 112 level signal is at a low level, the first data pin 121 level signal is at a high level, and the second data pin 111 level signal is at a high level; again detecting the level signal of the first clock pin 122; if the level signal of the first clock pin 122 detected again is low level, the level signal of the second data pin 111 is further detected; if the level signal of the second data pin 111 is low, the level signal of the first data pin 121 is set to low, and the step of detecting the level signal of the first clock pin 122 again is returned; if the level signal of the second data pin 111 is at a high level, the level signal of the first data pin 121 is further detected; if the level signal of the first data pin 121 is low, the level signal of the second data pin 111 is set to low, and the step of detecting the level signal of the first clock pin 122 again is returned; if the level signal of the first data pin 121 is at the high level, the level signal of the second data pin 111 is set at the high level and the first data pin is at the high level at the same time, and then the step of detecting the level signal of the first clock pin 122 again is returned; if the level signal of the first clock pin 122 detected again is high, it ends.
In addition, the optical module debugging system further comprises a test board and an oscilloscope, wherein the communication terminal of the optical module is electrically connected to the test board, the test board is usually provided with a connector, the communication terminal of the optical module is inserted into the connector, the test board is electrically connected with the oscilloscope, after the debugging is started, data transmission is started between the optical module and the test board, the quality of an eye pattern on the oscilloscope is observed, and the electric parameters of each slave chip and the optical parameters including equalization parameters, pre-emphasis parameters, de-emphasis parameters, reverse bias voltage, signal gain and the like are gradually adjusted.
Therefore, the debugging system only needs to match the upper computer 5 and the switching module 4 with the optical module, and the flying lead test is not needed to be connected again, so that the damage to the optical module is avoided.
The embodiment of the invention provides an optical module debugging method, which is realized based on the optical module debugging system of any embodiment of the invention, and comprises the following steps:
as shown in fig. 2, detecting a level signal of a first clock pin of the MCU unit;
when the level signal of the first clock pin is low level, judging whether the MCU unit and the slave chip are in a release state;
if not, the MCU replicates the chip feedback instruction in real time and outputs the following feedback instruction to the switching module at the same time; returning to the step of detecting the level signal of the first clock pin of the MCU unit;
If yes, judging whether the MCU unit and the upper computer are in a release state or not; if not, the MCU unit replicates the upper computer instruction in real time and simultaneously outputs the upper computer instruction to any slave chip; and returning to the step of detecting the level signal of the first clock pin of the MCU unit, if so, maintaining the release state between the MCU unit and the upper computer and between the MCU unit and the slave chip, and returning to the step of detecting the level signal of the first clock pin of the MCU unit.
When the level signal of the first clock pin is at a low level, determining whether the MCU unit and the slave chip are in a released state includes: detecting a level signal of a second data pin of the MCU unit; when the level signal of the second data pin is at a high level, the MCU unit and the slave chip are in a release state; when the level signal of the second data pin is at a low level, the MCU unit and the slave chip are in an unreleased state.
When the MCU unit and the slave chip are in a release state, judging whether the MCU unit and the upper computer are in the release state comprises the following steps: detecting a level signal of a first data pin of the MCU unit; when the level signal of the first data pin is high level, the MCU unit and the slave chip are in a release state; when the level signal of the first data pin is at a low level, the MCU unit and the slave chip are in an unreleased state.
That is, when the level signal of the first clock pin is low, and when the level signal of the second data pin is low, the MCU unit copies the feedback chip instruction of the slave chip for the read operation; when the level signal of the first clock pin is at a low level, the MCU unit duplicates the upper computer instruction for the write operation when the level signal of the first data pin is at a low level.
As shown in fig. 3, when the level signal of the first clock pin is at a high level, determining whether the MCU unit and the slave chip are in a released state;
if yes, setting the MCU unit and the upper computer to be in a release state;
if not, the MCU unit replicates the upper computer instruction in real time, and outputs the upper computer instruction to any slave chip at the same time, and returns to the step of detecting the level signal of the first clock pin of the MCU unit.
That is, when the level signal of the first clock pin is high, the write operation is generally directed.
More specifically, when the level signal of the first clock pin is at a high level, determining whether the MCU unit and the slave chip are in a released state includes: detecting a level signal of a second data pin of the MCU unit; when the level signal of the second data pin is at a high level, the MCU unit and the slave chip are in a release state; when the level signal of the second data pin is at a low level, the MCU unit and the slave chip are in an unreleased state. And when the level signal of the second data pin is high, setting the level signal of the first data pin to be high.
That is, when the level signal of the first clock pin is high and the level signal of the second data pin is low, the MCU unit copies the upper computer instruction for the write operation.
More specifically, the optical module debugging method includes:
the method comprises the steps of firstly detecting a level signal of a first clock pin of an MCU unit;
if the level signal of the first clock pin detected for the first time is high level, setting the level signal of the second clock pin of the MCU unit to be high level;
detecting a level signal of a second data pin of the MCU unit;
if the level signal of the second data pin is high level, setting the level signal of the first data pin of the MCU unit to be high level, and detecting the level signal of the first clock pin again;
if the level signal of the second data pin is low level, directly detecting the level signals of the first data pin and the first clock pin again;
if the detected level signal of the first clock pin is high level, the level signal of the second data pin replicates the detected level signal of the first data pin;
if the level signal of the first clock pin detected again is low level, ending.
Optionally, if the level signal of the first clock pin detected for the first time is low level, the level signal of the second clock pin is set to be low level, the level signal of the first data pin is set to be high level, and the level signal of the second data pin is set to be high level;
Detecting the level signal of the first clock pin again;
if the level signal of the first clock pin detected again is low level, detecting the level signal of the second data pin;
if the level signal of the second data pin is low level, setting the level signal of the first data pin to be low level, and returning to detect the level signal of the first clock pin again;
if the level signal of the second data pin is high level, further detecting the level signal of the first data pin;
if the level signal of the first data pin is low level, setting the level signal of the second data pin to be low level, and returning to detect the level signal of the first clock pin again;
if the level signal of the first data pin is high level, setting the level signal of the second data pin to be high level and the level signal of the first data pin to be high level at the same time, and returning to the step of detecting the level signal of the first clock pin again;
if the level signal of the first clock pin detected again is high level, ending.
Specifically, as shown in fig. 4 to 6, the optical module debugging method includes:
s101, primarily detecting a level signal of a first clock pin of the MCU unit;
S102, judging whether a level signal of a first clock pin is at a high level, if so, executing S103, and if not, executing S104;
s103, entering a high level cycle, and returning to S101 after the high level cycle is finished.
S104, entering a low level cycle, and returning to S101 after the low level cycle is finished.
Wherein, as shown in fig. 5, the high level cycle includes:
s201, if the level signal of the first clock pin detected for the first time is high level, setting the level signal of the second clock pin of the MCU unit to be high level;
s202, detecting a level signal of a second data pin of the MCU unit;
s203, judging whether the level signal of the second data pin is at a high level, if so, executing S204, and if not, executing S205;
s204, setting a level signal of a first data pin of the MCU unit to be a high level;
s205, detecting the level signal of the first clock pin again, and detecting the level signal of the first data pin at the same time;
s206, judging whether the level signal of the first clock pin detected again is at a high level, if so, executing S207, and if not, ending;
s207, the level signal of the second data pin replicates the level signal of the first data pin just detected, and the process returns to S202.
That is, during the period in which the first clock pin is at the high level, the second clock pin is set at the high level, and the second clock pin can be maintained at the high level; at this time, if the second data pin is at a high level, the first data pin is set at a high level, that is, the first data pin level follows the second data pin and then is at a high level, so as to maintain a release state between the upper computer and the MCU unit. If the second data pin is at low level and the first clock pin is still at high level, then the MCU unit and the slave chip are not in a release state, and the second data pin level follows the first data pin level, namely, the write operation is performed.
Wherein, as shown in fig. 6, the low level cycle includes:
s301, if the level signal of the first clock pin detected for the first time is low level, setting the level signal of the second clock pin to be low level, the level signal of the first data pin to be high level, and the level signal of the second data pin to be high level at the same time;
s302, detecting the level signal of the first clock pin again; judging whether the level signal of the first clock pin detected again is at a low level, if so, executing S303, and if not, ending;
S303, detecting a level signal of the second data pin, judging whether the level signal of the second data pin is at a low level, if so, executing S304, and if not, executing S305;
s304, setting the level signal of the first data pin to be low level, and returning to S302;
s305, further detecting the level signal of the first data pin, judging whether the level signal of the first data pin is at a low level, if so, executing S306, and if not, executing S307;
s306, setting the level signal of the second data pin to be low level, and returning to S302;
s307, the level signal of the second data pin is set to high level, and the level signal of the first data pin is set to high level, and then S302 is returned.
That is, when the first clock pin is at a low level, the second clock pin follows the first clock pin and sets the second data pin to a high level (i.e. the first data pin is set between the upper computer and the MCU unit and between the MCU unit and the slave chip is in a release state), if the second data pin becomes at a low level, it means that the release state between the MCU unit and the slave chip is not successfully set, meaning that the chip is transmitting data to the upper computer, the first data pin needs to follow the second data pin to be at a low level, and the read operation can be performed. If the first data pin becomes low level, it indicates that the release state between the MCU unit and the upper computer is unsuccessful, meaning that the upper computer is transmitting data to the chip, and the second data pin becomes low level following the first data pin level, which can be aimed at the write operation.
In summary, according to the system and method for debugging an optical module provided by the embodiment of the present invention, the system includes: the system comprises an upper computer, a switching module and an optical module, wherein the optical module comprises an MCU unit and at least one slave chip; the MCU unit is electrically connected with the switching module and any slave chip and is communicated with the switching module through an I2C protocol; the upper computer is connected with the switching module through a serial bus to carry out serial port communication; the upper computer is used for outputting an upper computer instruction, the upper computer instruction is transmitted to the MCU unit through the switching module, the MCU unit is used for copying the upper computer instruction in real time and outputting a follow-up upper computer instruction to any slave chip at the same time, and the follow-up upper computer instruction is executed by any slave chip; any slave chip is also used for outputting a chip feedback instruction, the chip feedback instruction is transmitted to the MCU unit, the MCU unit is also used for copying the chip feedback instruction in real time, and simultaneously outputting a following feedback instruction to the switching module, and the switching module transmits the following feedback instruction to the upper computer. Therefore, the MCU unit directly copies the instruction, signals output by the upper computer can be efficiently and stably transmitted to the slave chip, and signals output by the slave chip can be transmitted to the upper computer, so that a flying wire is not required, the damage to an optical module is avoided, and the debugging system and method have universality and low cost.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (13)
1. An optical module commissioning system, comprising:
the system comprises an upper computer, a switching module and an optical module, wherein the optical module comprises an MCU unit and at least one slave chip;
the MCU unit is electrically connected with the switching module and any slave chip and is communicated with the switching module through an I2C protocol; the upper computer is connected with the switching module through a serial bus to carry out serial port communication;
The upper computer is used for outputting an upper computer instruction, the upper computer instruction is transmitted to the MCU unit through the switching module, the MCU unit is used for copying the upper computer instruction in real time and outputting a following upper computer instruction to any slave chip at the same time, and any slave chip executes the following upper computer instruction;
any slave chip is further used for outputting a chip feedback instruction, the chip feedback instruction is transmitted to the MCU unit, the MCU unit is further used for copying the chip feedback instruction in real time, and simultaneously outputting a following feedback instruction to the switching module, and the switching module transmits the following feedback instruction to the upper computer.
2. The optical module debugging system of claim 1, wherein the upper computer instructions and the chip feedback instructions each comprise periodic and/or aperiodic level signals comprising high level signals and/or low level signals.
3. The optical module debugging system of claim 1, wherein the upper computer instructions comprise write instructions and read instructions; the chip feedback instruction comprises a chip confirmation instruction and an information instruction.
4. The light module debug system of claim 1, wherein the MCU unit comprises a first data pin, a first clock pin, a second data pin, a second clock pin; any slave chip comprises a third data pin and a third clock pin; the switching module comprises a fourth data pin and a fourth clock pin;
the first data pin is electrically connected with the fourth data pin, the first clock pin is electrically connected with the fourth clock pin, the second data pin is electrically connected with the third data pin, and the second clock pin is electrically connected with the third clock pin.
5. The optical module debugging system of claim 4, wherein the level signal of the second data pin replicates the level signal of the first data pin when the upper computer outputs an upper computer instruction;
and when the upper computer receives the following feedback instruction, the level signal of the first data pin replicates the level signal of the second data pin.
6. An optical module debugging method, characterized in that it is implemented based on the optical module debugging system according to claim 5, comprising the steps of:
Detecting a level signal of a first clock pin of the MCU unit;
when the level signal of the first clock pin is at a low level, judging whether the MCU unit and the slave chip are in a release state, if not, the MCU unit copies the chip feedback instruction in real time and simultaneously outputs a following feedback instruction to the switching module; returning to the step of detecting the level signal of the first clock pin of the MCU unit;
if yes, judging whether the MCU unit and the upper computer are in a release state, if not, the MCU unit replicates the upper computer instruction in real time, simultaneously outputs the upper computer instruction to any slave chip, returns to the step of detecting the level signal of the first clock pin of the MCU unit, and if yes, maintains the release state between the MCU unit and the upper computer, between the MCU unit and the slave chip, returns to the step of detecting the level signal of the first clock pin of the MCU unit.
7. The method for debugging an optical module of claim 6, further comprising: when the level signal of the first clock pin is at a high level, judging whether the MCU unit and the slave chip are in a release state, and if so, setting the MCU unit and the upper computer to be in the release state;
If not, the MCU unit copies the upper computer instruction in real time, and outputs the upper computer instruction to any slave chip at the same time, and returns to the step of detecting the level signal of the first clock pin of the MCU unit.
8. The method according to claim 6, wherein when the level signal of the first clock pin is at a low level, determining whether the MCU unit and the slave chip are in a released state comprises:
detecting a level signal of a second data pin of the MCU unit;
when the level signal of the second data pin is at a high level, the MCU unit and the slave chip are in a release state;
when the level signal of the second data pin is at a low level, the MCU unit and the slave chip are in an unreleased state.
9. The optical module debugging method of claim 8, wherein when the MCU unit and the slave chip are in a released state, determining whether the MCU unit and the upper computer are in a released state comprises:
detecting a level signal of a first data pin of the MCU unit;
when the level signal of the first data pin is at a high level, the MCU unit and the slave chip are in a release state;
When the level signal of the first data pin is at a low level, the MCU unit and the slave chip are in an unreleased state.
10. The method according to claim 7, wherein when the level signal of the first clock pin is at a high level, determining whether the MCU unit and the slave chip are in a released state comprises:
detecting a level signal of a second data pin of the MCU unit;
when the level signal of the second data pin is at a high level, the MCU unit and the slave chip are in a release state;
when the level signal of the second data pin is at a low level, the MCU unit and the slave chip are in an unreleased state.
11. The optical module debugging method of claim 10, wherein the level signal of the first data pin is set to a high level when the level signal of the second data pin is a high level.
12. An optical module debugging method, characterized in that it is implemented based on the optical module debugging system according to claim 5, comprising the steps of:
initially detecting a level signal of a first clock pin of the MCU unit;
If the first detected level signal of the first clock pin is low level, setting the level signal of the second clock pin to be low level, the level signal of the first data pin to be high level and the level signal of the second data pin to be high level at the same time;
detecting the level signal of the first clock pin again;
if the level signal of the first clock pin detected again is low level, further detecting the level signal of the second data pin;
if the level signal of the second data pin is low level, setting the level signal of the first data pin to be low level, and returning to the step of detecting the level signal of the first clock pin again;
if the level signal of the second data pin is high level, further detecting the level signal of the first data pin;
if the level signal of the first data pin is low level, setting the level signal of the second data pin to be low level, and returning to the step of detecting the level signal of the first clock pin again;
if the level signal of the first data pin is high level, setting the level signal of the second data pin to be high level and the first data pin to be high level at the same time, and returning to the step of detecting the level signal of the first clock pin again;
And if the level signal of the first clock pin detected again is at a high level, ending.
13. The optical module commissioning method of claim 12, further comprising:
if the level signal of the first clock pin detected for the first time is high level, setting the level signal of the second clock pin of the MCU unit to be high level;
then detecting a level signal of a second data pin of the MCU unit;
if the level signal of the second data pin is high level, setting the level signal of the first data pin of the MCU unit to be high level, and detecting the level signals of the first clock pin and the first data pin again;
if the level signal of the second data pin is low level, detecting the level signals of the first clock pin and the first data pin again;
if the detected level signal of the first clock pin is high level again, the detected level signal of the first data pin is duplicated by the level signal of the second data pin;
and if the level signal of the first clock pin detected again is at a low level, ending.
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