CN116155236A - Implementation method and device of parallel IIR universal filter - Google Patents
Implementation method and device of parallel IIR universal filter Download PDFInfo
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Abstract
The invention belongs to the field of filters, and particularly relates to a method and a device for realizing a parallel IIR universal filter; the method includes dividing an output sequence into a first sequence and a second sequence; establishing an internal buffer space with the size of 2Q, parallelly reading data to be processed in a first sequence in a ping-pong buffer mode, circularly shifting and reading out Q data each time, and performing multiply-accumulate operation on the Q data by using Q multipliers; multiplexing the internal buffer space of 2Q, reading the cyclic shift access number of the data to be processed in the second sequence by adopting a ping-pong buffer mode, reading Q data by cyclic shift each time, and calculating Q-order data by adopting Q multipliers. The invention divides the output sequence of the filter into two parts for processing, and each part simultaneously processes a plurality of data in parallel, thereby improving the processing speed and efficiency; meanwhile, the invention has the characteristics of small occupation of hardware resources, high processing speed, universality and the like.
Description
Technical Field
The invention belongs to the field of filters, and particularly relates to a method and a device for realizing a parallel IIR universal filter.
Background
The IIR (infinite impulse response) filter is an infinite impulse response filter, also called a recursive filter, and has the characteristics of nonlinear phase-frequency response, infinite length of unit impulse response, low order requirement, feedback loop, high amplitude-frequency characteristic precision and the like, and has better filtering effect when compared with the FIR at the same order. Therefore, IIR filters are widely used in the fields of communication, image processing, pattern recognition, and the like.
The IIR filter has two schemes of software implementation and hardware implementation, an IIR filter algorithm is associated with the front data and the rear data of the input data to be processed, and the cumulative sum frequency of each input data is directly associated with the order of the vector data. When the software is realized, the limitation of the software implementation mode and the CPU multiply-accumulate resource is limited, and generally, one data is processed after the other data, namely, after the multiply-accumulate result of one data is processed, the next data is processed, so that the occupation condition of the CPU resource and the bus is more, and the processing speed is slower. When the hardware is realized, if the hardware is directly and completely realized according to a general IIR calculation formula, more multiplication and accumulation units are needed for synchronous processing to obtain a quicker processing effect, and more hardware resources are needed; processing time is sacrificed if resources are saved. Some designs simplify the formula of IIR in order to save resources and achieve faster processing speeds, but this approach has special requirements on input data and vector data, sacrificing some IIR performance.
Based on the above analysis, a technical problem that needs to be solved by a person skilled in the art is how to obtain a faster processing speed without adding a multiply-accumulate unit.
Disclosure of Invention
Based on the problems existing in the prior art, the invention provides a new implementation scheme, namely a method and a device for implementing a parallel IIR universal filter. Multiple groups of data are processed simultaneously in a parallel mode, so that the processing efficiency is improved; the ping-pong buf, the cyclic access, the shared multiplier resource and other modes are used, so that the resource consumption of data processing and storage is saved. The value and the length of the data to be processed and the vector data have no special requirements, and the universality is realized.
In a first aspect of the present invention, the present invention proposes a method for implementing a parallel IIR general-purpose filter, the method comprising:
dividing an output sequence into a first sequence with a length of M and a second sequence with a length of N, carrying out serial processing between the first sequence and the second sequence, and respectively carrying out parallel processing on the interiors of the first sequence and the second sequence;
determining the number of parallel processing data with the length of Q;
establishing an internal buffer space with the size of 2Q, parallelly reading data to be processed in a first sequence in a ping-pong buffer mode, circularly shifting and reading Q data from the 2Q internal buffer spaces each time, and performing multiply-accumulate operation on the Q data by using Q multipliers;
multiplexing an internal buffer space with the size of 2Q, reading data to be processed in the second sequence by adopting a ping-pong buffer mode, circularly shifting and reading Q data from the 2Q internal buffer spaces each time, and calculating Q-order data by adopting Q multipliers.
In a second aspect of the present invention, the present invention further provides an implementation apparatus of a parallel IIR general filter, where the implementation apparatus includes a configuration register, an AHB bus control module, an AMEM memory, a BMEM memory, an XMEM memory, a YMEM memory, a ping-pong buffer control module, and a multiply-accumulate module; the configuration register is connected with an AHB bus control module and a ping-pong buffer control module, and the AHB bus control module is connected with an AMEM memory, a BMEM memory, an XMEM memory and a multiplication accumulation module; the AMEM storage, the BMEM storage, the XMEM storage and the YMEM storage are connected with a ping-pong buffer control module; and the ping-pong buffer module is connected with a multiplication accumulation module.
The invention has the beneficial effects that:
the invention divides the output sequence of the filter into two parts for processing, and each part simultaneously processes a plurality of data in parallel, thereby improving the processing speed and efficiency; meanwhile, the two parts of the invention are serially processed data, and only less hardware resources are occupied; the number of the parallel processing data can be selected according to the actual situation by a person skilled in the art, and the value and the length of the data to be processed and the vector data are not particularly required, so that the parallel processing method has universality.
Drawings
Fig. 1 is a schematic structural diagram of an implementation apparatus of a parallel IIR general filter in an embodiment of the present invention;
FIG. 2 is a schematic diagram of a multiply-accumulate module according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of another multiply-accumulate module according to an embodiment of the present invention;
FIG. 4 is a flowchart of a method for implementing a parallel IIR general filter in an embodiment of the invention;
FIG. 5 is a data diagram of parallel processing data according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Fig. 1 is a schematic structural diagram of an implementation device of a parallel IIR general filter in an embodiment of the present invention, where, as shown in fig. 1, the implementation device includes a configuration register, an AHB bus control module, an AMEM memory, a BMEM memory, an XMEM memory, a YMEM memory, a ping-pong buffer control module, and a multiply-accumulate module; the configuration register is connected with an AHB bus control module and a ping-pong buffer control module, and the AHB bus control module is connected with an AMEM memory, a BMEM memory, an XMEM memory and a multiplication accumulation module; the AMEM storage, the BMEM storage, the XMEM storage and the YMEM storage are connected with a ping-pong buffer control module; and the ping-pong buffer module is connected with a multiplication accumulation module.
In the embodiment of the invention, the configuration register is connected with the configuration source module through the APB (APB_BUS), so that low power consumption and simplified interface design can be realized, and the complexity of the interface design is reduced.
In the embodiment of the invention, the AHB bus control module is connected with the data source module through the bus, and can provide a high-bandwidth interface for a large number of data transmission modules.
In the embodiment of the invention, the AMEM memory, the BMEM memory, the XMEM memory and the YMEM memory are connected with a ping-pong buffer control module, the AMEM memory and the BMEM memory are connected with a first data selector, and the XMEM memory and the YMEM memory are connected with a second data selector; the ping-pong buffer control module is respectively connected with the first data selector and the second data selector in a bidirectional manner; and the ping-pong buffer control module is connected with the YMEM memory through a bus.
In the embodiment of the present invention, the configuration register includes a plurality of configuration interfaces, where one configuration interface is connected to the AHB bus control module, and the other configuration interface is connected to the ping-pong buffer control module, for example, through a control signal line.
In the embodiment of the invention, the configuration register further comprises an input interface, and the configuration source module is connected through an APB (APB_BUS), so that low power consumption and simplified interface design can be realized, and the complexity of the interface design is reduced.
The AHB bus control module comprises a plurality of input ports and a plurality of output ports, wherein part of the output ports are respectively connected with the BMEM memory, the AMEM memory and the XMEM memory through memory read-write buses; one input port is connected with a configuration interface of the configuration register through a configuration signal, and the other input port and the other output port are connected with a data source through an AHB bus; the remaining input ports are connected to the multiply-accumulate module via a data transmission line.
In the embodiment of the invention, the AHB control module is connected with the data source module through a bidirectional AHB (AHB_BUS) BUS, so that a high-bandwidth interface can be provided for a large number of data transmission modules. In the embodiment of the invention, the AMEM memory, the BMEM memory, the XMEM memory and the YMEM memory are connected with a ping-pong buffer control module, the AMEM memory and the BMEM memory are connected with a first data selector, and the XMEM memory and the YMEM memory are connected with a second data selector; the ping-pong buffer control module is respectively connected with the first data selector and the second data selector in a bidirectional manner; and the ping-pong buffer control module is connected with the YMEM memory through a memory write bus.
In a preferred embodiment of the present invention, the AMEM memory, BMEM memory, XMEM memory and YMEM memory each have an input port and an output port, where the input ports of the AMEM memory, BMEM memory and XMEM memory are respectively connected to the output ports of the AHB bus control module through a memory write bus; the input port of the YMEM memory is connected with the ping-pong buffer control module through a memory write bus; the output ports of the AMEM memory and the BMEM memory are connected to the input of the same data selector, i.e. the first data selector, and the output ports of the XMEM memory and the YMEM memory are connected to the input of the same data selector, i.e. the second data selector.
The AMEM memory, the BMEM memory, the XMEM memory and the YMEM memory are all readable and writable memories, and the readable and writable memories can store sequence signals.
In the embodiment of the invention, the ping-pong buffer control module also comprises a plurality of input ports and a plurality of output ports, wherein one input port is connected with a configuration interface of a configuration register through a configuration signal, two input ports are respectively connected with an output end of a first data selector and an output end of a second data selector, and other input ports are consistent with the AHB bus control module in connection mode and are also connected with a multiplication accumulation module through a data transmission line. One output port is connected with the input port of the YMEM memory through a memory write bus, one output port is connected with the input end of the first data selector and the input end of the second data selector through a data transmission line as a selection channel after being split, and the other output ports are connected with the input port of the multiply-accumulate module through the data transmission line.
In the embodiment of the invention, the ping-pong buffer control module reads in Q data from the first data selector and the second data selector respectively, and after shifting and taking the input data, Q multipliers a and Q multipliers B and multiplication enabling signals are sent out, wherein the data selector refers to a circuit which can select any one of the data according to the need in the process of multi-path data transmission, and is called a data selector, also called a multi-path selector or a multi-path switch.
In the embodiment of the invention, the multiply-accumulate module comprises a plurality of input ports and a plurality of output ports, wherein all the input ports are connected with the output ports of the ping-pong buffer control module, and all the output ports are connected with the input ports of the ping-pong buffer control module and the AHB bus control module.
In the embodiment of the present invention, fig. 2 is a schematic diagram of a multiply-accumulate module in the embodiment of the present invention, taking q=4 as an example, 4 data are read out from the 8 internal buffer spaces each time in a cyclic shift manner, and 4 multipliers are used to multiply-accumulate the 4 data.
In the embodiment of the present invention, fig. 3 is a schematic diagram of another multiply-accumulate module structure according to the embodiment of the present invention, and as shown in fig. 2, taking q=4 as an example, 1 data is read out from the 8 internal buffer spaces in a cyclic shift manner each time, and 4-order data is calculated by using 4 multipliers.
Fig. 4 is a flowchart of a method for implementing a parallel IIR general filter according to an embodiment of the present invention, as shown in fig. 4, where the method includes:
dividing an output sequence into a first sequence with a length of M and a second sequence with a length of N, carrying out serial processing between the first sequence and the second sequence, and respectively carrying out parallel processing on the interiors of the first sequence and the second sequence;
in the embodiment of the invention, the output sequence of the IIR is divided into two sequences according to the calculation formula of the IIR filter, wherein serial processing is carried out between the first sequence and the second sequence, and parallel processing is respectively carried out inside the first sequence and the second sequence.
Determining the number of parallel processing data with the length of Q;
in the embodiment of the invention, the number of parallel processing data can be determined by configuring a register, and the number of parallel processing is related to the number of multipliers and accumulators of the multiply-accumulate module, so that once the number of parallel processing is determined, the corresponding number of multipliers and accumulators is required to be determined.
Establishing an internal buffer space with the size of 2Q, parallelly reading data to be processed in a first sequence in a ping-pong buffer mode, circularly shifting and reading Q data from the 2Q internal buffer spaces each time, and performing multiply-accumulate operation on the Q data by using Q multipliers;
multiplexing an internal buffer space with the size of 2Q, reading data to be processed in the second sequence by adopting a ping-pong buffer mode, circularly shifting and reading Q data from the 2Q internal buffer spaces each time, and calculating Q-order data by adopting Q multipliers.
In the embodiment of the invention, the ping-pong buffer control module can be utilized to read source data from the XMEN memory, Q data is sent to the multiply-accumulate module in a cyclic shift output mode, vector data is read from the BMEM memory, and the vector data is sent to the multiply-accumulate module.
In the embodiment of the invention, source data and vector data can be acquired through an AHB bus control module, wherein an AMEM memory is used for storing vector data A, a BMEM memory is used for storing vector data B, an XMEM memory is used for storing input data, and a YMEM memory is used for storing output data; reading source data from an XMEN memory by utilizing a ping-pong buffer control module, sending Q data to a multiply-accumulate module in a cyclic shift output mode, reading vector data from a BMEM memory, and sending the vector data to the multiply-accumulate module;
in the embodiment of the invention, the value of Q can be larger than the value of M or/and N, and the actual processing number can be adjusted according to the requirements of Q, M and N.
In the embodiment of the invention, the general calculation formula of the IIR is as follows:
wherein y [ n ]]The output sequence is represented by a sequence of outputs,
represents a first sequence, b [ k ]]Represents the kth multiplier, x [ n-k ]]Representing input data [ n-k ]]，/>
Represents a second sequence, a [ j ]]Represents the j-th multiplier, y [ n-j ]]Representing output data [ n-j ]]。
The front and back parts of the formula are processed by serial calculation respectively, and each part processes a plurality of data simultaneously in parallel, because the serial processing can share data buffering and multiplier resources. And selecting the number of data to be processed in parallel, and respectively processing the data.
The first half of the formula is processed as: and (3) setting up an internal buffer space with twice the number of parallel data, namely a 2Q data buffer space, reading data to be processed in a ping-pong manner, circularly shifting the 2Q data buffer spaces to take out Q data at a time, and performing multiply-accumulate operation by using Q multipliers to achieve the purpose of processing the Q data at a time. In the embodiment of the invention, the process of parallel processing data by adopting a ping-pong buffer mode comprises the following steps:
dividing 2Q input data of an internal buffer space with the size of 2Q into Q ping buffer data and Q pong buffer data;
2Q pieces of input data are read, and Q pieces of data are fetched downwards from the highest bit data;
continuously moving one data downwards to fetch Q data until the data of the buffer is completely fetched;
after the data of the buffer is completely fetched, updating the buffer data into the next group of data;
when the data of the pong buffer moves downwards, circularly retrieving the data of the pong buffer;
after the data of the buffer is completely fetched, updating the buffer data into the next group of data;
and circularly taking the number in 2Q data buffers, and alternately updating the data by the ping-pong buffers.
The latter half of the formula: since the data output of the latter half is related to the calculation result of the previous data, the parallel processing of the Q data cannot be performed, and therefore, the Q data processed in the former half are processed respectively in such a way that one data is simultaneously calculated in multiple steps and the calculation speed is increased. The data buffer space in the first half of the multiplexing formula also adopts a ping-pong buf mode to circularly shift the access number, and Q multiplier resources are shared to calculate Q-order data once. And (5) completing data calculation.
It will be appreciated that the calculation of each output data in the first sequence is related to the M input data preceding it, the first sequence first calculates the intermediate results of Q input data from input data X, and the second sequence is calculated from the calculation of the preceding data of the Q input data, where the calculation is independent of the Q intermediate results, and also independent of the input data, and is related only to the output results of the preceding data; in the second sequence, the first data is calculated first, after the N-order calculation is accumulated, the first data is accumulated with the intermediate result of the first data, and then the IIR result Y of the first data is calculated. The IIR output of the first data is used in calculating the second sequence of the second data. Wherein the first sequence is calculated using the input data, and no relation exists between the input data; the second sequence needs to be calculated with the output data and the output data is calculated one before the other to calculate the next, so that the output data in the second sequence is related to both the input data and the previous output data.
Fig. 5 is a data schematic diagram of parallel processing data according to an embodiment of the present invention, as shown in fig. 5, taking q=4 as an example, 1, reading 8 input data at the beginning, and then fetching 4 data downwards from the highest bit data. 2. One data is moved down to take 4 data. 3. The move down continues to fetch 4 data. 4. After the data of the buffer is completely fetched, the buffer data is updated to be the next group of data. 5. The data of the pong buffer is circularly returned to be ping-pong buffer when the data of the pong buffer moves downwards. 6. And updating the data of the buffer to be the next group of data after the data of the buffer is completely fetched. 7. And circularly taking the number in 8 data buffers, and alternately updating the data by the ping-pong buffers. Since the first half of the formula, i.e. the first sequence, and the second half of the formula, i.e. the second sequence, are not processed simultaneously, a set of multiply-accumulate modules is shared.
In the description of the present invention, it should be understood that the terms "coaxial," "bottom," "one end," "top," "middle," "another end," "upper," "one side," "top," "inner," "outer," "front," "center," "two ends," etc. indicate or are based on the orientation or positional relationship shown in the drawings, merely to facilitate description of the invention and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the invention. In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "configured," "connected," "secured," "rotated," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intermediaries, or in communication with each other or in interaction with each other, unless explicitly defined otherwise, the meaning of the terms described above in this application will be understood by those of ordinary skill in the art in view of the specific circumstances.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (10)
1. A method for implementing a parallel IIR generic filter, the method comprising:
dividing an output sequence into a first sequence with a length of M and a second sequence with a length of N, carrying out serial processing between the first sequence and the second sequence, and respectively carrying out parallel processing on the interiors of the first sequence and the second sequence;
determining the number of parallel processing data with the length of Q;
establishing an internal buffer space with the size of 2Q, parallelly reading data to be processed in a first sequence in a ping-pong buffer mode, circularly shifting and reading Q data from the 2Q internal buffer spaces each time, and performing multiply-accumulate operation on the Q data by using Q multipliers;
multiplexing an internal buffer space with the size of 2Q, reading data to be processed in the second sequence by adopting a ping-pong buffer mode, circularly shifting and reading Q data from the 2Q internal buffer spaces each time, and calculating Q-order data by adopting Q multipliers.
2. The method for implementing a parallel IIR general filter according to claim 1, wherein the output sequence division is formulated as:
wherein y [ n ]]The output sequence is represented by a sequence of outputs,
represents a first sequence, b [ k ]]Represents the kth multiplier, x [ n-k ]]Representing input data [ n-k ]]，/>
Represents a second sequence, a [ j ]]Represents the j-th multiplier, y [ n-j ]]Representing output data [ n-j ]]。
3. The method for implementing the parallel IIR general filter according to claim 1, wherein the process of parallel processing data by adopting a ping-pong buffer mode comprises the following steps:
dividing 2Q input data of an internal buffer space with the size of 2Q into Q ping buffer data and Q pong buffer data;
2Q pieces of input data are read, and Q pieces of data are fetched downwards from the highest bit data;
continuously moving one data downwards to fetch Q data until the data of the buffer is completely fetched;
when the data of the buffer is completely fetched, updating the buffer data into the next group of data;
when the data of the pong buffer moves downwards, circularly retrieving the data of the buffer;
when the data of the pong buffer is completely fetched, updating the buffer data into the next group of data;
and circularly taking the number in 2Q data buffers, and alternately updating the data by the ping-pong buffers.
4. The implementation device of the parallel IIR general filter is characterized by comprising a configuration register, an AHB bus control module, an AMEM memory, a BMEM memory, an XMEM memory, a YMEM memory, a ping-pong buffer control module and a multiply-accumulate module; the configuration register is connected with an AHB bus control module and a ping-pong buffer control module, and the AHB bus control module is connected with an AMEM memory, a BMEM memory, an XMEM memory and a multiplication accumulation module; the AMEM storage, the BMEM storage, the XMEM storage and the YMEM storage are connected with a ping-pong buffer control module; and the ping-pong buffer module is connected with a multiplication accumulation module.
5. The implementation apparatus of a parallel IIR general-purpose filter according to claim 4, wherein the AMEM memory, BMEM memory, XMEM memory, YMEM memory are all readable and writable memories.
6. The implementation apparatus of a parallel IIR general filter according to claim 4, wherein the amom memory, BMEM memory, XMEM memory and YMEM memory are connected with a ping-pong buffer control module, and the amom memory and the BMEM memory are connected with a first data selector, and the XMEM memory and the YMEM memory are connected with a second data selector; the ping-pong buffer control module is respectively connected with the first data selector and the second data selector in a bidirectional manner; and the ping-pong buffer control module is connected with the YMEM memory through a memory read bus.
7. The device for implementing the parallel IIR general filter according to claim 4, wherein the ping-pong buffer control module is connected to a first data selector and a second data selector, reads Q data from the first data selector, shifts the input data, and sends Q multipliers a and Q multipliers B, and a multiplication enable signal.
8. The device for implementing the parallel IIR general filter according to claim 4, wherein the multiplication accumulation module comprises Q multipliers and Q accumulators, each multiplier is connected with a multiplier a and a multiplier B, and the Q multipliers output respectively send the Q multipliers to the Q accumulators for accumulation.
9. The device for implementing the parallel IIR general filter according to claim 4, wherein the multiplication accumulation module further comprises Q multipliers and Q accumulators, the Q multipliers are respectively connected with a multiplier a and a multiplier B, and products output by the Q multipliers are sent to one accumulator together for accumulation.
10. The implementation apparatus of a parallel IIR general filter according to claim 8 or 9, wherein an AHB bus control module output is connected after the accumulator.
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