CN116154074A - 分辨率可调的垂直结构Micro/Nano-LED阵列芯片及其制备方法 - Google Patents
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- 238000002360 preparation method Methods 0.000 title abstract description 6
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- 239000002184 metal Substances 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims description 19
- 238000000151 deposition Methods 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 12
- 239000002070 nanowire Substances 0.000 claims description 12
- 238000003892 spreading Methods 0.000 claims description 8
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 239000003989 dielectric material Substances 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 238000005192 partition Methods 0.000 abstract description 12
- 230000000694 effects Effects 0.000 abstract description 4
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- 238000005516 engineering process Methods 0.000 description 5
- 238000009826 distribution Methods 0.000 description 4
- 238000001338 self-assembly Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
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- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 238000009827 uniform distribution Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000004720 dielectrophoresis Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000000838 magnetophoresis Methods 0.000 description 1
- 238000013041 optical simulation Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Abstract
本申请公开了分辨率可调的垂直结构Micro/Nano‑LED阵列芯片及其制备方法。本技术方案中,采用将传统大尺寸的LED外延层刻蚀成Micro/Nano‑LED阵列,并将其包裹在绝缘层中,在Micro/Nano‑LED阵列两端做接触电极,形成垂直结构芯片。该结构可以保证每个Micro/Nano‑LED与电极之间形成良好的欧姆接触,同时实现均匀发光。本Micro/Nano‑LED芯片为垂直结构,电极分布在两端,可以极大减少有源区的电流聚集效应,提高Micro/Nano‑LED的内量子效率,同时,n‑GaN侧采用高反射率的金属做电极,可以提高Micro/Nano‑LED的光提取效率。本结构的另一大优势是可以通过改变p型电极之间Micro/Nano‑LED阵列分区的大小,实现不同的显示分辨率。本结构可以通过逻辑电路控制不同n型电极与p型电极的接通和断开,从而实现调控不同Micro/Nano‑LED阵列分区的发光。
Description
技术领域
本申请涉及半导体发光器件的技术领域,尤其涉及分辨率可调的垂直结构Micro/Nano-LED阵列芯片及其制备方法。
背景技术
GaN基LED由于其高发光效率和高稳定性被广泛地运用在照明、显示和光电通信等领域。近年来,在高分辨率显示领域,Micro-LED显示技术因其具有高分辨率、微体积、高亮度和长寿命,被认为是一种终极显示技术。狭义上,Micro-LED芯片的尺寸在100μm-1μm。但是目前,由于Micro-LED芯片尺寸相较于传统芯片急剧减小,其表面积与体积之比迅速增大,大量的芯片表面缺陷会形成非辐射复合中心,严重影响芯片的内量子效率和外量子效率。Micro-LED显示技术面临的另一个巨大的问题是如何将巨量的micro-LED芯片转移到显示衬底上。在巨量转移的过程中,Micro-LED还面临着高缺陷率,低产能、高成本等问题。为了解决这些问题,许多科研人员开始研究Micro/Nano-LED显示技术。
一般mirco-LED芯片的尺寸在100μm以下,而Nano-LED芯片的尺寸则为纳米级别。相较于micro-LED,虽然Nano-LED在尺寸上更小,但是根据目前的研究,其晶体质量更好,通过改进的刻蚀技术可以实现更少的表面缺陷。正因为Nano-LED的尺寸很小,其可以通过大尺寸芯片刻蚀得到,再将其分离成大量一维纳米线结构,利用磁泳或者介电泳等技术实现自组装,从而实现了低成本的巨量转移。虽然通过一维自组装Nano-LED可以实现高分辨显示,但是并不能保证每个Nano-LED与电极之间形成良好的接触,同时也难以控制Nano-LED的均匀分布。因此,目前需要一种可以实现Nano-LED与电极之间稳定接触的芯片结构。
发明内容
有鉴于此,本申请提供分辨率可调的垂直结构Micro/Nano-LED阵列芯片及其制备方法,能够在保证每个Micro/Nano-LED与电极之间形成良好的接触的同时能够较好控制Micro/Nano-LED纳米线的垂直均匀分布。
第一方面,本申请提供一种分辨率可调的垂直结构Micro/Nano-LED阵列芯片,包括由绝缘层、ITO电流扩展层、金属导电层、p型电极和由若干个Micro/Nano-LED纳米线排布形成的Micro/Nano-LED阵列;
所述绝缘层包围在所述Micro/Nano-LED阵列的侧外围,ITO电流扩展层叠设在所述Micro/Nano-LED阵列的顶面,所述金属导电层叠设在所述Micro/Nano-LED阵列的底面,并且每个Micro/Nano-LED纳米线的n-GaN与金属导电层形成欧姆接触,p-GaN与ITO层形成欧姆接触,所述p型电极叠设在所述ITO电流扩展层上。
可选地,所述单个Micro/Nano-LED阵列芯片尺寸为150×150μm左右。
可选地,所述Micro/Nano-LED阵列分区的大小为50×50μm左右。
可选地,所述单个Micro/Nano-LED纳米线的直径为0.5μm左右。
可选地,所述金属导电层为功函数小于n-GaN的金属或者合金。
可选地,所述金属导电层为铝且其厚度为200nm。
可选地,所述绝缘层的材料为透明电介质材料。
可选地,所述p型电极为Cr/Al/Ti/Pt/Ti/Au金属层。
可选地,所述绝缘层的材料为SiO2或Al2O3。
第二方面,本申请提供一种如上述垂直结构Micro/Nano-LED阵列芯片的制备方法,其特征在于,包括以下步骤:
(1)在衬底上外延生长GaN基LED,并在p-GaN上,沉积ITO电流扩展层;
(2)激光剥离衬底,将外延层倒置在Si基板上,ITO电流扩展层与Si基板粘合接触,并在n-GaN上沉积SiO2层;
(3)在LED的n-GaN层上沉积圆形阵列光刻胶掩模层,刻蚀得到圆形阵列的SiO2层,并洗去残余光刻胶;
(4)刻蚀直到ITO电流扩展层,得到具有高深宽比的Micro/Nano-LED阵列;
(5)在Micro/Nano-LED阵列之间沉积SiO2或者Al2O3,用以形成将Micro/Nano-LED侧壁完全包裹的绝缘层,仅露出Micro/Nano-LED的n-GaN端;
(6)在Micro/Nano-LED阵列的n-GaN一侧沉积导电金属层,并退火,使导电金属层与n-GaN之间形成欧姆接触;
(7)除去Si基板,将整个芯片进行翻转,并在ITO电流扩展层上、Micro/Nano-LED阵列的两侧的上方沉积p型电极。
可选地,步骤(1)、(6)中,沉积方式为电子束蒸镀;
步骤(5)中,沉积方式为化学气相沉积或者原子层沉积。
可选地,步骤(3)中,所述刻蚀的方式为反应离子刻蚀;
步骤(4)中,所述刻蚀的方式为感应耦合等离子体刻蚀。
本申请提供的技术方案,具有以下技术效果和优点:
(1)在本申请中,将整个Micro/Nano-LED阵列设置在绝缘层的所围成的包围空间内,p型电极分布在芯片的上下两侧,这样相对于自组装的Micro/Nano-LED,保证了每个Micro/Nano-LED与电极接触良好接触。并且,这种结构避免了由自组装过程导致的Micro/Nano-LED聚集和分布不均匀的情况,保证了发光显示的均匀性和一致性。
(2)本申请中,顶面ITO电流扩展层与芯片阵列的p-GaN之间形成欧姆接触,底部金属导电层与n-GaN形成欧姆接触,电流垂直穿过芯片两端,避免了由于电流横向扩展导致的单个芯片内部电流分布不均匀,从而引起电流聚集效应,导致芯片内部温度升高,内量子效率下降。底部的金属导电层还可以将LED有源区向下的出光反射出去,提高芯片的光提取效率。
(3)本申请中,单个阵列芯片的尺寸一般为150×150μm,为典型的Mini-LED芯片的尺寸,便于芯片的转移组装。Micro/Nano-LED阵列分区的的大小一般为50×50μm,是典型的Micro-LED芯片的尺寸,用于实现超高显示分辨率。在传统的大尺寸芯片上通过刻蚀得到的Micro/Nano-LED芯片阵列,可以通过改变p型电极之间的Micro/Nano-LED芯片阵列分区的大小,来改变显示分辨率。可以通过逻辑电路控制不同n型电极与p型电极的接通和断开,从而实现不同Micro/Nano-LED阵列分区的发光。
附图说明
下面结合附图,通过对本申请的具体实施方式详细描述,将使本申请的技术方案及其它有益效果显而易见。
图1为本申请实施例提供的垂直结构Micro/Nano-LED阵列芯片的三维结构图;
图2为本申请实施例提供的垂直结构Micro/Nano-LED阵列芯片的侧视结构图;
图3为本申请实施例提供的垂直结构Micro/Nano-LED阵列芯片的制备流程示意图;
图4为本申请提供的实现不同Micro/Nano-LED阵列分区控光的俯视电路示意图;
图5为本申请实施例提供垂直结构Micro/Nano-LED阵列芯片的FDTD仿真顶部电场强度分布图。
其中,图中元件标识如下:
1-绝缘层;2-Micro/Nano-LED阵列;3-ITO电流扩展层;4-金属导电层;5-p型电极;6-衬底;7-LED外延层;8-Si基板;9-SiO2层;10-圆形阵列光刻胶掩模层;11-Micro/Nano-LED纳米线;12-电路基板;15-n型电极。
具体实施方式
下面将结合本申请实施例,对本申请实施例中的技术方案进行清楚、完整地描述。显然,所描述的实施例仅仅是本申请一部分实施例,而不是全部的实施例。基于本申请中的实施例,本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本申请保护的范围。
在本申请的描述中,需要理解的是,术语“第一”、“第二”仅用于描述目的,而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此,限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中,“多个”的含义是两个或两个以上,除非另有明确具体的限定。
在本申请的描述中,需要说明的是,除非另有明确的规定和限定,术语“安装”、“相连”、“连接”应做广义理解,例如,可以是固定连接,也可以是可拆卸连接,或一体地连接;可以是机械连接,也可以是电连接或可以相互通讯;可以是直接相连,也可以通过中间媒介间接相连,可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言,可以根据具体情况理解上述术语在本申请中的具体含义。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开,下文中对特定例子的部件和设置进行描述。当然,它们仅仅为示例,并且目的不在于限制本申请。此外,本申请可以在不同例子中重复参考数字和/或参考字母,这种重复是为了简化和清楚的目的,其本身不指示所讨论各种实施方式和/或设置之间的关系。此外,本申请提供了的各种特定的工艺和材料的例子,但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
请参考图1、图2,本申请提供垂直结构Micro/Nano-LED阵列芯片,包括:绝缘层1、Micro/Nano-LED阵列2、ITO电流扩展层3、金属导电层4和p型电极5。
具体的,所述垂直结构的Micro/Nano-LED阵列整体尺寸为150×150μm,为一般单个Mini-LED芯片尺寸大小。Micro/Nano-LED阵列2由多个圆柱形的Micro/Nano-LED纳米线排布所形成。单个Micro/Nano-LED纳米线的直径可为0.5μm,一般在1μm及以下。Micro/Nano-LED阵列的周期长度为1.5μm。两个p型电极5之间所包含的Micro/Nano-LED阵列大小可为50×50μm,为一般单个Micro-LED芯片尺寸大小。
具体的,所述垂直结构的Micro/Nano-LED阵列芯片结构中,绝缘层1材料可以为Al2O3,并将整个Micro/Nano-LED阵列包裹在其中。金属导电层4的材质可为Al,其厚度约为200nm。ITO电流扩展层3的厚度可为200nm。
请参考图3,本申请提供制备垂直结构的Micro/Nano-LED阵列芯片制备的流程为:
(1)在蓝宝石衬底6上外延生长GaN基的LED外延层7,并在LED外延层7的p-GaN上,利用电子束蒸镀技术得到200nm的ITO电流扩展层3;
(2)激光剥离蓝宝石衬底6,将外延层倒置在Si基板8上,ITO电流扩展层3与Si基板8粘合接触。并在n-GaN上沉积一层SiO2层9;
(3)利用光刻工艺在LED的n-GaN层上得到圆形阵列光刻胶掩模层10,通过反应离子刻蚀刻蚀得到圆形阵列的SiO2层9,并洗去残余光刻胶;
(4)利用感应耦合等离子体刻蚀,直到ITO电流扩展层3,得到具有高深宽比的Micro/Nano-LED阵列2;
(5)利用化学气相沉积或者原子层沉积技术沉积Al2O3在Micro/Nano-LED阵列之间,并将Micro/Nano-LED侧壁完全包裹,仅露出Micro/Nano-LED的n-GaN端,形成绝缘层1。
(6)利用电子束蒸镀的方式在Micro/Nano-LED的n-GaN一侧蒸镀一层200nm厚的Al并退火,以形成金属导电层4,使金属导电层4与n-GaN之间形成欧姆接触;
(7)除去Si基板8,将整个芯片进行翻转,并在ITO电流扩展层3上、Micro/Nano-LED阵列2的两侧上方利用电子束蒸镀条状p型电极5,一般为Cr/Al/Ti/Pt/Ti/Au金属层。
请参考图4,下面阐述本发明实现对Micro/Nano-LED阵列分区进行调控的过程。
具体的,所述Micro/Nano-LED阵列分区调控电路图,可以看到若干个Micro/Nano-LED纳米线排布在位于电路基板12上以形成Micro/Nano-LED阵列2,并且被p型电极5分成了不同的区域,通过改变p型电极5的间隔和数量来控制分区的大小,实现不同的辨率。
从图中可以看出多个p型电极5对应不同的n型电极15,可以通过逻辑电路控制不同n型电极与p型电极5的接通和断开,从而实现不同Micro/Nano-LED阵列分区的发光。
具体的,对Micro/Nano-LED阵列芯片简要模型进行FDTD光学仿真。在保留单个的Micro/Nano-LED纳米线11及Micro/Nano-LED阵列2的基本尺寸的前提下,选取Micro/Nano-LED阵列2的部分区域,提取简要模型进行仿真,其顶部和侧壁仿真电场强度如图5所示。从图5可以看到,Micro/Nano-LED芯片在顶部的出光分布均匀,表明了该结构具有一定的可行性。
以上所述实例仅仅是对本发明技术方案所做的举例说明。所设计的垂直结构Micro/Nano-LED阵列芯片不仅保证了Micro/Nano-LED两端与电极进行良好的接触,避免了又自组装带来的发光亮度分布不均匀的情况。本结构为垂直结构,其电流扩展更加均匀,提高芯片的内量子效率,同时芯片底部为高反射率的金属导电层,可以提高芯片的光提取效率。本结构中,单个阵列芯片的尺寸较大,便于芯片的巨量转移和组装。本结构还可以通过改变p型电极之间的Micro/Nano-LED阵列分区的大小,实现不同的分辨率。对于特定电极结构的Micro/Nano-LED芯片可以通过逻辑电路控制不同电极的导通与断开,实现不同阵列分区的发光。
以上所述,仅为本申请较佳的具体实施方式,但本申请的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本申请揭露的技术范围内,可轻易想到的变化或替换,都应涵盖在本申请的保护范围之内。
Claims (10)
1.一种分辨率可调的垂直结构Micro/Nano-LED阵列芯片,其特征在于,包括由绝缘层、ITO电流扩展层、金属导电层、p型电极和由若干个Micro/Nano-LED纳米线竖直排布形成的Micro/Nano-LED阵列;
所述绝缘层包围在所述Micro/Nano-LED阵列的侧外围;ITO电流扩展层叠设在所述Micro/Nano-LED阵列的顶面;所述金属导电层叠设在所述Micro/Nano-LED阵列的底面,并且每个Micro/Nano-LED纳米线的n-GaN与金属导电层形成欧姆接触,p-GaN与ITO层形成欧姆接触;所述p型电极叠设在所述ITO电流扩展层上。
2.根据权利要求1所述垂直结构Micro/Nano-LED阵列芯片,其特征在于,所述金属导电层为功函数小于n-GaN的金属或者合金。
3.根据权利要求2所述垂直结构Micro/Nano-LED阵列芯片,其特征在于,所述金属导电层为铝。
4.根据权利要求3所述垂直结构Micro/Nano-LED阵列芯片,其特征在于,所述金属导电层的厚度为200nm。
5.根据权利要求1所述垂直结构Micro/Nano-LED阵列芯片,其特征在于,所述绝缘层的材料为透明电介质材料。
6.根据权利要求1所述垂直结构Micro/Nano-LED阵列芯片,其特征在于,所述p型电极为Cr/Al/Ti/Pt/Ti/Au金属层。
7.根据权利要求5所述垂直结构Micro/Nano-LED阵列芯片,其特征在于,所述绝缘层的材料为SiO2或Al2O3。
8.一种如权利要求1所述垂直结构Micro/Nano-LED阵列芯片的制备方法,其特征在于,包括以下步骤:
(1)在衬底上外延生长GaN基LED,并在p-GaN上,沉积ITO电流扩展层;
(2)激光剥离衬底,将外延层倒置并粘合在Si基板上,ITO电流扩展层与Si基板粘合接触,并在n-GaN上沉积SiO2层;
(3)在LED的n-GaN层上沉积圆形阵列光刻胶掩模层,刻蚀得到圆形阵列的SiO2层,并洗去残余光刻胶;
(4)刻蚀直到ITO电流扩展层,得到具有高深宽比的Micro/Nano-LED阵列;
(5)在Micro/Nano-LED阵列之间沉积SiO2或者Al2O3,以形成将Micro/Nano-LED侧壁完全包裹的绝缘层,仅露出Micro/Nano-LED的n-GaN端;
(6)在Micro/Nano-LED阵列的n-GaN一侧沉积导电金属层,并退火,使导电金属层与n-GaN之间形成欧姆接触;
(7)除去Si基板,将整个芯片进行翻转,并在ITO电流扩展层上、Micro/Nano-LED阵列的两侧的上方沉积p型电极。
9.根据权利要求8所述制备方法,其特征在于,步骤(1)、(6)中,沉积方式为电子束蒸镀;
步骤(5)中,沉积方式为化学气相沉积或者原子层沉积。
10.根据权利要求8所述制备方法,其特征在于,步骤(4)中,所述刻蚀的方式为感应耦合等离子体刻蚀;
步骤(3)中,所述刻蚀的方式为反应离子刻蚀。
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