CN116153979A - LDMOS terminal structure and manufacturing method thereof - Google Patents

LDMOS terminal structure and manufacturing method thereof Download PDF

Info

Publication number
CN116153979A
CN116153979A CN202211698844.9A CN202211698844A CN116153979A CN 116153979 A CN116153979 A CN 116153979A CN 202211698844 A CN202211698844 A CN 202211698844A CN 116153979 A CN116153979 A CN 116153979A
Authority
CN
China
Prior art keywords
field plate
substrate
epitaxial layer
region
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202211698844.9A
Other languages
Chinese (zh)
Other versions
CN116153979B (en
Inventor
王畅畅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suzhou Huatai Electronics Co Ltd
Original Assignee
Suzhou Huatai Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suzhou Huatai Electronics Co Ltd filed Critical Suzhou Huatai Electronics Co Ltd
Priority to CN202211698844.9A priority Critical patent/CN116153979B/en
Publication of CN116153979A publication Critical patent/CN116153979A/en
Application granted granted Critical
Publication of CN116153979B publication Critical patent/CN116153979B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The LDMOS terminal structure comprises a substrate, an epitaxial layer, a body region and a drift region, wherein the epitaxial layer and the substrate are arranged in a stacked mode, the body region and the drift region are arranged in the epitaxial layer in a spaced mode, doping types of the epitaxial layer and the body region are the same, doping types of the drift region and the epitaxial layer are different, and doping concentration of the drift region is larger than that of the epitaxial layer; the field plate structure is located one side of the epitaxial layer far away from the substrate, the field plate structure comprises a field plate base and an arc-shaped field plate located on one side of the field plate base, a first through hole is formed between the field plate base and the arc-shaped field plate in a surrounding mode, projection of the arc-shaped field plate in the base covers part of the drift region, and projection of the epitaxial layer between the body region and the drift region in the field plate structure is located in the first through hole. The high breakdown voltage of the LDMOS device is ensured, and the high performance of the semiconductor device is further ensured.

Description

LDMOS terminal structure and manufacturing method thereof
Technical Field
The application relates to the field of semiconductors, in particular to an LDMOS terminal structure and a manufacturing method of the LDMOS terminal structure.
Background
The high-voltage LDMOS (Laterally Diffused Metal Oxide Semiconductor) device is widely applied to industrial equipment, scientific instruments, medical equipment and other infrastructure supporting social development and daily life at present, and reasonable terminal design has important significance in the aspects of ensuring higher breakdown voltage of the device and improving the robustness of the device for the high-voltage LDMOS device.
The layout design of the high-voltage LDMOS device mainly comprises three main schemes, namely a circular layout, a runway-shaped layout and an interdigital layout, wherein the circular layout and the runway-shaped layout are mainly aimed at the high-voltage device with small passing current, and for the LDMOS device with large passing current, the interdigital layout is generally used because the whole grid length is large, so that a drain wrap-source structure is introduced at the interdigital terminal, and because the high voltage is applied to the drain and wraps the source, the electric field lines are concentrated and point to the source, the electric field is converged, so that the breakdown voltage of the LDMOS device is caused to be lower in advance, and the breakdown voltage of the whole LDMOS device cannot reach an ideal design value, therefore, the LDMOS device with large-current working requirements is aimed at the high-voltage LDMOS device, especially the LDMOS device with the interdigital layout.
Therefore, a terminal design is needed to ensure that the breakdown voltage of the LDMOS device is high, that is, the terminal structure of the drain-to-source junction is specially designed, so that the improvement of the breakdown voltage is a critical device design optimization direction, thereby ensuring that the robustness of the high-voltage LDMOS device is good.
The above information disclosed in the background section is only for enhancement of understanding of the background art from the technology described herein and, therefore, may contain some information that does not form the prior art that is already known in the country to a person of ordinary skill in the art.
Disclosure of Invention
The main purpose of the application is to provide an LDMOS terminal structure and a manufacturing method of the LDMOS terminal structure, so as to solve the problem of poor performance of a device due to low breakdown voltage of the device in the prior art.
According to an aspect of an embodiment of the present invention, there is provided an LDMOS terminal structure, the LDMOS terminal structure including a substrate, an epitaxial layer, a body region and a drift region, wherein the substrate includes a substrate, the epitaxial layer is located on a surface of the substrate, the body region and the drift region are disposed in the epitaxial layer in a spaced manner, doping types of the epitaxial layer and the body region are the same, doping types of the drift region and the epitaxial layer are different, and doping concentration of the drift region is greater than that of the epitaxial layer; the field plate structure is located the epitaxial layer keep away from one side of substrate, just the field plate structure includes field plate portion and is located the arc field plate of field plate portion one side, field plate portion with arc field plate contact sets up, the field plate structure has first through-hole, first through-hole is located field plate portion with between the arc field plate, the projection of arc field plate in the basement covers some drift region, the projection of field plate portion in the basement covers some the body region, the body region with the projection of epitaxial layer in the field plate structure between the drift region is located in the first through-hole.
Optionally, the base further comprises a source contact region, a drain contact region, a source and a drain, wherein the source contact region is located in the body region, a surface of the source contact region away from the substrate is flush with a surface of the epitaxial layer away from the substrate, and doping types of the source contact region and the body region are different; the drain contact region is positioned in the drift region, the surface of the drain contact region, which is far away from the substrate, is flush with the surface of the drift region, which is far away from the substrate, and the doping type of the drain contact region is the same as that of the drift region; the source electrode is positioned on a part of the surface of the source contact region, which is far away from the substrate; the drain electrode is located on a portion of a surface of the drain contact region remote from the substrate.
Optionally, the LDMOS terminal structure further includes a gate dielectric layer, a gate electrode, and a dielectric layer, where the gate dielectric layer is located on a portion of a surface of the substrate, the gate dielectric layer covers a portion of the body region and a portion of the epitaxial layer, and the gate dielectric layer is not in contact with the source contact region; the grid electrode is positioned on the surface, far away from the substrate, of the grid dielectric layer, and the projection of the grid electrode in the field plate structure is positioned in the first through hole; the gate dielectric layer, the gate electrode and the surface of the epitaxial layer, which is far away from the substrate, are covered by the dielectric layer, the surface of the dielectric layer, which is far away from the epitaxial layer, is a plane, the source electrode and the drain electrode penetrate through the dielectric layer, and the field plate structure is positioned on the surface of the dielectric layer, which is far away from the substrate.
Optionally, the epitaxial layer is located on a part of a predetermined surface of the substrate, the LDMOS terminal structure further comprises a first metal layer, the first metal layer is located on another part of the predetermined surface of the substrate, a surface of the first metal layer away from the substrate is flush with a surface of the dielectric layer away from the substrate, the first metal layer is used for electrically connecting the source contact region and the substrate, and the field plate structure is in contact with the first metal layer.
Optionally, the LDMOS terminal structure further includes a second metal layer, the second metal layer is located on a portion of the surface of the dielectric layer away from the substrate, the second metal layer is in contact with the drain electrode, the second metal layer is spaced from the field plate structure, and the second metal layer and the field plate structure expose a portion of the dielectric layer.
Optionally, the doping type of the epitaxial layer is P-type, and the doping type of the drift region is N-type.
According to another aspect of the present application, there is further provided a method for manufacturing an LDMOS terminal structure, the method including: providing a substrate, wherein the substrate comprises a substrate, an epitaxial layer, a body region and a drift region, the epitaxial layer is positioned on the surface of the substrate, the body region and the drift region are arranged in the epitaxial layer in a space mode, the doping types of the epitaxial layer and the body region are the same, the doping types of the drift region and the epitaxial layer are different, and the doping concentration of the drift region is larger than that of the epitaxial layer; the field plate structure comprises a field plate body and an arc-shaped field plate positioned on one side of the field plate body, the field plate body is in contact with the arc-shaped field plate, the field plate structure is provided with a first through hole, the first through hole is positioned between the field plate body and the arc-shaped field plate, the projection of the arc-shaped field plate in the substrate covers part of the drift region, the projection of the field plate body in the substrate covers part of the body region, and the projection of the epitaxial layer between the body region and the drift region in the field plate structure is positioned in the first through hole.
Optionally, providing a substrate, comprising: providing the substrate and the epitaxial layer which are stacked; forming a gate dielectric layer on a part of the surface of the epitaxial layer, which is far away from the substrate, and forming a gate on the surface of the gate dielectric layer, which is far away from the base; and performing ion implantation in the gate dielectric layer and the epitaxial layer at two sides of the gate to form a body region, a drift region, a source contact region and a drain contact region, wherein the gate dielectric layer covers part of the body region and part of the epitaxial layer, the gate dielectric layer is not contacted with the source contact region, the projection of the gate dielectric layer and the gate in the field plate structure is positioned in the first through hole, the source contact region is positioned in the body region, the surface of the source contact region, which is far away from the substrate, is flush with the surface of the epitaxial layer, which is far away from the substrate, the doping type of the source contact region is different from that of the body region, the drain contact region is positioned in the drift region, the surface of the drain contact region, which is far away from the substrate, is not contacted with the surface of the drift region, which is far away from the substrate, and the doping type of the drain contact region is flush with that of the drift region.
Optionally, forming a gate dielectric layer on a portion of a surface of the epitaxial layer away from the substrate, and forming a gate on a surface of the gate dielectric layer away from the base, including: forming a laminated preparation gate dielectric layer and a preparation gate on the surface of the epitaxial layer, which is far away from the substrate; and removing part of the preparation gate dielectric layer and part of the preparation gate, forming the gate dielectric layer by the rest of the preparation gate dielectric layer, and forming the gate by the rest of the preparation gate.
Optionally, before forming the field plate structure on a side of the epitaxial layer remote from the substrate, the method further comprises: forming a preparation medium layer on the exposed surface of the epitaxial layer, wherein the surface of the preparation medium layer, which is far away from the epitaxial layer, is a plane, and the field plate structure is positioned on the surface of the preparation medium layer, which is far away from the substrate; removing part of the preparation medium layer to form a second through hole and a third through hole, wherein the second through hole and the third through hole expose part of the source contact area and part of the drain contact area respectively; removing part of the preparation medium layer, part of the source contact region, part of the body region and part of the epitaxial layer to form a fourth through hole, wherein part of the substrate is exposed by the fourth through hole, and the rest of the preparation medium layer forms a medium layer; and forming metal materials in the second through hole, the third through hole and the fourth through hole, and respectively forming a source electrode, a drain electrode and a first metal layer, wherein the first metal layer is used for electrically connecting the source contact area and the substrate, and the field plate structure is in contact with the first metal layer.
Optionally, forming a field plate structure on a side of the epitaxial layer away from the substrate, including: forming a preparation field plate structure on the surface of the dielectric layer far away from the substrate; and removing part of the preparation field plate structure to expose part of the dielectric layer, wherein the rest of the preparation field plate structure forms the field plate structure and a second metal layer which are arranged at intervals, and the second metal layer is in contact with the drain electrode.
By applying the technical scheme, the LDMOS terminal structure comprises a substrate and a field plate structure, wherein the substrate comprises a substrate, an epitaxial layer, a body region and a drift region, the epitaxial layer and the substrate are arranged in a stacked mode, the body region and the drift region are arranged in the epitaxial layer in a spaced mode, doping types of the epitaxial layer and the body region are the same, doping types of the drift region and the epitaxial layer are different, and doping concentration of the drift region is larger than that of the epitaxial layer; the field plate structure is located the epitaxial layer keep away from one side of substrate, just the field plate structure includes field plate portion and is located the arc field plate of field plate portion one side, field plate portion with arc field plate contact sets up, in addition, the field plate structure has first through-hole, field plate portion with enclose between the arc field plate first through-hole, the projection of arc field plate in the basement covers the part drift region, the projection of field plate portion in the basement covers the part the body region, the body region with the projection of epitaxial layer in the field plate structure between the drift region is located in the first through-hole. Compared with the problem of poor performance of a device caused by lower breakdown voltage of the device in the prior art, the LDMOS terminal structure is characterized in that the substrate comprising the substrate, the epitaxial layer, the body region and the drift region is provided, in addition, the LDMOS terminal structure further comprises the field plate structure, the field plate structure comprises the field plate body and the arc-shaped field plate, the arc-shaped field plate is projected in the substrate to cover part of the drift region, so that electric field distribution in the drift region can be optimized through the field plate structure, in addition, the projection of the epitaxial layer between the body region and the drift region in the field plate structure is positioned in the first through hole, namely, the field plate structure enables part of the epitaxial layer to be hollowed out, the field plate structure has smaller influence on the electric field of the epitaxial layer, the electric field distribution of the LDMOS device is optimized, the breakdown voltage of the LDMOS device is guaranteed to be higher, and the performance of the semiconductor device is guaranteed to be better.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:
FIG. 1 illustrates a schematic structure obtained after forming a pre-gate according to one embodiment of the present application;
fig. 2 shows a schematic structural diagram obtained after forming a gate dielectric layer and a gate according to an embodiment of the present application;
FIG. 3 shows a schematic structural diagram obtained after forming a substrate by implantation according to one embodiment of the present application;
FIG. 4 shows a schematic structural diagram obtained after forming a preliminary dielectric layer according to an embodiment of the present application;
fig. 5 shows a schematic structural diagram obtained after forming the second, third and fourth through holes according to an embodiment of the present application;
fig. 6 shows a schematic structural diagram obtained after forming a source, a drain and a first metal layer according to an embodiment of the present application;
FIG. 7 illustrates a schematic structure obtained after formation of a preliminary field plate structure in accordance with one embodiment of the present application;
fig. 8 shows a schematic structural diagram of an LDMOS terminal structure according to an embodiment of the present application;
Fig. 9 shows a schematic top view of an LDMOS termination structure according to an embodiment of the present application;
fig. 10 is a flow chart illustrating a method for fabricating an LDMOS terminal structure according to an embodiment of the application.
Wherein the above figures include the following reference numerals:
10. a substrate; 20. a field plate structure; 30. a gate dielectric layer; 40. a gate; 50. a dielectric layer; 60. a first metal layer; 70. a second metal layer; 80. preparing a gate dielectric layer; 90. a preliminary gate; 100. preparing a dielectric layer; 101. a substrate; 102. an epitaxial layer; 103. a body region; 104. a drift region; 105. a source contact region; 106. a drain contact region; 107. a source electrode; 108. a drain electrode; 110. a second through hole; 120. a third through hole; 130. a fourth through hole; 140. preparing a field plate structure; 201. a field plate body; 202. an arc field plate; 203. a first through hole.
Detailed Description
It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
In order to make the present application solution better understood by those skilled in the art, the following description will be made in detail and with reference to the accompanying drawings in the embodiments of the present application, it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, shall fall within the scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the present application described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Furthermore, in the description and in the claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As described in the background art, in order to solve the problem in the prior art that the device performance is poor due to the low breakdown voltage of the device, in an exemplary embodiment of the present application, an LDMOS terminal structure and a method for manufacturing the LDMOS terminal structure are provided.
According to an exemplary embodiment of the present application, as shown in fig. 8 and 9, there is provided an LDMOS terminal structure, where the LDMOS terminal structure includes a substrate 10 and a field plate structure 20, where the substrate 10 includes a substrate 101, an epitaxial layer 102, a body region 103 and a drift region 104, the epitaxial layer 102 is located on a surface of the substrate 101, the body region 103 and the drift region 104 are spaced apart from each other and are disposed in the epitaxial layer 102, doping types of the epitaxial layer 102 and the body region 103 are the same, doping types of the drift region 104 and the epitaxial layer 102 are different, and a doping concentration of the drift region 104 is greater than a doping concentration of the epitaxial layer 102; the field plate structure 20 is located on a side of the epitaxial layer 102 away from the substrate 101, and the field plate structure 20 includes a field plate base 201 and an arc field plate 202 located on a side of the field plate base 201, the field plate base 201 is disposed in contact with the arc field plate 202, the field plate structure 20 has a first through hole 203, the first through hole 203 is located between the field plate base 201 and the arc field plate 202, a projection of the arc field plate 202 in the substrate 10 covers the drift region 104, a projection of the field plate base 201 in the substrate 10 covers the body region 103, and a projection of the epitaxial layer 102 between the body region 103 and the drift region 104 in the field plate structure 20 is located in the first through hole 203.
The LDMOS terminal structure comprises a substrate, an epitaxial layer, a body region and a drift region, wherein the substrate comprises the substrate, the epitaxial layer and the substrate are stacked, the body region and the drift region are arranged in the epitaxial layer in a spaced mode, the doping types of the epitaxial layer and the body region are the same, the doping types of the drift region and the epitaxial layer are different, and the doping concentration of the drift region is larger than that of the epitaxial layer; the field plate structure is located on one side of the epitaxial layer far away from the substrate, the field plate structure comprises a field plate base and an arc-shaped field plate located on one side of the field plate base, the field plate base is in contact with the arc-shaped field plate, the field plate structure is provided with a first through hole, the first through hole is formed between the field plate base and the arc-shaped field plate in a surrounding mode, a projection covering part of the arc-shaped field plate in the substrate covers the drift region, a projection covering part of the field plate base in the substrate covers the body region, and a projection of the epitaxial layer between the body region and the drift region in the field plate structure is located in the first through hole. Compared with the problem of poor performance of a device caused by lower breakdown voltage of the device in the prior art, the LDMOS terminal structure of the application comprises the substrate, the epitaxial layer, the body region and the base of the drift region, and further comprises the field plate structure, the field plate structure comprises the field plate body and the arc-shaped field plate, the projection of the arc-shaped field plate in the base covers part of the drift region, so that the electric field distribution in the drift region can be optimized through the field plate structure, and in addition, the projection of the epitaxial layer between the body region and the drift region in the field plate structure is located in the first through hole, namely, the field plate structure enables part of the epitaxial layer to be hollowed out, the field plate structure has small influence on the electric field of the epitaxial layer, the electric field distribution of the LDMOS device is optimized, the breakdown voltage of the device is guaranteed to be higher, and the performance of the semiconductor device is guaranteed to be better.
In addition, as the body region and the drift region are arranged at intervals, and the doping concentration of the drift region is larger than that of the epitaxial layer, the epitaxial layer with smaller concentration exists between the body region and the drift region, and the doping types of the epitaxial layer and the drift region are different, so that a reverse PN junction is formed between the epitaxial layer and the drift region, and pressure bearing can be carried out through the reverse PN junction, the electric field distribution of the semiconductor device is guaranteed to be good, the breakdown voltage of the semiconductor device is guaranteed to be high, and the performance of the semiconductor device is further guaranteed to be good.
Specifically, the principle of the field plate modulating the breakdown voltage and the surface electric field of the drift region is described as follows: as shown in fig. 8, when the doping types of the epitaxial layer 102, the body region 103, and the source contact region 105 are P-type, and the doping types of the drift region 104 and the drain contact region 106 are N-type, and when the entire device receives an external breakdown voltage, a positive voltage is applied to the electrode corresponding to the drain electrode 108, the electrode corresponding to the source electrode 107 and the first metal layer 60 is shorted to ground, in which case, a positive voltage is applied to the drain electrode 108, electrons in the N-region gather in the region of the drain contact region 106 having a high potential, holes in the P-region gather in the region of the source contact region 105 having a low potential, and similarly, the holes in the P-region expand in the depletion region at the junction interface formed by the epitaxial layer 102 and the drift region 104 until the spatial integral of the electric field formed by the fixed charges in the depletion region is equal to the external applied voltage, and the depletion region expansion stops, at which time, the PN junction reaches a reverse bias balanced state at a certain voltage. It will be appreciated that the location of the strongest electric field intensity of the entire reverse biased junction should occur at the junction interface, and in the ideal case of uniform doping, the electric field intensity should decrease linearly along the junction interface to the depletion region boundary, and the electric field intensity at both sides of the junction interface forms a triangle (as shown by the triangle dashed line in fig. 8), and the area (integral) of the triangle is the reverse bias voltage that the reverse biased junction can withstand. Specifically, fig. 8 is a schematic diagram showing that the electric field intensities of the N-type region of the drift region 104 and the P-type region of the epitaxial layer 102 are distributed along the vertical junction interface in the two directions, after the ground field plate (the field plate base 201 and the arc field plate 202) is introduced, it may be assumed that the field plate gradually approaches to the drain electrode as a low potential point, so as to promote the electrons in the region of the drain contact region 106 to be more concentrated, i.e. to assist the depletion of the non-depleted region near the drain contact region 106, and the vertex of the corresponding triangular electric field in the drift region 104 may move to the right, so that the triangular area is increased, thereby ensuring the increase of the bearing voltage of the LDMOS terminal structure, and at the same time, adjusting the height of the field plate, i.e. the distance near the N region, may promote the electric field intensity at the corresponding position of the N region, i.e. the edge of the triangular electric field near the drain contact region 106 may bulge, and similarly enhance the bearing voltage of the device. However, the P-type region is covered in the process that the field plate extends from the region of the drain contact region 106 to the upper portion of the N-type region across the PN junction interface, which leads to pressure-bearing reduction of the P-type region.
According to an embodiment of the present application, as shown in fig. 8 and 9, the substrate 10 further includes a source contact region 105, a drain contact region 106, a source 107, and a drain 108, wherein the source contact region 105 is located in the body region 103, a surface of the source contact region 105 away from the substrate 101 is flush with a surface of the epitaxial layer 102 away from the substrate 101, and doping types of the source contact region 105 and the body region 103 are different; the drain contact region 106 is located in the drift region 104, a surface of the drain contact region 106 away from the substrate 101 is flush with a surface of the drift region 104 away from the substrate 101, and a doping type of the drain contact region 106 is the same as a doping type of the drift region 104; the source electrode 107 is located on a portion of the surface of the source contact region 105 remote from the substrate 101; the drain electrode 108 is located on a portion of the surface of the drain contact region 106 remote from the substrate 101. The substrate further comprises the source contact region, the drain contact region, the source electrode and the drain electrode, so that the source electrode can be led out through the source contact region, the drain electrode can be led out through the drain contact region, the performance of the LDMOS device can be realized, and the better performance of the LDMOS device is further ensured.
According to another embodiment of the present application, as shown in fig. 8 and 9, the LDMOS terminal structure further includes a gate dielectric layer 30, a gate electrode 40 and a dielectric layer 50, wherein the gate dielectric layer 30 is located on a portion of the surface of the substrate 10, the gate dielectric layer 30 covers a portion of the body region 103 and a portion of the epitaxial layer 102, and the gate dielectric layer 30 is not in contact with the source contact region 105; the gate electrode 40 is located on a surface of the gate dielectric layer 30 away from the substrate 10, and projections of the gate dielectric layer 30 and the gate electrode 40 in the field plate structure 20 are located in the first through hole 203; the dielectric layer 50 covers the gate dielectric layer 30, the gate electrode 40, and the surface of the epitaxial layer 102 away from the substrate 101, the surface of the dielectric layer 50 away from the epitaxial layer 102 is a plane, the source electrode 107 and the drain electrode 108 penetrate the dielectric layer 50, and the field plate structure 20 is located on the surface of the dielectric layer 50 away from the substrate 10. The LDMOS terminal structure further comprises the gate dielectric layer, the grid electrode and the dielectric layer, so that the performance of the LDMOS device can be realized through the grid electrode, and the better performance of the LDMOS device is further ensured.
In one embodiment, as shown in fig. 8, the surface area of the gate electrode 40 near the substrate 10 is smaller than the surface area of the gate electrode 40 near the substrate 10. That is, the angle of the grid electrode, which is close to the substrate, is not a right angle, so that the grid electrode has an optimization function on the electric field of the substrate, the breakdown voltage of the semiconductor device is guaranteed to be higher, and the performance of the semiconductor device is further guaranteed to be better.
In order to further ensure that the performance of the LDMOS termination structure is better, according to a further embodiment of the present application, the epitaxial layer is located on a portion of the predetermined surface of the substrate, as shown in fig. 8 and 9, the LDMOS termination structure further comprises a first metal layer 60, the first metal layer 60 is located on another portion of the predetermined surface of the substrate 101, and a surface of the first metal layer 60 remote from the substrate 101 is level with a surface of the dielectric layer 50 remote from the substrate 101, the first metal layer 60 is used for electrically connecting the source contact region 105 to the substrate 101, and the field plate structure 20 is in contact with the first metal layer 60. Because the epitaxial layer is positioned on the preset surface of the part of the substrate, and the first metal layer is positioned on the preset surface of the other part of the substrate, namely the epitaxial layer is contacted with the first metal layer and is positioned on the substrate, and because the first metal layer is used for electrically connecting the source contact area and the substrate, the source contact area can be connected with the substrate through the first metal layer, namely the grounding is realized, and the device of the LDMOS is further ensured to be better.
Specifically, the predetermined surface is a surface of the substrate adjacent to the epitaxial layer, the epitaxial layer is located on a part of the surface of the substrate, the first metal layer is in contact with the epitaxial layer, and the first metal layer is located on another part of the predetermined surface of the substrate.
According to an embodiment of the present application, as shown in fig. 8 and 9, the LDMOS terminal structure further includes a second metal layer 70, the second metal layer 70 is located on a portion of the surface of the dielectric layer 50 away from the substrate 10, the second metal layer 70 is in contact with the drain 108, the second metal layer 70 is spaced apart from the field plate structure 20, and the second metal layer 70 and the field plate structure 20 expose a portion of the dielectric layer 50. The LDMOS terminal structure further comprises the second metal layer, and the second metal layer is in contact with the drain electrode, so that the drain contact region can be led out through the second metal layer and the drain electrode, namely, the drain electrode and the drain contact region can be connected through the second metal layer, and the better performance of the LDMOS device is further ensured.
According to another embodiment of the present application, the material of the field plate structure comprises aluminum. Of course, the structure of the field plate is not limited to aluminum, and other materials such as tungsten and copper may be selected, and the structure is not limited thereto.
In order to further ensure that the performance of the LDMOS device is better, according to still another embodiment of the present application, the doping type of the epitaxial layer is P-type, and the doping type of the drift region is N-type. Because the doping type of the epitaxial layer is P type, the doping type of the drift region is N type, namely, a reverse PN junction is formed between the epitaxial layer of P type and the drift region of N type, so that pressure bearing can be carried out through the formed reverse PN junction, the distribution optimization of the electric field of the LDMOS terminal device is realized, the breakdown voltage of the LDMOS is ensured to be higher, and the performance of the LDMOS device is further ensured to be better.
Specifically, the terminal voltage-resistant structure of the current LDMOS device is generally a reverse PN junction formed between a P heavily doped region at a source and an N-type drift region, and the main design thought of the terminal structure of the current drain-wrapped source is to add a P shallow doped region between the P heavily doped region of the source and the N-type drift region of the drain, so that the voltage-resistant value of the whole terminal is improved by forming a more slowly-changed PN junction, the possibility of process implementation is generally considered, the P shallow doped region is generally borne by a P-type epitaxial layer, but the electric field strength is rapidly reduced within the range of the N-type drift region due to the injection concentration difference between the P-type epitaxial layer and the N-type drift region, so that the breakdown voltage lifting amplitude of the LDMOS device is limited, the surface electric field of the N-type region can be optimized for the reverse PN junction through a field plate, and the breakdown voltage is lifted, however, the P-type region is covered by the design field plate, the voltage-resistant equipotential line is produced due to the low potential of the field plate, and the strength of the P-type drift region is reduced with the voltage-resistant force of the P-type region. According to the LDMOS terminal structure, the field plate structure comprising the field plate body and the arc-shaped field plate is designed, on one hand, the electric field distribution of the terminal is optimized through bearing the reverse PN junction formed between the P-type epitaxial layer and the N-type drift region, on the other hand, the electric field distribution in the drift region can be optimized through the arc-shaped field plate above the N-type drift region, on the other hand, due to the fact that the projection of the epitaxial layer between the body region and the drift region in the field plate structure is located in the first through hole, namely the field plate structure corresponding part of the P-type epitaxial layer is hollowed out, the electric field effect of the field plate structure on the P-type epitaxial layer is smaller, the electric field optimization effect on the P-type epitaxial layer region is achieved, the breakdown voltage of the LDMOS device is further guaranteed to be higher, and the LDMOS device is further guaranteed to be better in performance.
In a specific embodiment, through carrying out actual potential line distribution test to the LDMOS terminal structure of the non-hollowed-out field plate in the prior art and the LDMOS terminal structure comprising the hollowed-out field plate, it can be obtained that although the field plate of the LDMOS terminal structure in the prior art can play a role in enhancing the surface electric field of NLDD (N-type low doped drain region), the equipotential lines are pinned by the zero potential field plate, so that the bearing capacity of the P-type epitaxial region of the LDMOS terminal structure is reduced, the maximum bearing capacity of the LDMOS terminal structure in the prior art is not exerted, the actual test can be obtained, the maximum bearing capacity of the LDMOS terminal structure in the prior art is 50V, part of electric potential lines of a drain end are released through the field plate structure provided with the hollowed-out field plate, so that the bearing capacity of the epitaxial layer is enhanced, and the field plate structure (namely the hollowed-out field plate) does not drop too much on the surface electric field enhancement effect of the NLDD.
According to the embodiment of the application, a manufacturing method of the LDMOS terminal structure is further provided.
Fig. 10 is a flowchart of a method for fabricating an LDMOS termination structure according to an embodiment of the application. As shown in fig. 10, the method includes the steps of:
step S101, as shown in fig. 3, providing a base 10, where the base 10 includes a substrate 101, an epitaxial layer 102, a body 103 and a drift region 104, the epitaxial layer 102 is located on the surface of the substrate 101, the body 103 and the drift region 104 are spaced apart from each other and are disposed in the epitaxial layer 102, the doping types of the epitaxial layer 102 and the body 103 are the same, the doping types of the drift region 104 and the epitaxial layer 102 are different, and the doping concentration of the drift region 104 is greater than the doping concentration of the epitaxial layer 102;
in step S102, as shown in fig. 8 and 9, a field plate structure 20 is formed on a side of the epitaxial layer 102 away from the substrate 101, the field plate structure 20 includes a field plate base 201 and an arc field plate 202 located on a side of the field plate base 201, the field plate base 201 is disposed in contact with the arc field plate 202, the field plate structure 20 has a first through hole 203, the first through hole 203 is located between the field plate base 201 and the arc field plate 202, a projection of the arc field plate 202 covers the drift region 104 in the base 10, a projection of the field plate base 201 covers the body region 103 in the base 10, and a projection of the epitaxial layer 102 between the body region 103 and the drift region 104 in the field plate structure 20 is located in the first through hole 203.
In the method for manufacturing the LDMOS terminal structure, firstly, a substrate is provided, the substrate comprises a substrate, an epitaxial layer, a body region and a drift region, the epitaxial layer is positioned on the surface of the substrate, the body region and the drift region are arranged in the epitaxial layer in a spacing mode, the doping types of the epitaxial layer and the body region are the same, the doping types of the drift region and the epitaxial layer are different, and the doping concentration of the drift region is larger than that of the epitaxial layer; then, a field plate structure is formed on a side of the epitaxial layer away from the substrate, the field plate structure includes a field plate base and an arc field plate located on a side of the field plate base, the field plate base is in contact with the arc field plate, the field plate structure has a first through hole, the first through hole is located between the field plate base and the arc field plate, a projection of the arc field plate in the substrate covers the drift region, a projection of the field plate base in the substrate covers the body region, and a projection of the epitaxial layer between the body region and the drift region in the field plate structure is located in the first through hole. Compared with the problem of poor performance of a device caused by lower breakdown voltage of the device in the prior art, the manufacturing method of the LDMOS terminal structure of the application comprises the steps of providing the substrate comprising the substrate, the epitaxial layer, the body region and the drift region, forming the field plate structure on one side of the epitaxial layer far away from the substrate, wherein the field plate structure comprises the field plate body and the arc-shaped field plate, and the arc-shaped field plate covers part of the drift region due to the fact that the projection of the arc-shaped field plate in the substrate covers the drift region, so that the electric field distribution in the drift region can be optimized through the field plate structure, and in addition, the projection of the epitaxial layer between the body region and the drift region in the field plate structure is located in the first through hole, namely, the field plate structure enables part of the epitaxial layer to be hollowed out, the electric field effect of the field plate structure on the epitaxial layer is smaller, the electric field distribution of the LDMOS device is optimized, the breakdown voltage of the device is higher, and the semiconductor device is guaranteed to be better in performance.
Specifically, compared with the prior art, the process for forming the substrate and the field plate structure does not need additional design or additional process steps, and in the manufacturing process of the LDMOS terminal structure, the process integration level of the LDMOS terminal structure is high and simple only by designing the hollowed-out field plate structure.
In a specific embodiment, the position of the field plate structure and/or the width of the first through hole may be adjusted according to actual requirements, so that the breakdown voltage of the LDMOS device is higher.
According to a specific embodiment of the present application, there is provided a substrate comprising: as shown in fig. 1, the substrate 101 and the epitaxial layer 102 are provided as a stack; as shown in fig. 2, a gate dielectric layer 30 is formed on a portion of the surface of the epitaxial layer 102 away from the substrate 101, and a gate electrode 40 is formed on a surface of the gate dielectric layer 30 away from the base 10; as shown in fig. 3, ion implantation is performed in the epitaxial layer 102 on both sides of the gate dielectric layer 30 and the gate electrode 40 to form the body region 103, the drift region 104, a source contact region 105 and a drain contact region 106, the gate dielectric layer 30 covers a portion of the body region 103 and a portion of the epitaxial layer 102, the gate dielectric layer 30 is not in contact with the source contact region 105, the projections of the gate dielectric layer 30 and the gate electrode 40 in the field plate structure 20 are located in the first through hole 203, the source contact region 105 is located in the body region 103, a surface of the source contact region 105 away from the substrate 101 is flush with a surface of the epitaxial layer 102 away from the substrate 101, the source contact region 105 is different in doping type from the body region 103, the drain contact region 106 is located in the drift region 104, a surface of the drain contact region 106 away from the substrate 101 is flush with a surface of the drift region 104 away from the substrate 101, and the doping type of the drain contact region 106 is the same as the drift region 104. The substrate and the epitaxial layer are provided in a stacked mode, the gate dielectric layer is formed on the part of the surface, far away from the substrate, of the epitaxial layer, the grid electrode is formed on the surface, far away from the substrate, of the gate dielectric layer, and finally the body region, the drift region, the source contact region and the drain contact region are obtained through ion implantation of the epitaxial layer, so that the substrate can be obtained through a simpler process, and the manufacturing process of the LDMOS device is simpler.
In addition, as the body region and the drift region are arranged at intervals, and the doping concentration of the drift region is larger than that of the epitaxial layer, the epitaxial layer with smaller concentration exists between the body region and the drift region, and the doping types of the epitaxial layer and the drift region are different, so that a reverse PN junction is formed between the epitaxial layer and the drift region, and pressure bearing can be carried out through the reverse PN junction, the electric field distribution of the semiconductor device is guaranteed to be good, the breakdown voltage of the semiconductor device is guaranteed to be high, and the performance of the semiconductor device is further guaranteed to be good.
In order to further ensure that the manufacturing process of the LDMOS terminal structure is simpler, according to another embodiment of the present application, forming a gate dielectric layer on a portion of the surface of the epitaxial layer away from the substrate, and forming a gate electrode on a surface of the gate dielectric layer away from the substrate includes: as shown in fig. 1, a preliminary gate dielectric layer 80 and a preliminary gate 90 are formed on a surface of the epitaxial layer 102 remote from the substrate 101; as shown in fig. 2, a portion of the preliminary gate dielectric layer 80 and a portion of the preliminary gate electrode 90 are removed, the remaining preliminary gate dielectric layer 80 forms the gate dielectric layer 30, and the remaining preliminary gate electrode 90 forms the gate electrode 40. By forming the laminated preparation gate dielectric layer and the preparation gate electrode on the surface of the epitaxial layer far away from the substrate and removing part of the preparation gate dielectric layer and part of the preparation gate electrode, the gate dielectric layer and the gate electrode can be obtained through a simpler process, and the manufacturing process of the LDMOS terminal structure is further ensured to be simpler.
According to a further embodiment of the present application, before forming the field plate structure on the side of the epitaxial layer remote from the substrate, the method further comprises: as shown in fig. 4, a preliminary dielectric layer 100 is formed on the exposed surface of the epitaxial layer 102, the surface of the preliminary dielectric layer 100 away from the epitaxial layer 102 is a plane, and the field plate structure 20 is located on the surface of the preliminary dielectric layer 100 away from the substrate 10; as shown in fig. 4 and 5, a portion of the preliminary dielectric layer 100 is removed, and a second via hole 110 and a third via hole 120 are formed, wherein the second via hole 110 and the third via hole 120 expose a portion of the source contact region 105 and a portion of the drain contact region 106, respectively; as shown in fig. 5, a portion of the preliminary dielectric layer 100, a portion of the source contact region 105, a portion of the body region 103, and a portion of the epitaxial layer 102 are removed to form a fourth via 130, the fourth via 130 exposes a portion of the substrate 101, and the remaining preliminary dielectric layer 100 forms a dielectric layer 50; as shown in fig. 6, a metal material is formed in the second via hole 110, the third via hole 120, and the fourth via hole 130, and a source electrode 107, a drain electrode 108, and a first metal layer 60 are formed, respectively, the first metal layer 60 is used to electrically connect the source contact region 105 and the substrate 101, and the field plate structure 20 is in contact with the first metal layer 60. The second via hole and the third via hole are obtained by forming the preliminary dielectric layer on the exposed surface of the epitaxial layer, and then removing part of the preliminary dielectric layer, and the fourth via hole is obtained by removing part of the preliminary dielectric layer, part of the source contact region, part of the body region and part of the epitaxial layer, the second via hole, the third via hole and the fourth via hole expose the source contact region, the drain contact region and the substrate, respectively, and then the source electrode, the drain electrode and the first metal layer are obtained by depositing the metal materials in the second via hole, the third via hole and the fourth via hole, respectively, so that the source contact region can be led out through the source electrode, the drain contact region can be led out through the drain electrode, the source contact region and the substrate can be electrically connected through the first metal layer, and the grounding of the source contact region can be realized, and the device performance can be further ensured.
Specifically, the epitaxial layer is located on a portion of the predetermined surface of the substrate, and the first metal layer is located on another portion of the predetermined surface of the substrate.
According to a specific embodiment of the present application, a field plate structure is formed on a side of the epitaxial layer away from the substrate, including: as shown in fig. 7, a preliminary field plate structure 140 is formed on a surface of the dielectric layer 50 away from the substrate 10; as shown in fig. 8, a portion of the preliminary field plate structure 140 is removed, so that a portion of the dielectric layer 50 is exposed, and the remaining preliminary field plate structure 140 forms the field plate structure 20 and the second metal layer 70 disposed at intervals, and the second metal layer 70 contacts the drain electrode 108. The field plate structure and the second metal layer are formed by forming the preparation field plate structure on the surface of the dielectric layer far away from the substrate and removing part of the preparation field plate structure, and the field plate structure comprises the field plate base and the arc-shaped field plate positioned at one side of the field plate base, and the projection of the arc-shaped field plate in the substrate covers part of the drift region, so that the electric field distribution in the drift region can be optimized through the field plate structure.
In addition, by forming the second metal layer and making the second metal layer contact with the drain electrode, the drain contact region can be led out through the second metal layer and the drain electrode, that is, the drain electrode and the drain contact region can be connected through the second metal layer, so that better performance of the LDMOS device is further ensured.
Specifically, the metal material includes tungsten, but the metal material is not limited to tungsten, and other metal materials such as copper may be selected, and the metal material is not limited thereto.
In the foregoing embodiments of the present invention, the descriptions of the embodiments are emphasized, and for a portion of this disclosure that is not described in detail in this embodiment, reference is made to the related descriptions of other embodiments.
From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:
1) The LDMOS terminal structure comprises a substrate, an epitaxial layer, a body region and a drift region, wherein the substrate comprises a substrate, the epitaxial layer and the substrate are stacked, the body region and the drift region are arranged in the epitaxial layer in a spaced mode, the doping types of the epitaxial layer and the body region are the same, the doping types of the drift region and the epitaxial layer are different, and the doping concentration of the drift region is larger than that of the epitaxial layer; the field plate structure is located on one side of the epitaxial layer far away from the substrate, the field plate structure comprises a field plate base and an arc-shaped field plate located on one side of the field plate base, the field plate base is in contact with the arc-shaped field plate, the field plate structure is provided with a first through hole, the first through hole is formed between the field plate base and the arc-shaped field plate in a surrounding mode, a projection covering part of the arc-shaped field plate in the substrate covers the drift region, a projection covering part of the field plate base in the substrate covers the body region, and a projection of the epitaxial layer between the body region and the drift region in the field plate structure is located in the first through hole. Compared with the problem of poor performance of a device caused by lower breakdown voltage of the device in the prior art, the LDMOS terminal structure of the application comprises the substrate, the epitaxial layer, the body region and the base of the drift region, and further comprises the field plate structure, the field plate structure comprises the field plate body and the arc-shaped field plate, the projection of the arc-shaped field plate in the base covers part of the drift region, so that the electric field distribution in the drift region can be optimized through the field plate structure, and in addition, the projection of the epitaxial layer between the body region and the drift region in the field plate structure is located in the first through hole, namely, the field plate structure enables part of the epitaxial layer to be hollowed out, the field plate structure has small influence on the electric field of the epitaxial layer, the electric field distribution of the LDMOS device is optimized, the breakdown voltage of the device is guaranteed to be higher, and the performance of the semiconductor device is guaranteed to be better.
2) In the method for manufacturing the LDMOS terminal structure, firstly, a substrate is provided, the substrate comprises a substrate, an epitaxial layer, a body region and a drift region, the epitaxial layer is positioned on the surface of the substrate, the body region and the drift region are arranged in the epitaxial layer in a space mode, doping types of the epitaxial layer and the body region are the same, doping types of the drift region and the epitaxial layer are different, and doping concentration of the drift region is larger than that of the epitaxial layer; then, a field plate structure is formed on a side of the epitaxial layer away from the substrate, the field plate structure includes a field plate base and an arc field plate located on a side of the field plate base, the field plate base is in contact with the arc field plate, the field plate structure has a first through hole, the first through hole is located between the field plate base and the arc field plate, a projection of the arc field plate in the substrate covers the drift region, a projection of the field plate base in the substrate covers the body region, and a projection of the epitaxial layer between the body region and the drift region in the field plate structure is located in the first through hole. Compared with the problem of poor performance of a device caused by lower breakdown voltage of the device in the prior art, the manufacturing method of the LDMOS terminal structure of the application comprises the steps of providing the substrate comprising the substrate, the epitaxial layer, the body region and the drift region, forming the field plate structure on one side of the epitaxial layer far away from the substrate, wherein the field plate structure comprises the field plate body and the arc-shaped field plate, and the arc-shaped field plate covers part of the drift region due to the fact that the projection of the arc-shaped field plate in the substrate covers the drift region, so that the electric field distribution in the drift region can be optimized through the field plate structure, and in addition, the projection of the epitaxial layer between the body region and the drift region in the field plate structure is located in the first through hole, namely, the field plate structure enables part of the epitaxial layer to be hollowed out, the electric field effect of the field plate structure on the epitaxial layer is smaller, the electric field distribution of the LDMOS device is optimized, the breakdown voltage of the device is higher, and the semiconductor device is guaranteed to be better in performance.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims (11)

1. An LDMOS termination structure, comprising:
the substrate comprises a substrate, an epitaxial layer, a body region and a drift region, wherein the epitaxial layer is positioned on the surface of the substrate, the body region and the drift region are arranged in the epitaxial layer in a space mode, the doping types of the epitaxial layer and the body region are the same, the doping types of the drift region and the epitaxial layer are different, and the doping concentration of the drift region is larger than that of the epitaxial layer;
the field plate structure is located the epitaxial layer keep away from one side of substrate, just the field plate structure includes field plate portion and is located the arc field plate of field plate portion one side, field plate portion with arc field plate contact sets up, the field plate structure has first through-hole, first through-hole is located field plate portion with between the arc field plate, the projection of arc field plate in the basement covers the part drift region, the projection of field plate portion in the basement covers the part the body region, the body region with between the drift region the projection of epitaxial layer in the field plate structure is located in the first through-hole.
2. The LDMOS terminal structure of claim 1, wherein the substrate further comprises:
a source contact region in the body region, a surface of the source contact region away from the substrate being flush with a surface of the epitaxial layer away from the substrate, the source contact region being of a different doping type than the body region;
the drain contact region is positioned in the drift region, the surface of the drain contact region, which is far away from the substrate, is flush with the surface of the drift region, which is far away from the substrate, and the doping type of the drain contact region is the same as that of the drift region;
a source electrode located on a portion of a surface of the source contact region remote from the substrate;
and a drain electrode located on a portion of the surface of the drain contact region remote from the substrate.
3. The LDMOS terminal structure of claim 2, further comprising:
the gate dielectric layer is positioned on part of the surface of the substrate, covers part of the body region and part of the epitaxial layer, and is not contacted with the source contact region;
the grid electrode is positioned on the surface, far away from the substrate, of the grid dielectric layer, and the projection of the grid electrode in the field plate structure is positioned in the first through hole;
The dielectric layer covers the gate dielectric layer, the grid electrode and the surface of the epitaxial layer, which is far away from the substrate, the surface of the dielectric layer, which is far away from the epitaxial layer, is a plane, the source electrode and the drain electrode penetrate through the dielectric layer, and the field plate structure is positioned on the surface of the dielectric layer, which is far away from the substrate.
4. The LDMOS terminal structure of claim 3, wherein the epitaxial layer is located on a portion of the predetermined surface of the substrate, the LDMOS terminal structure further comprising:
and the first metal layer is positioned on the other part of the preset surface of the substrate, the surface of the first metal layer away from the substrate is flush with the surface of the dielectric layer away from the substrate, the first metal layer is used for electrically connecting the source contact area and the substrate, and the field plate structure is in contact with the first metal layer.
5. The LDMOS terminal structure of claim 3, further comprising:
the second metal layer is positioned on a part of the surface, far away from the substrate, of the dielectric layer, the second metal layer is in contact with the drain electrode, the second metal layer is arranged at intervals with the field plate structure, and the second metal layer is exposed with the field plate structure to enable part of the dielectric layer to be exposed.
6. The LDMOS terminal structure of any one of claims 1 to 5, wherein the doping type of the epitaxial layer is P-type and the doping type of the drift region is N-type.
7. The manufacturing method of the LDMOS terminal structure is characterized by comprising the following steps of:
providing a substrate, wherein the substrate comprises a substrate, an epitaxial layer, a body region and a drift region, the epitaxial layer is positioned on the surface of the substrate, the body region and the drift region are arranged in the epitaxial layer in a space mode, the doping types of the epitaxial layer and the body region are the same, the doping types of the drift region and the epitaxial layer are different, and the doping concentration of the drift region is larger than that of the epitaxial layer;
the field plate structure comprises a field plate body and an arc-shaped field plate positioned on one side of the field plate body, the field plate body is in contact with the arc-shaped field plate, the field plate structure is provided with a first through hole, the first through hole is positioned between the field plate body and the arc-shaped field plate, the projection of the arc-shaped field plate in the substrate covers part of the drift region, the projection of the field plate body in the substrate covers part of the body region, and the projection of the epitaxial layer between the body region and the drift region in the field plate structure is positioned in the first through hole.
8. The method of claim 7, wherein providing a substrate comprises:
providing the substrate and the epitaxial layer which are stacked;
forming a gate dielectric layer on a part of the surface of the epitaxial layer, which is far away from the substrate, and forming a gate on the surface of the gate dielectric layer, which is far away from the base;
and performing ion implantation in the gate dielectric layer and the epitaxial layer at two sides of the gate to form a body region, a drift region, a source contact region and a drain contact region, wherein the gate dielectric layer covers part of the body region and part of the epitaxial layer, the gate dielectric layer is not contacted with the source contact region, the projection of the gate dielectric layer and the gate in the field plate structure is positioned in the first through hole, the source contact region is positioned in the body region, the surface of the source contact region, which is far away from the substrate, is flush with the surface of the epitaxial layer, which is far away from the substrate, the doping type of the source contact region is different from that of the body region, the drain contact region is positioned in the drift region, the surface of the drain contact region, which is far away from the substrate, is not contacted with the surface of the drift region, which is far away from the substrate, and the doping type of the drain contact region is flush with that of the drift region.
9. The method of claim 8, wherein forming a gate dielectric layer on a portion of a surface of the epitaxial layer remote from the substrate and forming a gate electrode on a surface of the gate dielectric layer remote from the base comprises:
forming a laminated preparation gate dielectric layer and a preparation gate on the surface of the epitaxial layer, which is far away from the substrate;
and removing part of the preparation gate dielectric layer and part of the preparation gate, forming the gate dielectric layer by the rest of the preparation gate dielectric layer, and forming the gate by the rest of the preparation gate.
10. The method of claim 8, wherein prior to forming a field plate structure on a side of the epitaxial layer remote from the substrate, the method further comprises:
forming a preparation medium layer on the exposed surface of the epitaxial layer, wherein the surface of the preparation medium layer, which is far away from the epitaxial layer, is a plane, and the field plate structure is positioned on the surface of the preparation medium layer, which is far away from the substrate;
removing part of the preparation medium layer to form a second through hole and a third through hole, wherein the second through hole and the third through hole expose part of the source contact area and part of the drain contact area respectively;
Removing part of the preparation medium layer, part of the source contact region, part of the body region and part of the epitaxial layer to form a fourth through hole, wherein part of the substrate is exposed by the fourth through hole, and the rest of the preparation medium layer forms a medium layer;
and forming metal materials in the second through hole, the third through hole and the fourth through hole, and respectively forming a source electrode, a drain electrode and a first metal layer, wherein the first metal layer is used for electrically connecting the source contact area and the substrate, and the field plate structure is in contact with the first metal layer.
11. The method of claim 10, wherein forming a field plate structure on a side of the epitaxial layer remote from the substrate comprises:
forming a preparation field plate structure on the surface of the dielectric layer far away from the substrate;
and removing part of the preparation field plate structure to expose part of the dielectric layer, wherein the rest of the preparation field plate structure forms the field plate structure and a second metal layer which are arranged at intervals, and the second metal layer is in contact with the drain electrode.
CN202211698844.9A 2022-12-28 2022-12-28 LDMOS terminal structure and manufacturing method thereof Active CN116153979B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211698844.9A CN116153979B (en) 2022-12-28 2022-12-28 LDMOS terminal structure and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211698844.9A CN116153979B (en) 2022-12-28 2022-12-28 LDMOS terminal structure and manufacturing method thereof

Publications (2)

Publication Number Publication Date
CN116153979A true CN116153979A (en) 2023-05-23
CN116153979B CN116153979B (en) 2023-11-03

Family

ID=86338185

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211698844.9A Active CN116153979B (en) 2022-12-28 2022-12-28 LDMOS terminal structure and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN116153979B (en)

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5710455A (en) * 1996-07-29 1998-01-20 Motorola Lateral MOSFET with modified field plates and damage areas
JP2001237423A (en) * 1999-12-17 2001-08-31 Matsushita Electric Ind Co Ltd High breakdown voltage semiconductor device
US20110121389A1 (en) * 2008-07-22 2011-05-26 Nxp B.V. Ldmos having a field plate
CN102244092A (en) * 2011-06-20 2011-11-16 电子科技大学 Junction termination structure of transverse high-pressure power semiconductor device
KR20140112629A (en) * 2013-03-12 2014-09-24 주식회사 동부하이텍 Lateral double diffused metal oxide semiconductor and method for fabricating the same
TWI544578B (en) * 2015-03-13 2016-08-01 旺宏電子股份有限公司 Semiconductor device having metal layer and method of fabricating same
JP2017107942A (en) * 2015-12-08 2017-06-15 株式会社東芝 Semiconductor device
CN108807541A (en) * 2018-05-29 2018-11-13 东南大学 A kind of shallow groove isolation structure horizontal semiconductor device with staggeredly interdigital arrangement
CN114566540A (en) * 2022-02-11 2022-05-31 华虹半导体(无锡)有限公司 LDMOS device and manufacturing method thereof
CN114883410A (en) * 2022-04-22 2022-08-09 上海晶丰明源半导体股份有限公司 mOSFET with enhanced high frequency performance
CN115274849A (en) * 2021-04-29 2022-11-01 苏州华太电子技术股份有限公司 LDMOS device

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5710455A (en) * 1996-07-29 1998-01-20 Motorola Lateral MOSFET with modified field plates and damage areas
JP2001237423A (en) * 1999-12-17 2001-08-31 Matsushita Electric Ind Co Ltd High breakdown voltage semiconductor device
US20110121389A1 (en) * 2008-07-22 2011-05-26 Nxp B.V. Ldmos having a field plate
CN102244092A (en) * 2011-06-20 2011-11-16 电子科技大学 Junction termination structure of transverse high-pressure power semiconductor device
KR20140112629A (en) * 2013-03-12 2014-09-24 주식회사 동부하이텍 Lateral double diffused metal oxide semiconductor and method for fabricating the same
TWI544578B (en) * 2015-03-13 2016-08-01 旺宏電子股份有限公司 Semiconductor device having metal layer and method of fabricating same
JP2017107942A (en) * 2015-12-08 2017-06-15 株式会社東芝 Semiconductor device
CN108807541A (en) * 2018-05-29 2018-11-13 东南大学 A kind of shallow groove isolation structure horizontal semiconductor device with staggeredly interdigital arrangement
CN115274849A (en) * 2021-04-29 2022-11-01 苏州华太电子技术股份有限公司 LDMOS device
CN114566540A (en) * 2022-02-11 2022-05-31 华虹半导体(无锡)有限公司 LDMOS device and manufacturing method thereof
CN114883410A (en) * 2022-04-22 2022-08-09 上海晶丰明源半导体股份有限公司 mOSFET with enhanced high frequency performance

Also Published As

Publication number Publication date
CN116153979B (en) 2023-11-03

Similar Documents

Publication Publication Date Title
CN108682689B (en) Laterally diffused metal oxide semiconductor structure and method of forming the same
KR101840903B1 (en) Insulated gate bipolar transistor
CN108807543B (en) Laterally diffused metal oxide semiconductor device and method of manufacturing the same
JP3979258B2 (en) MIS semiconductor device and manufacturing method thereof
TWI695512B (en) Lateral diffusion metal oxide semiconductor device and its manufacturing method
US11652167B2 (en) Semiconductor device having junction termination structure and method of formation
CN116153979B (en) LDMOS terminal structure and manufacturing method thereof
CN110364568B (en) IGBT device and forming method thereof
CN115547838A (en) Preparation method of metal oxide semiconductor device and device
CN115528115A (en) LDMOS power device and preparation method thereof
US20210193847A1 (en) High voltage diode on soi substrate with trench-modified current path
CN208240687U (en) Transverse diffusion metal oxide semiconductor device
CN113053991A (en) Cell structure of reverse conducting IGBT and reverse conducting IGBT
CN116565022A (en) LDMOS terminal structure and manufacturing method thereof
US9882043B2 (en) Semiconductor device with trench termination structure
TWI714683B (en) Surface-optimised transistor with superlattice structures
CN115498013B (en) Preparation method of power chip termination region, structure of termination region and power chip
CN116779537B (en) Method for manufacturing semiconductor structure and semiconductor structure
KR102119483B1 (en) Power semiconductor device and method of fabricating the same
JPH10335631A (en) Power semiconductor device with field plate and manufacture thereof
CN117981090A (en) Power diode and method for producing a power diode
CN116504837A (en) LDMOS device and manufacturing method thereof
CN102184870B (en) Umos transistor and forming method thereof
CN105097889A (en) Terminal structure of semiconductor element, and manufacturing method thereof
CN114141858A (en) Semiconductor terminal structure with transverse variable doping and preparation method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant