CN116153974A - Cell structure of power device, preparation method of cell structure and power device - Google Patents
Cell structure of power device, preparation method of cell structure and power device Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0804—Emitter regions of bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
Abstract
The invention discloses a power device cell structure, a preparation method thereof and a power device, wherein the power device cell structure comprises the following components: the collector, the collector region of the first conductivity type, the drift region of the second conductivity type, the well region of the first conductivity type, the injection region of the first conductivity type, the first insulating layer and the emitter are sequentially stacked, a contact hole is formed in the first insulating layer, and the emitter is contacted with the injection region through the contact hole; the top of the gate groove structure is contacted with the first insulating layer, the gate groove structure penetrates through the injection region and the well region, and the bottom of the gate groove structure extends to the drift region; at least one side of the gate trench structure is formed with an emitter region of the second conductivity type extending along a top of the gate trench structure toward a bottom of the gate trench structure. The cell structure of the power device can shorten the channel length, reduce the channel resistance and reduce the forward conduction voltage drop.
Description
Technical Field
The invention relates to the technical field of power semiconductor devices, in particular to a cell structure of a power device, a preparation method of the cell structure and the power device.
Background
As a bipolar and fully-controlled semiconductor power device, an IGBT (Insulated Gate Bipolar Transistor) has advantages of low driving power consumption, simple driving circuit, reduced saturation voltage, and the like, and is thus widely used in high-voltage and high-current fields.
However, in the prior cell structure of the IGBT, an emission region is formed by injecting ions into the surface, so that the length of a channel is longer, the resistance of the channel is larger, and the forward conduction voltage drop is reduced.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems existing in the prior art. Therefore, a first object of the present invention is to provide a power device cell structure, which can shorten the channel length, reduce the channel resistance, and reduce the forward conduction voltage drop.
A second object of the present invention is to provide a power device.
The third objective of the present invention is to provide a method for manufacturing a cell structure of a power device.
In order to achieve the above object, a power device cell structure according to an embodiment of a first aspect of the present invention includes: the collector, the collector region of the first conductivity type, the drift region of the second conductivity type, the well region of the first conductivity type, the injection region of the first conductivity type, the first insulating layer and the emitter are sequentially stacked, wherein a contact hole is formed in the first insulating layer, and the emitter is contacted with the injection region through the contact hole; a gate trench structure, wherein a top portion of the gate trench structure is in contact with the first insulating layer, and penetrates through the injection region and the well region, and a bottom portion of the gate trench structure extends to the drift region; at least one side of the gate trench structure is formed with an emitter region of a second conductivity type, the emitter region extending along a top of the gate trench structure to a bottom of the gate trench structure.
According to the cell structure of the power device, which is provided by the embodiment of the invention, a brand new preparation mode of the emitting region is adopted, the emitting region of the second conductivity type is formed on at least one side of the gate groove structure, namely ions are injected along the side wall of the gate groove structure to form the emitting region, the emitting region extends from the top of the gate groove structure to the bottom of the gate groove structure, the emitting region is distributed along the side wall of the gate groove in a slender manner, and the channel length can be shortened to form a short channel, so that the resistance of the channel region can be reduced, the forward conduction voltage drop can be reduced, and the device loss can be reduced. In addition, when a unilateral emitting region is formed on one side of the gate groove structure, the density of the channel region can be reduced, so that the short-circuit current of the power device can be reduced, and the short-circuit capability of the power device can be improved.
In some embodiments of the present invention, the gate trench structures are plural, and the plural gate trench structures are arranged at intervals along a direction parallel to the drift region, and the two sides of each gate trench structure are provided with the emitter regions with equal extension lengths or unequal extension lengths.
In some embodiments of the present invention, the gate trench structures are plural, and the plural gate trench structures are arranged at intervals along a direction parallel to the drift region, and the emission region is disposed at one side of each gate trench structure.
In some embodiments of the present invention, the extension length of the emitter region gradually shortens from the edge of the power element cell structure to the center of the power element cell structure, wherein the extension length is a length of the emitter region extending along the top of the gate trench structure to the bottom of the gate trench structure.
In some embodiments of the present invention, the extension lengths of the emission regions corresponding to the adjacent two gate trench structures are different.
In some embodiments of the invention, the emitter region comprises a first emitter region having a first extension and a second emitter region having a second extension, the first emitter region alternating with the second emitter region, wherein the first extension is greater than the second extension.
In some embodiments of the present invention, the gate trench structure includes: a gate trench penetrating the implant region and the well region and extending to the drift region; the grid electrode is arranged in the grid groove; and the gate oxide layer is arranged between the inner surface of the gate groove and the gate electrode.
In some embodiments of the invention, the power device cell structure further comprises a buffer layer disposed between the collector region and the drift region.
In order to achieve the above object, a power device according to an embodiment of the second aspect of the present invention includes at least one power device cell structure as described in any one of the above.
According to the power device provided by the embodiment of the invention, at least one cell structure of the power device as in any one of the embodiments is adopted, and the channel length can be shortened to form a short channel by arranging the emitting regions of the second conductivity type on one side or two sides of the gate groove structure and distributing the emitting regions along the side walls of the gate groove in an elongated manner, so that the resistance of the channel region can be reduced, the forward conduction voltage drop can be reduced, and the loss of the power device can be reduced. And when a unilateral emitting region is formed on one side of the gate groove structure, the density of the channel region can be reduced, so that the short-circuit current of the power device is reduced, and the short-circuit capacity of the power device is improved. And arranging a plurality of gate groove structures according to a certain rule according to the extension length of the emission region, so that the turn-off speeds of different regions of the power device can be balanced, and the threshold voltages of different cell structures can be adjusted, thereby playing a role in protecting the power device and the chip.
In order to achieve the above object, a method for manufacturing a cell structure of a power device according to an embodiment of a third aspect of the present invention includes: providing a substrate, and preparing a drift region of a second conductivity type on the substrate; performing first conductivity type doping on the drift region to form a well region; etching the well region and the drift region to form a gate groove of a gate groove structure; implanting ions of a second conductivity type along the sidewalls of the gate trench at a desired tilt angle on at least one side of the gate trench adjacent the channel region to form an emitter region extending along the top of the gate trench structure toward the bottom of the gate trench structure; and forming a gate oxide layer on the inner surface of the gate groove and filling a gate material in the gate groove to form the gate groove structure.
According to the preparation method of the cell structure of the power device, ions of the second conductivity type are injected along the side wall of the gate groove at a required inclination angle at least at one side of the gate groove close to the channel region, so that the channel regions with different lengths can be controlled to be formed, further, the short-circuit current of the corresponding region of the power device can be controlled, and the resistance of the channel region can be reduced when the length of the channel region is precisely controlled to form a short channel, so that the forward conduction voltage drop is reduced. In addition, ions of the second conductivity type are injected into one side of the gate groove to form a unilateral emission region, so that the density of the channel region can be reduced, and further, the short-circuit current of the power device can be reduced, and the short-circuit capability of the power device can be improved.
In some embodiments of the present invention, implanting ions of a second conductivity type along the sidewalls of the gate trench at a desired tilt angle on at least one side of the gate trench adjacent to the channel region, comprises: and implanting ions of a second conductivity type at two sides of the gate groove by adopting an inclined ion implantation process at the required inclination angle, wherein the required inclination angle is an included angle formed by the ion implantation direction and the side wall direction of the gate groove, alpha = arctan (H/L) is satisfied, alpha is the required inclination angle, H is the extension length of the emitter region, and L is the width of the gate groove.
In some embodiments of the present invention, implanting ions of a second conductivity type on both sides of the gate trench at the desired tilt angle using a tilt ion implantation process, comprising: and implanting ions of a second conductivity type at one side of the gate trench by adopting the inclined ion implantation process at a first required inclination angle, and implanting ions of a second conductivity type at the other side of the gate trench by adopting the inclined ion implantation process at a second required inclination angle, wherein the first required inclination angle is equal to the second required inclination angle.
In some embodiments of the present invention, implanting ions of a second conductivity type on both sides of the gate trench at the desired tilt angle using a tilt ion implantation process, comprising: implanting ions of a second conductivity type at one side of the gate trench with a first desired tilt angle using the tilted ion implantation process, and implanting ions of a second conductivity type at the other side of the gate trench with a second desired tilt angle using the tilted ion implantation process, wherein the first desired tilt angle is different from the second desired tilt angle.
In some embodiments of the present invention, implanting ions of a second conductivity type along the sidewalls of the gate trench at a desired tilt angle on at least one side of the gate trench adjacent to the channel region, comprises: and implanting ions of a second conductivity type at one side of the gate groove by adopting an inclined ion implantation process at the required inclination angle, wherein the required inclination angle is an included angle formed by the ion implantation direction and the side wall direction of the gate groove, alpha = arctan (H/L) is satisfied, alpha is the required inclination angle, H is the extension length of the emitter region, and L is the width of the gate groove.
According to the preparation method of the cell structure of the power device, ions of the second conductivity type are injected into one side of the gate groove to form a unilateral emission region, so that the density of a channel region can be reduced, the short-circuit current of the power device can be further reduced, and the short-circuit capacity of the power device can be improved.
In some embodiments of the invention, the method of preparing further comprises: and controlling the ion implantation to adopt the required inclination angle to gradually decrease from the edge of the power device cell structure to the center of the power device cell structure.
In some embodiments of the invention, the method of preparing further comprises: ions of the second conductivity type are implanted along sidewalls of the gate trench alternately at a third desired tilt angle and a fourth desired tilt angle such that the differently extended emitter regions are alternately disposed, wherein the third desired tilt angle is greater than the fourth desired tilt angle.
In some embodiments of the invention, the method of preparing further comprises: selectively implanting ions of a first conductivity type into the well region to form an implanted region, depositing a first insulating layer, etching the portion of the first insulating layer which does not cover the gate trench structure and the emitter region to form a contact hole, depositing metal to form an emitter, and contacting the emitter with the implanted region through the contact hole; and forming at least a collector region and a collector electrode doped with the first conductivity type on the back surface of the drift region in sequence.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the invention will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
FIG. 1 is a schematic diagram of a power device cell structure according to one embodiment of the invention;
FIG. 2 is a schematic diagram of a power device cell structure according to another embodiment of the present invention;
FIG. 3 is a schematic diagram of a power device cell structure according to yet another embodiment of the present invention;
FIG. 4 is a schematic diagram of a power device cell structure according to yet another embodiment of the present invention;
FIG. 5 is a schematic diagram of a power device cell structure according to yet another embodiment of the present invention;
FIG. 6 is a block diagram of a power device according to one embodiment of the invention;
FIG. 7 is a flow chart of a method of fabricating a cell structure of a power device according to one embodiment of the invention;
FIG. 8 is a schematic diagram of a cell structure for preparing a power device according to one embodiment of the present invention;
FIG. 9 is a schematic diagram of a cell structure for preparing a power device according to another embodiment of the present invention;
FIG. 10 is a schematic diagram of a cell structure for fabricating a power device according to yet another embodiment of the present invention;
FIG. 11 is a schematic diagram of a cell structure for preparing a power device according to yet another embodiment of the present invention;
FIG. 12 is a schematic diagram of a cell structure for fabricating a power device according to yet another embodiment of the present invention;
FIG. 13 is a schematic diagram of a cell structure for fabricating a power device according to yet another embodiment of the present invention;
FIG. 14 is a schematic diagram of a cell structure for fabricating a power device according to yet another embodiment of the present invention;
FIG. 15 is a schematic diagram of a cell structure for fabricating a power device according to yet another embodiment of the present invention;
fig. 16 is a schematic diagram of a cell structure for preparing a power device according to another embodiment of the present invention.
Reference numerals:
a power device 1000;
a power device cell structure 100;
Detailed Description
For a more complete understanding of the nature and the technical content of the embodiments of the present invention, reference should be made to the following detailed description of embodiments of the invention, taken in conjunction with the accompanying drawings, which are meant to be illustrative only and not limiting of the embodiments of the invention. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may still be practiced without these details. In other instances, well-known structures and devices may be shown simplified in order to simplify the drawing.
A power device cell structure 100 according to an embodiment of the invention is described below with reference to fig. 1-5.
In some embodiments of the present invention, as shown in fig. 1, a schematic diagram of a power device cell structure according to an embodiment of the present invention is shown, where a power device cell structure 100 includes a collector 13, a collector region 12 of a first conductivity type, a drift region 10 of a second conductivity type, a well region 4 of the first conductivity type, an implantation region 6 of the first conductivity type, a first insulating layer 2, an emitter 1, and a gate trench structure N, which are sequentially stacked.
The first conductive type may be P-type conductive, and the second conductive type may be N-type conductive. Alternatively, the first conductivity type is N-type conductivity and the second conductivity type is P-type conductivity.
In some embodiments, the emitter 1 is a front metal layer, the collector 13 is a back metal layer, and a metal component may be plated on the front or back of the power device cell structure 100 by evaporation or sputtering to form the emitter 1 or the collector 13, where the metal component in the emitter 1 may include AlSi or AlSiCu, and the metal component in the collector 13 may include AlTiNiAg or AlTiNNiAg or AlTiNiAu, and the like.
Wherein the well region 4 or the collector region 12 may be doped with boron ions or other ions by implantation, for example, the well region 4 or the collector region 12 may be formed by implantation, driving in or in diffusion, or the like. Specifically, the well region 4 and the collector region 12 are doped with boron (B), and the doping is heavily doped, for example, the doping concentration may be 10 14 -10 16 cm -3 And the impurity concentration is linear or gaussian-like.
And implanting ions of the first conductivity type at the front surface of the well region 4 by a process of selective implantation, diffusion, or driving in to form an implantation region 6. Wherein the implantation region 6 is heavily doped with a doping concentration of 10 16 -10 18 cm -3 The impurity doped in the implanted region 6 is boron (B) and the doping concentration thereof is in a gaussian-like distribution. The injection region 6 forms an ohmic contact with the emitter 1, so that the contact performance of the power device 1000 can be improved and the contact resistance can be reduced.
In other embodiments, the doping impurity of the drift region 10 may be phosphorus (P) or arsenic (As), and the doping is lightly doped, the doping concentration of the drift region 10 being 2×10 13 ㎝ -3 -4×10 14 ㎝ -3 The light doping concentration is linear distribution or Gaussian-like distribution.
The first insulating layer 2 is provided with a contact hole 3, and the emitter 1 is in contact with the implantation region 6 through the contact hole 3. The top of the gate trench structure N is located in the first insulating layer 2 and the gate trench structure N extends through the implant region 6 and the well region 4, the bottom of the gate trench structure N extending to the drift region 10.
Specifically, the first insulating layer 2 covers the gate trench structure N on the upper surface of the first conductivity type epitaxial layer, and the first insulating layer 2 can be used to prevent external impurities from entering the gate trench structure N, so as not to affect the threshold voltage, and the first insulating layer 2 can also isolate the emitter 1, so as to prevent short circuits from affecting the electrical characteristics, wherein the isolation layer material selected for the first insulating layer 2 includes silicon oxide such as silicon dioxide, PSG, USG, BPSG, or a combination of the above materials, and the like.
Wherein in some embodiments the gate trench structure N comprises a gate trench 9, a gate 5 and a gate oxide layer 8, wherein the gate trench 9 extends through the implanted region 6 and the well region 4 and to the drift region 10. Specifically, the shape of the gate groove 9 may be rectangular, trapezoidal, U-shaped, or abnormal, and in the embodiment of the present invention, taking the shape of the gate groove 9 as a U-shaped groove as an example, the gate groove 9 may be formed by using a photoresist to etch silicon and a specific silicon etching solution to etch or dry etch silicon, wherein the depth of the gate groove 9 may be set to 2.5um to 5.5um.
Further, the gate 5 is disposed in the gate trench 9, wherein the gate 5 comprises silicon oxide, and the gate trench 9 may be filled with silicon oxide to form the gate 5. Wherein the gate 5 is heavily doped with a doping concentration of 10 21 cm -3 A gate oxide layer 8 is disposed between the inner surface of the gate trench 9 and the gate 5, i.e., the gate 5 is disposed inside the gate oxide layer 8, it is understood that the gate oxide layer 8 is an oxide layer inside the gate trench 9, the gate oxide layer 8 may be formed inside the gate trench 9 by an oxidation or deposition method, and the filled gate 5 is adapted to the shape of the gate trench 9.
In other embodiments, at least one side of the gate trench structure N is formed with an emitter region 7 of the second conductivity type, the emitter region 7 extending along the top of the gate trench structure N toward the bottom of the gate trench structure N.
Specifically, an inclined ion implantation process may be used to implant ions of the second conductivity type along the sidewalls of the gate trench 9 at a desired inclination angle at one or both sides of the gate trench 9 adjacent to the channel region to form the emitter region 7. The angle formed by the implantation direction of the inclined ion implantation angle and the sidewall direction of the gate trench 9 is denoted by α, and taking the width of the gate trench 9 as L and the height of the emitter 7 as H as an example, the inclined ion implantation angle α=arctan (H/L), where the height H of the emitter 7 is determined by the width of the protection layer defined by photolithography. And the emitter region 7 is heavily doped,a doping concentration of 10 16 -10 18 cm -3 The doping impurities of the emitter region 7 may be phosphorus (P) or arsenic (As), and the doping concentration of the emitter region 7 is linearly distributed or gaussian-like distributed.
According to the cell structure 10 of the power device provided by the embodiment of the invention, based on the structures of the collector 13, the collector 12, the drift region 10, the well region 4, the injection region 6, the first insulation 2, the emitter 1 and the gate trench structure N, a brand new preparation mode of the emitter 7 is adopted, the emitter 7 of the second conductivity type is formed on at least one side of the gate trench structure N, namely, ions are injected along the side wall of the gate trench structure N to form the emitter 7, the emitter 7 extends from the top of the gate trench structure N to the bottom of the gate trench structure N, the emitter 7 is distributed along the side wall of the gate trench 9 in an elongated manner, and the channel length can be shortened to form a short channel, so that the resistance of the channel region can be reduced, the forward conduction voltage drop can be reduced, and the device loss can be reduced. In addition, when the single-sided emitter region 7 is formed on one side of the gate trench structure N, the density of the channel region can be reduced, so that the short-circuit current of the power device 1000 can be reduced and the short-circuit capability of the power device 1000 can be improved.
In some embodiments of the present invention, as shown in fig. 2, a schematic diagram of a power device cell structure according to another embodiment of the present invention is shown, where the power device cell structure 100 further includes a buffer layer 11, and the buffer layer 11 is disposed between the collector region 12 and the drift region 10.
Specifically, H ions or other ions may be implanted between the collector region 12 and the drift region 10 by implantation, driving, diffusion, or the like to form the buffer layer 11 under the drift region 10. The doping impurity of the buffer layer 11 may be phosphorus (P) or other ions, and the doping is light doping with a doping concentration of 2×10 14 ㎝ -3 —5×10 15 ㎝ -3 The doping concentration of the buffer layer 11 is linear or gaussian-like.
In some embodiments of the present invention, as shown in fig. 2, the gate trench structures N are plural and are arranged at intervals in a direction parallel to the drift region 10, wherein a distance between each gate trench structure N and an adjacent gate trench structure N may be set to 1um to 10um. The two sides of each gate groove structure N are provided with emitting areas 7 with equal extension lengths or unequal extension lengths, wherein the extension lengths are the lengths of the emitting areas 7 extending along the top of the gate groove structure N to the bottom of the gate groove structure N. The extension length of the emitter region 7 may be set as desired, for example, the extension length of the emitter region 7 may be formed by defining a protective layer by photolithography, and thus a short channel may be formed by precisely controlling the extension length of the emitter region 7.
In some embodiments of the present invention, as shown in fig. 3, a schematic diagram of a power device cell structure according to another embodiment of the present invention is shown, where a plurality of gate trench structures N are provided, and the plurality of gate trench structures N are arranged at intervals along a direction parallel to the drift region 10, and an emitter region 7 is disposed on one side of each gate trench structure N.
Specifically, by adopting the inclined ion implantation process with a certain angle, the emitter region 7 is formed on one side of the gate groove 9 through single-side implantation, and n+ is implanted on one side of the gate groove structure N to form a single-side channel, so that the channel density can be greatly reduced under the condition of the same cell structure 100 area of the power device, the short-circuit current of the power device 1000 can be reduced, the short-circuit current bearing tolerance of the power device 1000 can be improved, and the impact resistance of the power device 1000 can be enhanced.
In some embodiments of the present invention, the extension length of the emitter region 7 gradually shortens from the edge of the power device cell structure 100 to the center of the power device cell structure 100, wherein the extension length is the length of the emitter region 7 extending along the top of the gate trench structure N toward the bottom of the gate trench structure N. Fig. 4 is a schematic diagram of a cell structure of a power device according to another embodiment of the invention.
In the power device cell structure 100 shown in fig. 4, two sides of each gate groove structure N are formed with emitter regions 7 with equal extension lengths, and the extension lengths of the emitter regions 7 at two sides of each gate groove structure N are gradually shortened from the edge of the power device cell structure 100 to the center of the power device cell structure 100, for example, the extension length of the emitter regions 7 is the channel length. Specifically, the channel length near the edge of the power device cell structure 100 is longer, and the channel length gradually near the center of the power device cell structure 100 is gradually shorter. The channel length is gradually shortened from the edge of the power device cell structure 100 to the center of the power device cell structure 100, so that the turn-off speed of the edge and the center of the power device 1000 can be balanced, the short-circuit current of the center cell of the power device cell structure 100 is reduced, the power device 100 has stronger current bearing capacity when turned off, the turn-off capacity of the power device 1000 is finally increased, and the service life of the power device 1000 is prolonged.
In other embodiments of the present invention, the extension lengths of the emitter regions 7 corresponding to two adjacent gate trench structures N are not equal.
Specifically, the emitter region 7 includes a first emitter region having a first extension length and a second emitter region having a second extension length, the first emitter region being alternately arranged with the second emitter region at intervals, wherein the first extension length is greater than the second extension length.
Fig. 5 is a schematic diagram of a cell structure of a power device according to another embodiment of the invention. Taking the example that the first emitter region shown in fig. 5 includes emitter regions 7 having a longer extension length disposed at both sides of one gate trench structure N, the second emitter region includes emitter regions 7 having a shorter extension length disposed at both sides of one gate trench structure N. It is understood that the first emission regions and the second emission regions are alternately arranged, that is, the corresponding plurality of gate groove structures N may be arranged in such a manner that the channels are long and short.
Further, when the plurality of gate trench structures N are arranged in accordance with the extension lengths of the emitter regions 7, not limited to the one-long-short alternating arrangement illustrated in fig. 5, it is also possible to include the first emitter region including the emitter regions 7 having a longer extension length disposed on both sides of the two gate trench structures N and include the second emitter region including the emitter regions 7 having a shorter extension length disposed on both sides of one gate trench structure N. Alternatively, it is also possible to provide the first emitter region with emitter regions 7 having a longer extension length disposed on both sides of the three gate trench structures N, and to provide the second emitter region with emitter regions 7 having a shorter extension length disposed on both sides of the two gate trench structures N. That is, the plurality of gate groove structures N may be arranged in any manner such as two long and one short or three long and two short, and the first emission region and the second emission region may be distributed at the edge of the power device cell structure 100 or in the center of the power device cell structure 100, or may be distributed throughout the power device cell structure 100.
According to the power device cell structure 100 of the embodiment of the invention, the emitting areas 7 are arranged in an alternate arrangement according to the different extension lengths of the emitting areas 7, so that the threshold voltages of different power device cell structures 100 can be divided into high and low values, and the power device 1000 can be always turned on and off in a certain gradient, thereby playing a role in protecting the power device 1000 and a chip.
In some embodiments of the present invention, as shown in fig. 6, a block diagram of a power device according to an embodiment of the present invention is shown, wherein a power device 1000 includes at least one power device cell structure 100 as in any of the above.
One or more power device cell structures 100 of the above embodiments are provided in the power device 1000, and the emitter 7 in the power device cell structure 100 is provided on one side or two sides of the gate trench structure N and extends along the top of the gate trench structure N to the bottom of the gate trench structure N, so that the channel density in the power device cell structure 100 can be adaptively adjusted, and further the short-circuit current of the power device 1000 can be reduced, the short-circuit current bearing capacity of the power device 1000 can be improved, and the impact resistance of the power device 1000 can be enhanced. The extension length of the emission area 7 is set to be gradually shortened from the edge of the power device cell structure 100 to the center of the power device cell structure 100, so that the turn-off speed of the edge and the center of the power device 1000 can be balanced, the short-circuit current in the center of the power device cell structure 100 is reduced, the power device cell structure has stronger current bearing capacity when turned off, the turn-off capacity of the power device 1000 is finally increased, and the service life of the power device 1000 is prolonged. And, the emitter region 7 is set to include a first emitter region and a second emitter region with different extension lengths, and the first emitter region and the second emitter region are alternately set at intervals, so that the threshold voltages of the cell structures 100 of different power devices can be divided into high and low values, and the power devices 1000 can be always turned on and off with a certain gradient, thereby playing a role in protecting the power devices 1000 and chips.
According to the power device 1000 provided in the embodiment of the present invention, at least one of the power device cell structures 100 as in any one of the above embodiments is adopted, and by arranging the emitter regions 7 of the second conductivity type on one side or both sides of the gate trench structure N and distributing the emitter regions along the side walls of the gate trench 9 in an elongated manner, the channel length can be shortened to form a short channel, so that the resistance of the channel region can be reduced, the forward conduction voltage drop can be reduced, and the loss of the power device 1000 can be reduced. When the unilateral emitting region 7 is formed on one side of the gate trench structure N, the density of the channel region can be reduced, so that the short-circuit current of the power device 1000 is reduced and the short-circuit capability of the power device 1000 is improved. And, according to the extension length of the emitter region 7, the gate groove structures N are arranged according to a certain rule, so that the turn-off speeds of different areas of the power device 1000 can be balanced, and the threshold voltages of different power device cell structures 100 can be adjusted, thereby playing a role in protecting the power device 1000 and the chip.
In other embodiments of the present invention, a method for manufacturing a cell structure of a power device according to an embodiment of the present invention may be described with reference to fig. 7 to 16, as shown in fig. 7, which is a flowchart of a method for manufacturing a cell structure of a power device according to an embodiment of the present invention, where the method for manufacturing a cell structure of a power device includes steps S1 to S7, specifically as follows.
S1, providing a substrate, and preparing a drift region of a second conductivity type on the substrate.
Specifically, as shown in fig. 8, a schematic diagram of a cell structure of a power device is prepared according to an embodiment of the present invention, where a second conductive type substrate may be an N-monocrystalline silicon substrate, and the second conductive type substrate is cleaned and dried to serve as a drift region 10.
S2, doping of the first conductivity type is conducted on the drift region to form a well region.
As shown in fig. 8, the well region 4 may be formed by selectively implanting, diffusing or driving ions of the first conductivity type into the front surface of the power device cell structure 100, i.e., the drift region 10.
And S3, etching is conducted on the well region and the drift region to form a gate groove of the gate groove structure.
In an embodiment, as shown in fig. 9, a schematic diagram of a cell structure of a power device is prepared according to another embodiment of the present invention, where a protective oxide layer is deposited on a substrate of a second conductivity type, and a gate trench structure N is etched by photolithography to define a gate trench 9, where the gate trench structure N penetrates the well region 4, and the bottom of the gate trench structure N extends to the drift region 10.
And S4, implanting ions of a second conductivity type along the side wall of the gate groove at a required inclination angle at least on one side of the gate groove close to the channel region so as to form an emission region extending from the top of the gate groove structure to the bottom of the gate groove structure.
Specifically, step S4 may be described in conjunction with fig. 10, where fig. 10 is a schematic diagram of a cell structure of a power device according to another embodiment of the present invention, and a tilted ion implantation process may be used to implant ions of the second conductivity type and/or ions of the first conductivity type into both sides or one side of the gate trench 9 near the channel region along the sidewalls according to a desired tilt angle. The formed emitter region 7 can be distributed along the side wall of the gate groove 9 in a slender manner by adopting the inclined ion implantation process, so that the channel length can be shortened to form a short channel, and the inclination angle required by the resistance ion implantation of the channel region, the dosage, the energy and the like of the ion implantation can be reduced, and the adjustment can be carried out according to the width of the gate groove 9 and the extension length of the emitter region 7.
In some embodiments, ions of the second conductivity type may be implanted at both sides of the gate trench 9 at a desired tilt angle using a tilt ion implantation process. The required inclination angle is an included angle formed by the ion implantation direction and the side wall direction of the gate groove, and meets the requirement of alpha=arctan (H/L), wherein alpha is the required inclination angle, H is the extension length of the emission region, and L is the width of the gate groove. Further, the distribution state of the emitter regions 7 as shown in fig. 2 is formed, ions are injected at both sides of the gate trench 9 according to a desired inclination angle, the formed emitter regions 7 can be distributed to be elongated along the sidewalls at both sides of the gate trench 9, and the channel length can be shortened to form a short channel, so that the resistance of the channel region can be reduced.
When ion implantation is performed on both sides of the gate trench 9, the conductivity types of the implanted ions on both sides may be set to be the same or different, and the inclination angles required when ion implantation is performed on both sides may be set to be the same or different. For example, ions of the second conductivity type may be implanted at one side of the gate trench with a first desired tilt angle α1 using a tilted ion implantation process, and ions of the second conductivity type may be implanted at the other side of the gate trench with a second desired tilt angle α2 using a tilted ion implantation process, wherein the first desired tilt angle α1 is equal to the second desired tilt angle α2. Alternatively, the ion of the second conductivity type may be implanted at one side of the gate trench with a first desired tilt angle α1 by a tilted ion implantation process, and the ion of the second conductivity type may be implanted at the other side of the gate trench with a second desired tilt angle α2 by a tilted ion implantation process, wherein the first desired tilt angle α1 is different from the second desired tilt angle α2.
In other embodiments, the second conductivity type ions may be implanted at the side of the gate trench 9 by using a tilted ion implantation process at the desired tilt angle, where the desired tilt angle is an angle formed by the ion implantation direction and the sidewall direction of the gate trench, α=arctan (H/L), where α is the desired tilt angle, H is the extension length of the emitter region, and L is the width of the gate trench. Further, the distribution of the emitter regions 7 shown in fig. 3 is formed, and the emitter regions 7 formed by single-side ion implantation are formed at one side of the gate trench 9, so that the density of the channel region can be controlled, and the short-circuit current of the power device 1000 can be reduced and the short-circuit capability of the power device 1000 can be improved.
In other embodiments, the desired tilt angle used for controlling the ion implantation may be gradually reduced from the edge of the power device cell structure 100 to the center of the power device cell structure 100. The distribution state of the emitting areas 7 shown in fig. 4 is formed, the extension length of the emitting areas 7 is set to be gradually shortened from the edge of the power device cell structure 100 to the center of the power device cell structure 100, the turn-off speed of the edge and the center of the power device 1000 can be balanced, the short circuit current in the center of the power device cell structure 100 is reduced, the power device cell structure 100 has stronger current bearing capacity when turned off, the turn-off capacity of the power device 1000 is finally increased, and the service life of the power device 1000 is prolonged.
Ions of the second conductivity type may also be implanted along the sidewalls of the gate trench 9 alternately at a third desired tilt angle α3 and a fourth desired tilt angle α4 such that the differently extended emitter regions 7 are alternately disposed, wherein the third desired tilt angle α3 is greater than the fourth desired tilt angle α4. For example, in the distribution state of the emitter regions 7 shown in fig. 5, by alternately arranging the emitter regions 7 with different extension lengths, the threshold voltages of the cell structures 100 of different power devices can be divided into high and low, so that the power devices 1000 are always turned on and off with a certain gradient, and the function of protecting the power devices 1000 and chips can be achieved.
In addition, when ions are injected into the gate groove 9 near two sides or one side of the channel region along the side wall at a required inclination angle, the high temperature can enable the impurities in the emitter region 7 to diffuse so as to obtain proper concentration, depth and width of the emitter region 7, after the ions are activated, the slender distribution of the emitter region 7 along the side wall of the gate groove 9 can be realized, and a short channel is formed through precise control of the extension length of the emitter region 7, so that electrons diffuse downwards rapidly through the short channel, the resistance of the channel region is further reduced, and finally the saturation voltage drop and the conduction voltage drop of the power device 1000 are reduced. And S5, forming a gate oxide layer on the inner surface of the gate groove and filling a gate material in the gate groove to form a gate groove structure.
Specifically, as shown in fig. 11, a schematic diagram of a cell structure for manufacturing a power device according to still another embodiment of the present invention is shown, wherein a gate oxide layer is grown or deposited on the inner wall surface of the gate trench 9 as the gate oxide layer 8. The gate material may comprise silicon oxide, for example, by deposition of polysilicon and etching of polysilicon in the gate oxide layer 8, or by filling polysilicon in the gate trench 9 by CMP or the like to form the gate 5.
In some embodiments of the present invention, as shown in fig. 7, the method for preparing a cell structure of a power device further specifically includes step S6 and step S7.
S6, selectively implanting ions of a first conductivity type into the well region to form an implanted region, depositing a first insulating layer, etching the part of the first insulating layer which is not covered by the gate groove structure and the emitting region to form a contact hole, depositing metal to form an emitting electrode, and enabling the emitting electrode to be in contact with the implanted region through the contact hole.
Step S6 of the present embodiment may be described with reference to fig. 12 to 14, and fig. 12 is a schematic diagram of a cell structure of a power device according to another embodiment of the present invention; FIG. 13 is a schematic diagram of a cell structure for fabricating a power device according to yet another embodiment of the present invention; fig. 14 is a schematic diagram of a cell structure for preparing a power device according to another embodiment of the present invention.
Specifically, as shown in fig. 12, a mask may be used, and ions of the first conductivity type may be implanted in the front surface of the well region 4 by a process of selective implantation, diffusion, or driving in to form the implantation region 6. As shown in fig. 13, a first insulating layer 2 is deposited on top of the gate trench structure N, and high-temperature reflow is performed on the first insulating layer 2, thereby achieving isolation of the gate trench structure N. The first insulating layer 2 may also be selectively etched, for example, by performing an etching process on a portion of the first insulating layer 2 not covering the gate trench structure N and the emitter region 7 to form the contact hole 3. Further, as shown in fig. 14, metal is deposited on the front surfaces of the first insulating layer 2 and the contact hole 3, thereby forming a front metal electrode, that is, an emitter 1, and the emitter 1 is isolated by the first insulating layer 2 from contact with the gate trench structure N, and the emitter 1 is in contact with the emitter region 7 and also in contact with the injection region 6 through the contact hole 3. Further, a passivation layer (not shown) may be deposited to protect the power device 1000 when metal is deposited on the front side.
And S7, forming at least a collector region and a collector electrode doped with the first conductivity type on the back surface of the drift region in sequence.
Step S6 of the present embodiment may be described with reference to fig. 15, 16 and 2, where fig. 15 is a schematic diagram of a cell structure of a power device according to another embodiment of the present invention; fig. 16 is a schematic diagram of a cell structure for preparing a power device according to another embodiment of the present invention.
Specifically, as shown in fig. 15, the substrate of the second conductivity type is chemically or physically thinned, and boron ions or other ions are implanted into the rear surface of the drift region 10, and the implanted ions are activated to form the collector region 12 on the rear surface of the drift region 10. For example, as shown in fig. 16, the buffer layer 11 may also be formed under the drift region 10 by implanting H ions or other ions between the collector region 12 and the drift region 10. Finally, the collector 13 may be formed on the back surface of the collector region 12 by evaporation or sputtering, so as to serve as a back metal electrode, and finally form the complete power device cell structure 100 as shown in fig. 2.
According to the preparation method of the cell structure of the power device, ions of the second conductivity type are injected along the side wall of the gate groove 9 at a required inclination angle at least at one side of the gate groove 9 close to the channel region, so that the channel regions with different lengths can be controlled to be formed, further, the short-circuit current of the corresponding region of the power device 1000 can be controlled, and the resistance of the channel region can be reduced when the short channel is formed by precisely controlling the length of the channel region, so that the forward conduction voltage drop is reduced. In addition, when ions of the second conductivity type are implanted into one side of the gate trench 9 to form the single-sided emitter region 7, the density of the channel region can be reduced, and thus the short-circuit current of the power device 1000 can be reduced and the short-circuit capability of the power device 1000 can be improved.
Other configurations and operations of the power device cell structure 100 and the power device 1000 according to embodiments of the invention are known to those of ordinary skill in the art and will not be described in detail herein.
In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples.
While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the invention, the scope of which is defined by the claims and their equivalents.
Claims (17)
1. A power device cell structure, comprising:
the collector, the collector region of the first conductivity type, the drift region of the second conductivity type, the well region of the first conductivity type, the injection region of the first conductivity type, the first insulating layer and the emitter are sequentially stacked, wherein a contact hole is formed in the first insulating layer, and the emitter is contacted with the injection region through the contact hole;
The top of the gate groove structure is in contact with the first insulating layer, the gate groove structure penetrates through the injection region and the well region, and the bottom of the gate groove structure extends to the drift region;
at least one side of the gate trench structure is formed with an emitter region of a second conductivity type, the emitter region extending along a top of the gate trench structure to a bottom of the gate trench structure.
2. The power device cell structure according to claim 1, wherein the gate groove structures are a plurality of, the gate groove structures are arranged at intervals along a direction parallel to the drift region, and the emitting regions with equal extension lengths or unequal extension lengths are arranged on two sides of each gate groove structure.
3. The power device cell structure according to claim 1, wherein the gate groove structures are a plurality of, the gate groove structures are arranged at intervals along a direction parallel to the drift region, and the emission region is arranged on one side of each gate groove structure.
4. A power device cell structure according to claim 2 or 3, wherein the extension of the emitter region is progressively shorter from the edge of the power device cell structure to the centre of the power device cell structure, wherein the extension is the length of the emitter region extending along the top of the gate trench structure towards the bottom of the gate trench structure.
5. A power device cell structure according to claim 2 or 3, wherein the extension lengths of the corresponding emitter regions of two adjacent gate trench structures are different.
6. The power device cell structure of claim 5 wherein the emitter region comprises a first emitter region having a first extension and a second emitter region having a second extension, the first emitter region alternating with the second emitter region, wherein the first extension is greater than the second extension.
7. The power device cell structure of claim 1, wherein the gate trench structure comprises:
a gate trench penetrating the implant region and the well region and extending to the drift region;
the grid electrode is arranged in the grid groove;
and the gate oxide layer is arranged between the inner surface of the gate groove and the gate electrode.
8. The power device cell structure of claim 1, further comprising a buffer layer disposed between the collector region and the drift region.
9. A power device comprising at least one power device cell structure according to any of claims 1-8.
10. The preparation method of the cell structure of the power device is characterized by comprising the following steps:
providing a substrate, and preparing a drift region of a second conductivity type on the substrate;
performing first conductivity type doping on the drift region to form a well region;
etching the well region and the drift region to form a gate groove of a gate groove structure;
implanting ions of a second conductivity type along the sidewalls of the gate trench at a desired tilt angle on at least one side of the gate trench adjacent the channel region to form an emitter region extending along the top of the gate trench structure toward the bottom of the gate trench structure;
and forming a gate oxide layer on the inner surface of the gate groove and filling a gate material in the gate groove to form the gate groove structure.
11. The method of claim 10, wherein implanting ions of the second conductivity type along the sidewalls of the gate trench at a desired tilt angle on at least one side of the gate trench adjacent to the channel region comprises:
and implanting ions of a second conductivity type at two sides of the gate groove by adopting an inclined ion implantation process at the required inclination angle, wherein the required inclination angle is an included angle formed by the ion implantation direction and the side wall direction of the gate groove, alpha = arctan (H/L) is satisfied, alpha is the required inclination angle, H is the extension length of the emitter region, and L is the width of the gate groove.
12. The method of claim 11, wherein implanting ions of the second conductivity type at both sides of the gate trench at the desired tilt angle using a tilt ion implantation process comprises:
and implanting ions of a second conductivity type at one side of the gate trench by adopting the inclined ion implantation process at a first required inclination angle, and implanting ions of a second conductivity type at the other side of the gate trench by adopting the inclined ion implantation process at a second required inclination angle, wherein the first required inclination angle is equal to the second required inclination angle.
13. The method of claim 11, wherein implanting ions of the second conductivity type at both sides of the gate trench at the desired tilt angle using a tilt ion implantation process comprises:
implanting ions of a second conductivity type at one side of the gate trench with a first desired tilt angle using the tilted ion implantation process, and implanting ions of a second conductivity type at the other side of the gate trench with a second desired tilt angle using the tilted ion implantation process, wherein the first desired tilt angle is different from the second desired tilt angle.
14. The method of claim 10, wherein implanting ions of the second conductivity type along the sidewalls of the gate trench at a desired tilt angle on at least one side of the gate trench adjacent to the channel region comprises:
and implanting ions of a second conductivity type at one side of the gate groove by adopting an inclined ion implantation process at the required inclination angle, wherein the required inclination angle is an included angle formed by the ion implantation direction and the side wall direction of the gate groove, alpha = arctan (H/L) is satisfied, alpha is the required inclination angle, H is the extension length of the emitter region, and L is the width of the gate groove.
15. The method for manufacturing a cell structure of a power device according to claim 12 or 14, further comprising:
and controlling the ion implantation to adopt the required inclination angle to gradually decrease from the edge of the power device cell structure to the center of the power device cell structure.
16. The method for manufacturing a cell structure of a power device according to claim 12 or 14, further comprising:
ions of the second conductivity type are implanted along sidewalls of the gate trench alternately at a third desired tilt angle and a fourth desired tilt angle such that the differently extended emitter regions are alternately disposed, wherein the third desired tilt angle is greater than the fourth desired tilt angle.
17. The method for manufacturing a cell structure of a power device according to claim 10, further comprising:
selectively implanting ions of a first conductivity type into the well region to form an implanted region, depositing a first insulating layer, etching the portion of the first insulating layer which does not cover the gate trench structure and the emitter region to form a contact hole, depositing metal to form an emitter, and contacting the emitter with the implanted region through the contact hole;
and forming a collector region and a collector electrode of the first conductivity type at least in sequence on the back surface of the drift region.
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