CN116153906A - Semiconductor structure, preparation method thereof and electronic equipment - Google Patents
Semiconductor structure, preparation method thereof and electronic equipment Download PDFInfo
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- CN116153906A CN116153906A CN202310321243.4A CN202310321243A CN116153906A CN 116153906 A CN116153906 A CN 116153906A CN 202310321243 A CN202310321243 A CN 202310321243A CN 116153906 A CN116153906 A CN 116153906A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The embodiment of the invention discloses a semiconductor structure, a preparation method thereof and electronic equipment. The electronic device includes: a substrate; a hard mask plate formed on the substrate; the through hole penetrates through the hard mask plate and extends to the substrate, a first conductor material is filled in the through hole, the first conductor material is etched back to a set depth to form an opening of the through hole, an isolation layer is formed at the opening of the through hole and covers the edge of the first conductor material, and the first conductor material is exposed in the middle of the isolation layer; and a second conductor material filled in the middle of the isolation layer, and a blocking adhesion layer is arranged between the first conductor material and the second conductor material.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a semiconductor structure, a method for manufacturing the semiconductor structure, and an electronic device.
Background
In the related art, as shown in fig. 1, a semiconductor structure includes a substrate 101 and a hard mask 102. After the etching process is completed, the silicon dioxide film layer of the hard mask plate 102 forms a through hole 103, and the opening 1031 of the through hole 103 forms a defect of an inverted trapezoid structure 1031a, so that the opening 1031 becomes larger. The via 103 is filled with a metal material (e.g., the first conductor material 106). The defect of the inverted trapezoid structure 1031a may cause the metal filling material 1091 of the subsequent through silicon via to invade the forbidden zone designed with the back-end metal wire, i.e. the metal filling material of the wiring layer is connected with the metal material, resulting in serious problems such as short circuit.
Therefore, a new technical solution is needed to solve the above technical problems.
Disclosure of Invention
An object of the present invention is to provide a new technical solution for a semiconductor structure, so as to solve the problem of short circuit caused by connection of a metal filling material of a wiring layer and a metal material in a hard mask plate in the prior art.
According to a first aspect of the present invention, a semiconductor structure is provided. The semiconductor structure includes: a substrate;
a hard mask plate formed on the substrate;
the through hole penetrates through the hard mask plate and extends to the substrate, a first conductor material is filled in the through hole, the first conductor material is etched back to a set depth to form an opening of the through hole, an isolation layer is formed at the opening of the through hole and covers the edge of the first conductor material, and the first conductor material is exposed in the middle of the isolation layer; and
and the second conductor material is filled in the middle of the isolation layer, and a blocking adhesion layer is arranged between the first conductor material and the second conductor material.
Preferably, the isolation layer is made of at least one of silicon oxycarbide, silicon oxyfluoride and organic polymer.
Preferably, the isolating layer is annular, and the outer diameter of the isolating layer gradually increases from a side close to the first conductor material to a side far away from the first conductor material.
Preferably, the thickness of the isolation layer at the highest point is 0.5 μm to 10 μm, and the height of the isolation layer is 1 μm to 3 μm.
Preferably, the hard mask plate comprises silicon dioxide layers and silicon nitride layers which are alternately arranged along the thickness direction, wherein the silicon nitride layers are etching stop layers.
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor structure, comprising:
providing a substrate;
depositing a hard mask plate on the substrate;
forming a through hole on the hard mask plate, wherein the through hole extends to the substrate;
filling a first conductor material in the through hole;
removing the first conductor material at the opening of the through hole by adopting a corrosion back etching process;
forming an isolation layer at the opening of the through hole, wherein the isolation layer covers the edge of the first conductor material, and the first conductor material is exposed to the middle part of the isolation layer;
and forming a blocking adhesion layer and a second conductor material on the hard mask plate, wherein the second conductor material is filled in the middle of the isolation layer, and the blocking adhesion layer is arranged between the first conductor material and the second conductor material.
Preferably, an isolation layer is formed at the opening of the cavity, the isolation layer covers the edge of the first conductor material, the first conductor material is exposed at the middle part of the isolation layer, and the isolation layer comprises:
depositing an isolating film layer on the hard mask plate and at the opening of the cavity;
and removing the isolation film layer on the hard mask plate to form the isolation layer at the opening of the cavity, wherein the first conductor material is exposed at the middle part of the isolation layer.
Preferably, the isolating film layer is deposited by adopting a chemical vapor deposition method;
and removing the isolation film layer by adopting an anisotropic dry etching method.
According to a third aspect of the present invention, an electronic device is provided. The electronic device comprising a semiconductor structure as claimed in any one of the preceding claims.
Preferably, the semiconductor structure is located between the first element and the second element, the first element is connected with the second conductor material, the first conductor material is connected with the second element at one end of the through hole, which is far away from the second conductor material, and the first element is conducted with the second element through the first conductor material and the second conductor material.
One technical effect of the present invention is that an isolation layer is formed at an edge position of the first conductor material near the opening of the via hole. The isolation layer effectively reduces the exposed area of the first conductor material, and can effectively prevent the first conductor material from contacting with the second conductor material in the wiring layer, so that the risk of short circuit of the semiconductor structure is reduced.
In addition, the isolation layer can effectively reduce the distance between the first conductor material and the second conductor material, and the mode can effectively reduce the whole occupied area of the conductor circuit in the wiring layer.
Other features of the present invention and its advantages will become apparent from the following detailed description of exemplary embodiments of the invention, which proceeds with reference to the accompanying drawings.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a prior art semiconductor structure.
Fig. 2-7 are schematic diagrams of various stages of a method of fabricating a semiconductor structure according to embodiments of the present invention.
Reference numerals illustrate:
101. a substrate; 102. a hard mask plate; 1021. a silicon dioxide layer; 1022. a silicon nitride layer; 103. a through hole; 1031. an opening; 1031a, inverted trapezoid structure; 104. an insulating layer; 105. a first barrier adhesion layer; 106. a first conductor material; 107. an isolation film layer; 1071. an isolation layer; 108. a second barrier adhesion layer; 109. a second conductor material; 110. an interlayer dielectric layer.
Detailed Description
Hereinafter, embodiments of the present invention will be described in detail. In order to avoid unnecessary detail, well-known structures or functions will not be described in detail in the following embodiments.
Approximating language, as used in the following examples, may be applied to create a quantitative representation that could permissibly vary without resulting in a change in the basic function. Accordingly, a numerical value modified by a language such as "about", "left and right", etc. is not limited to the exact numerical value itself. In some embodiments, "about" means that the values that it is permitted to correct vary within plus or minus ten percent (10%), for example, "about 100" means any value between 90 and 110. Further, in the expression "about a first value to a second value", both the first and second values are corrected at about the same time. In some cases, the approximating language may be related to the precision of a measuring instrument.
Unless defined otherwise, technical and scientific terms used in the following examples have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.
In one embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure includes:
a substrate 101;
a hard mask 102, the hard mask 102 being formed on the substrate 101;
a through hole 103 penetrating through the hard mask plate 102 and extending to the substrate 101, wherein a first conductor material 106 is filled in the through hole 103, the first conductor material is etched back to a set depth to form an opening 1031 of the through hole 103, an isolation layer 1071 is formed at the opening 1031 of the through hole 103, the isolation layer 1071 covers the edge of the first conductor material 106, and the first conductor material 106 is exposed at the middle part of the isolation layer 1071; and
a second conductor material 109, the second conductor material 109 being filled in the middle of the isolation layer 1071, a barrier adhesion layer 108 being provided between the first conductor material 106 and the second conductor material 109.
In an embodiment of the present invention, the via 103 is etched back to form an opening 1031. The isolation layer 1071 is formed at an edge position of the first conductor material 106 near the opening 1031 of the via 103. The isolation layer 1071 effectively reduces the exposed area of the first conductor material 106 and effectively prevents the first conductor material 106 from contacting the second conductor material 109 in the wiring layer, thereby reducing the risk of shorting the semiconductor structure.
In addition, the spacer 1071 can effectively reduce the distance between the first conductor material 106 and the second conductor material 109, which effectively reduces the area occupied by the entire conductor line in the wiring layer.
In one embodiment of the present invention, as shown in fig. 7, a semiconductor structure includes:
a substrate 101;
a hard mask 102, the hard mask 102 being formed on the substrate 101;
a through hole 103 penetrating through the hard mask plate 102 and extending to the substrate 101, an insulating layer 104 is formed on the inner wall of the through hole 103, a first blocking adhesive layer 105 is formed on the insulating layer 104, a cavity formed by the first blocking adhesive layer 105 is filled with a first conductor material 106, the first conductor material is etched back to a set depth to form an opening 1031 of the through hole, the cavity is provided with an opening 1031 positioned on one side of the hard mask plate 102, which is far away from the substrate 101, an isolation layer 1071 is formed at the opening 1031 of the cavity, the isolation layer 1071 covers the edge of the first conductor material 106, the first conductor material 106 is exposed at the middle part of the isolation layer 1071, and the isolation layer 1071 is an insulating material; and
a wiring layer disposed on the hard mask plate 102 and at the opening 1031 of the cavity, the wiring layer including a second conductor material 109, the second conductor material 109 being filled in the middle of the isolation layer 1071, and a second barrier adhesion layer 108 being disposed between the first conductor material 106 and the second conductor material 109.
Specifically, the substrate 101 is made of silicon, such as polysilicon, monocrystalline silicon, or the like. The substrate 101 is typically a wafer. The hard mask 102 is an insulating material, such as at least one of silicon dioxide, silicon nitride, and titanium nitride. The material has good insulating property and high structural strength.
The hard mask 102 made of a single material, such as silicon dioxide, is liable to generate warpage phenomenon, resulting in a decrease in strength and deterioration in durability of the semiconductor structure. In a preferred example, the hard mask 102 includes silicon dioxide layers 1021 and silicon nitride layers 1022 alternately arranged in the thickness direction. The silicon dioxide layer 1021 generates compressive stress and the silicon nitride layer 1022 generates tensile stress. The alternately arranged silicon dioxide layers 1021 and silicon nitride layers 1022 can effectively relieve Heng La stress and compressive stress, so that the warping of the hard mask plate 102 can be effectively reduced, and the overall strength of the semiconductor structure can be further improved.
In this example, the silicon nitride layer 1022 is an etch stop layer. I.e., the silicon oxide layer 1021 is etched until the silicon nitride layer 1022 is etched, so as to control the etching depth. In this way, the silicon nitride layer 1022 can effectively avoid the problem of excessive etching depth.
In other examples, the material of the etching stop layer is at least one of silicon oxynitride and silicon carbonitride. The above materials can all play a role in controlling etching depth.
Of course, the materials of the substrate 101 and the hard mask 102 are not limited to the above embodiments, and those skilled in the art can set the materials according to actual needs.
The through hole 103 may be formed in various ways, for example, a wet etching process, a dry etching process, and the like. The size and depth of the through holes 103 can be set by those skilled in the art according to actual needs. The insulating layer 104 and the first barrier adhesion layer 105 are thin layers attached to the inner walls of the through-holes 103. The insulating layer 104 is located between the first barrier adhesion layer 105 and the inner wall of the via 103. The first barrier adhesion layer 105 encloses a cavity. The cavity is filled with a first conductor material 106. The first conductor material 106 is made of metal, such as copper, tungsten, etc. The isolation layer 1071 is formed by chemical vapor deposition. The isolation layer 1071 is an insulating material so that the exposed area of the first conductor material 106 can be reduced to reduce the probability of contact with other conductor materials, such as the second conductor material 109 described below, and reduce shorting. Optionally, the first conductor material 106 and the second conductor material 109 are made of metal, such as copper, aluminum, gold, silver, and the like. The first conductor material 106 and the second conductor material 109 are the same or different.
The wiring layer is used for forming a conductor line, and the conductor line is used for inputting an electric signal into the semiconductor structure. The wiring layer covers the hard mask plate 102 at the opening 1031 of the cavity. The second conductor material 109 forms conductor lines according to a set line pattern.
In one example, the isolation layer 1071 is made of at least one of silicon oxycarbide, silicon oxyfluoride, and organic polymer. The insulating property of the above material is good, and the formation process of the insulating layer 1071 is simple.
Organic polymers include plastics, thermoplastic elastomers, and the like.
The silicon oxycarbide also has good corrosion resistance effect and can effectively resist etching liquid used in a wet etching process.
Of course, the material of the isolation layer 1071 is not limited to the above embodiment, and those skilled in the art can select the material based on actual needs.
In one example, the spacer 1071 is annular in shape. The outer diameter of the isolation layer 1071 gradually increases from the side closer to the first conductor material 106 to the side farther from the first conductor material 106.
An inverted trapezoid structure 1031a is formed at an opening 1031 of the through-hole 103. The isolation layer 1071 is disposed around the inverted trapezoid structure 1031a to form a horn-like ring structure. The isolation layer 1071 of this structure can effectively cover the edges of the first conductor material 106.
Further, the inner diameter of the isolation layer 1071 is smaller than or equal to the inner diameter of the portion below the opening 1031 of the through-hole 103. In this way, the isolation layer 1071 effectively reduces the area of the first conductor material 106 exposed at the opening 1031, further reducing the risk of contact with the second conductor material 109, reducing the risk of shorting of the semiconductor structure.
In one example, the spacer 1071 has a thickness of 0.5 μm to 10 μm at the highest point and the spacer 1071 has a height of 1 μm to 3 μm. The thickness is the dimension of the isolation layer 1071 along the radial direction of the through hole 103, and the height is the dimension of the isolation layer 1071 along the axial direction of the through hole 103. Within this size range, the isolation layer 1071 can more effectively prevent the first conductor material 106 from contacting the second conductor material 109 in the wiring layer, thereby reducing the risk of shorting the semiconductor structure.
In one example, the first barrier adhesion layer 105 and the second barrier adhesion layer 108 are at least one of refractory metals, nitrides of refractory metals, and nitrides thereof. Alternatively, the refractory metal is titanium or tantalum. For example, the first barrier adhesion layer 105 or the second barrier adhesion layer 108 is one of titanium, titanium nitride, titanium, and titanium nitride; it may be one of tantalum, tantalum nitride, tantalum and titanium nitride.
The above-described materials effectively prevent the migration of the first conductor material 106, the second conductor material 109, into the surrounding materials.
Of course, the refractory metals are not limited to the above embodiments and may be selected by those skilled in the art according to actual needs.
In one example, the material of the insulating layer 104 is at least one of silicon dioxide, silicon nitride, and an organic polymer. The material has good insulativity, and can effectively avoid the occurrence of short circuit of a semiconductor structure.
In one example, the wiring layer includes an interlayer dielectric layer 110, the second conductor material 109 is embedded in the interlayer dielectric layer 110, and the material of the interlayer dielectric layer 110 is at least one of silicon dioxide, phosphosilicate glass, and borophosphosilicate glass.
The interlayer dielectric layer 110 is an insulating material. For example, a trench is formed on the interlayer dielectric layer 110 by etching. The second conductor material 109 is formed in the trench by chemical vapor deposition to form a conductor line. The material has good insulating property and high structural strength. An interlayer dielectric layer 110 is formed on the hard mask plate 102 by physical vapor deposition or chemical vapor deposition.
In another embodiment of the present invention, an electronic device is provided. The electronic device comprises the semiconductor structure.
The electronic device may be, but is not limited to being used in a cell phone, a computer, a watch, a sound box, a display screen, etc.
In one example, the electronic device includes a first element and a second element, the semiconductor structure is located between the first element and the second element, the first element is connected with the second conductor material, the first conductor material is connected with the second element at an end of the through hole, which is far away from the second conductor material, and the first element is conducted with the second element through the first conductor material and the second conductor material.
In this example, the first element and the second element are turned on by the semiconductor structure, and the electronic apparatus can precisely control the on/off of the first element and the second element.
In yet another embodiment of the present invention, a method of fabricating a semiconductor structure is provided. The preparation method comprises the following steps: providing a substrate 101;
depositing a hard mask 102 on the substrate 101;
forming a through hole 103 on the hard mask plate 102, the through hole extending to the substrate 101;
filling a first conductor material 106 in the through hole 103;
removing the first conductor material 106 at the opening 1031 of the via 103 by an etching back process;
forming an isolation layer 1071 at an opening of the through hole 103, wherein the isolation layer 1071 covers an edge of the first conductor material 106, and the first conductor material 106 is exposed to a middle part of the isolation layer 1071;
a blocking adhesion layer and a second conductor material 109 are formed on the hard mask plate 102, the second conductor material 109 is filled in the middle of the isolation layer 1071, and the blocking adhesion layer is disposed between the first conductor material 106 and the second conductor material 109.
The preparation method can prepare the semiconductor structure.
In one embodiment of the present invention, as shown in fig. 2 to 7, the preparation method includes:
providing a substrate 101;
depositing a hard mask 102 on the substrate 101;
forming a through hole 103 on the hard mask plate 102, the through hole 103 extending to the substrate 101;
forming an insulating layer 104 and a first blocking adhesive layer 105 on the substrate 101, wherein a cavity is formed in the first blocking adhesive layer 105, the cavity is provided with an opening 1031 positioned on one side of the hard mask plate 102, which is away from the substrate 101, and a first conductor material 106 is filled in the cavity;
removing the first conductor material 106 and the first barrier adhesion layer 105 at the opening 1031 of the cavity by an etching back process;
forming an isolation layer 1071 at an opening 1031 of the cavity, wherein the isolation layer 1071 covers the edge of the first conductor material 106, the first conductor material 106 is exposed to the middle part of the isolation layer 1071, and the isolation layer 1071 is an insulating material;
a second blocking adhesion layer 108 and a wiring layer are formed on the hard mask plate 102, the wiring layer including a second conductor material 109, the second conductor material 109 being filled in the middle of the isolation layer 1071, the second blocking adhesion layer 108 being provided between the first conductor material 106 and the second conductor material 109.
Specifically, the substrate 101 is made of silicon, such as polysilicon, monocrystalline silicon, or the like. The substrate 101 is typically a wafer. The hard mask 102 is deposited on the substrate 101 by physical vapor deposition, chemical vapor deposition, or the like. The hard mask 102 is an insulating material, such as at least one of silicon dioxide, silicon nitride, and titanium nitride. The material has good insulating property and high structural strength. The thickness of the hard mask plate 102 is set as desired by those skilled in the art.
In a preferred example, silicon dioxide layers 1021 and silicon nitride layers 1022 are sequentially deposited alternately to form the hard mask plate 102. The silicon oxide layers 1021 and the silicon nitride layers 1022 are alternately arranged in the thickness direction. The silicon dioxide layer 1021 generates compressive stress and the silicon nitride layer 1022 generates tensile stress. The alternately arranged silicon dioxide layers 1021 and silicon nitride layers 1022 can effectively relieve Heng La stress and compressive stress, so that the warping of the hard mask plate 102 can be effectively reduced, and the overall strength of the semiconductor structure can be further improved. The silicon nitride layer 1022 is an etching stop layer, i.e., when the silicon oxide layer 1021 is etched, the etching is stopped from the time when the silicon nitride layer 1022 is etched, so as to control the etching depth. In this way, the silicon nitride layer 1022 can effectively avoid the problem of excessive etching depth. In other examples, the material of the etching stop layer is at least one of silicon oxynitride and silicon carbonitride. The above materials can all play a role in controlling etching depth.
A through hole 103 is formed in the hard mask plate 102 by a wet etching process, a dry etching process, or the like. The size and depth of the through holes 103 can be set by those skilled in the art according to actual needs.
An insulating layer 104 and a first barrier adhesion layer 105 are formed on the substrate 101 by physical vapor deposition, chemical vapor deposition, or the like. The insulating layer 104 and the first barrier adhesion layer 105 are both located within the via 103. The first barrier adhesion layer 105 forms a cavity within the via 103. The insulating layer 104 and the first barrier adhesion layer 105 are formed as described above. The first conductor material 106 is a metal, such as copper, gold, silver, or the like. A first conductor material 106 is formed within the cavity by electroplating. Before the plating, a seed layer is formed on the first barrier adhesion layer 105 using a physical sputtering method in order to allow the plated metal to be firmly adhered to the first barrier adhesion layer 105. The seed layer is of a material that is consistent with the material of the first conductor material 106. The seed layer forms a crystallization nucleus, so that metal grows on the crystallization nucleus during electroplating, which makes the electroplating effect better.
The first barrier adhesion layer 105 at the opening 1031 of the cavity is etched away using an etch back process. An isolation layer 1071 is formed at the opening 1031 of the cavity by physical vapor deposition, chemical vapor deposition, or the like. For example, a layer of isolation layer 1071 is integrally deposited on the hard mask 102, and then the isolation layer 1071 at the opening 1031 is remained by etching, so that the isolation layer 1071 at other positions is removed. The material of the isolation layer 1071 may be, but not limited to, an insulating material such as silicon nitride or silicon carbide.
The second barrier adhesion layer 108 is formed on the hard mask plate 102 by physical vapor deposition, chemical vapor deposition, or the like. The wiring layer may be formed by the above-described deposition method. The second conductor material 109 fills the middle of the isolation layer 1071. The second barrier adhesion layer 108 separates the first conductor material 106 from the second conductor material 109.
The preparation method has the characteristics of simple process and stable structure of the formed semiconductor.
In one example, the forming the isolation layer 1071 at the opening 1031 of the cavity, the isolation layer 1071 covers the edge of the first conductor material 106, the first conductor material 106 is exposed at the middle of the isolation layer 1071, the isolation layer 1071 is an insulating material, and includes:
removing the first conductor material 106 and the first barrier adhesion layer 105 at the opening 1031 of the cavity;
depositing an isolation film layer 107 on the hard mask plate 102 and at the opening 1031 of the cavity;
the isolation film 107 on the hard mask plate 102 is removed to form the isolation layer 1071 at the opening 1031 of the cavity, and the first conductor material 106 is exposed to the middle of the isolation layer 1071.
For example, the first conductor material 106 and the first barrier adhesion layer 105 at the opening 1031 of the cavity are removed using a dry etching process, a wet etching process. The isolation film layer 107 is made of an insulating material, such as at least one of silicon oxycarbide, silicon oxyfluoride, and organic polymer.
In this way, the insulating layer 1071 is formed to have a complete structure and a uniform thickness, and thus can provide a good insulating effect.
In one example, the depositing the isolation film 107 on the hard mask plate 102 and at the opening 1031 of the cavity includes:
the isolation film 107 is deposited by chemical vapor deposition. The thickness of the isolation film layer 107 formed by the method is uniform, and the structure is complete.
In one example, the removing the isolation film 107 on the hard mask plate 102 to form the isolation layer 1071 at the opening 1031 of the cavity, the first conductor material 106 is exposed at a middle portion of the isolation layer 1071, includes: the isolation film layer 107 is removed by anisotropic dry etching.
This ensures that a ring-shaped isolation layer 1071 is formed at the opening 1031 of the cavity to isolate the edges of the first conductor material 106.
In one example, the depositing the hard mask 102 on the substrate 101 includes:
In this way, the thickness of the silicon oxide layer 1021 and the silicon nitride layer 1022 formed is uniform. The connection strength of the two film layers is high. The alternately arranged silicon dioxide layers 1021 and silicon nitride layers 1022 can effectively avoid the warpage phenomenon of the hard mask plate 102.
In one example, the forming the insulating layer 104 and the first blocking adhesive layer 105 on the substrate 101, the first blocking adhesive layer 105 forms a cavity therein, the cavity has an opening 1031 located on a side of the hard mask plate 102 facing away from the substrate 101, and the cavity is filled with the first conductor material 106, including:
depositing the insulating layer 104 in the through hole 103 by adopting an atomic layer deposition method;
a seed layer for forming the first barrier adhesion layer 105 and the first conductor material 106 is deposited in the through hole 103 by a physical sputtering method;
the first conductor material 106 is electroplated on the seed layer using an electroless plating process.
Atomic layer deposition refers to a method of plating materials in the form of a monoatomic film layer by layer on the surface of the via 103. The thickness of the insulating layer 104 formed in this way is accurate and controllable. The atomic layer deposition method can form a uniform insulating layer 104 within the via 103.
The physical sputtering method refers to bombarding the surface of a target with ions to knock out atoms of the target to form sputtering, and the sputtered atoms are deposited on the inner wall of the through hole 103. In this way, the first barrier adhesive layer 105 having a uniform and dense thickness can be formed, and the seed layer can be uniformly adhered to the first barrier adhesive layer 105. The seed layer is capable of nucleation during the electroplating process, thereby allowing for a significant increase in the efficiency of the electroplating, and a more rapid and uniform formation of the first conductor material 106.
In one example, the removing the first conductor material 106 and the first barrier adhesion layer 105 at the opening 1031 of the cavity using an etch back process includes:
the etching back process is a wet etching process.
The wet etching process can precisely remove the first conductor material 106 and the first barrier adhesion layer 105 at the cavity opening 1031.
In one example, the forming the second blocking adhesion layer 108 and the wiring layer on the hard mask plate 102, where the wiring layer includes a second conductor material 109, the second conductor material 109 is filled in the middle of the isolation layer 1071, and the second blocking adhesion layer 108 is disposed between the first conductor material 106 and the second conductor material 109, and includes:
and depositing a silicon nitride film serving as an etching stop layer by adopting a chemical vapor deposition method, and depositing a high-filling silicon dioxide film on the silicon nitride film.
The silicon nitride can prevent etching of the etching liquid. Silicon nitride is used as an etching stop layer to ensure etching accuracy. The highly filled silicon dioxide film has a good insulating effect and can be used as an interlayer dielectric for the second conductor material 109. And forming a wiring groove by etching the silicon dioxide film. And taking the etching stop layer as an etching termination point. The second conductor material 109 is then filled in the wiring trench to form an electrode.
In one example, the wiring groove is a metal wiring groove. Forming a metal wiring pattern on the photoresist by adopting a photoetching process;
and etching the silicon dioxide film by adopting dry etching to form the metal wiring groove.
The metal wiring groove is filled with a metal material as the second conductor material 109.
In one example, the etch stop layer is etched using a wet etch process;
and sequentially depositing the second barrier adhesion layer 108 and the seed layer of the second conductor material 109 in the metal wiring groove by using a physical sputtering method.
The first conductor material 106 can be exposed by wet etching the etch stop layer. A seed layer of the second barrier adhesion layer 108 and the second conductor material 109 can be formed on the first conductor material 106 using a physical sputtering method.
Further, the second conductor material 109 is electroplated within the metal wiring trench using an electroless plating process. The seed layer is the same material as the second conductor material 109. The seed layer can form nuclei, which facilitates the electroplating of the second conductor material 109, the plating is uniform, and the bonding of the second conductor material 109 to the second barrier adhesion layer 108 is strong.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A semiconductor structure, comprising:
a substrate (101);
a hard mask plate (102), the hard mask plate (102) being formed on the substrate (101);
a through hole (103) penetrating through the hard mask plate (102) and extending to the substrate (101), wherein a first conductor material (106) is filled in the through hole (103), the first conductor material is etched back to a set depth to form an opening (1031) of the through hole, an isolation layer (1071) is formed at the opening (1031) of the through hole, the isolation layer (1071) covers the edge of the first conductor material (106), and the first conductor material (106) is exposed in the middle of the isolation layer (1071); and
-a second conductor material (109), the second conductor material (109) being filled in the middle of the isolation layer (1071), a barrier adhesion layer (108) being provided between the first conductor material (106) and the second conductor material (109).
2. The semiconductor structure according to claim 1, wherein the isolation layer (1071) is made of at least one of silicon oxycarbide, silicon oxyfluoride, and organic polymer.
3. The semiconductor structure of claim 1, wherein the isolation layer (1071) is annular, the outer diameter of the isolation layer (1071) gradually increasing from a side closer to the first conductor material (106) to a side farther from the first conductor material (106).
4. The semiconductor structure of claim 1, wherein the spacer layer has a thickness of 0.5 μm to 10 μm at the highest point and a height of 1 μm to 3 μm.
5. The semiconductor structure of claim 4, wherein the hard mask (102) comprises silicon dioxide layers (1021) and silicon nitride layers (1022) that are alternately arranged in a thickness direction, wherein the silicon nitride layers are etch stop layers.
6. A method of fabricating a semiconductor structure, comprising:
providing a substrate (101);
depositing a hard mask (102) over the substrate (101);
forming a through hole (103) on the hard mask plate (102), wherein the through hole (103) extends to the substrate (101);
filling a first conductor material (106) in the via hole;
removing the first conductor material (106) at the opening (1031) of the via using an etch back process;
-forming an isolation layer (1071) at an opening (1031) of the via, the isolation layer (1071) covering an edge of the first conductor material (106), the first conductor material (106) being exposed to a middle portion of the isolation layer (1071);
a blocking adhesion layer (108) and a second conductor material (109) are formed on the hard mask plate (102), the second conductor material (109) is filled in the middle of the isolation layer (1071), and the blocking adhesion layer (108) is arranged between the first conductor material (106) and the second conductor material (109).
7. The method of manufacturing a semiconductor structure according to claim 6, wherein the forming an isolation layer (1071) at the opening (1031) of the cavity, the isolation layer (1071) covering an edge of the first conductor material (106), the first conductor material (106) being exposed to a middle portion of the isolation layer (1071), comprises:
depositing an isolation film layer (107) on the hard mask plate (102) and at an opening (1031) of the cavity;
the isolation film layer (107) on the hard mask plate (102) is removed to form the isolation layer (1071) at the opening (1031) of the cavity, and the first conductor material (106) is exposed to the middle of the isolation layer (1071).
8. The method of manufacturing a semiconductor structure according to claim 7, wherein the isolation film layer (107) is deposited by chemical vapor deposition;
and removing the isolation film layer (107) by adopting an anisotropic dry etching method.
9. An electronic device comprising a semiconductor structure as claimed in any one of claims 1-5.
10. The electronic device of claim 9, comprising a first element and a second element, wherein the semiconductor structure is located between the first element and the second element, wherein the first element is connected to the second conductor material, wherein the first conductor material is connected to the second element at an end of the via hole facing away from the second conductor material, and wherein the first element is in communication with the second element through the first conductor material and the second conductor material.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310321243.4A CN116153906A (en) | 2023-03-29 | 2023-03-29 | Semiconductor structure, preparation method thereof and electronic equipment |
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|---|---|---|---|
| CN202310321243.4A CN116153906A (en) | 2023-03-29 | 2023-03-29 | Semiconductor structure, preparation method thereof and electronic equipment |
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| CN116153906A true CN116153906A (en) | 2023-05-23 |
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| CN202310321243.4A Pending CN116153906A (en) | 2023-03-29 | 2023-03-29 | Semiconductor structure, preparation method thereof and electronic equipment |
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| Country | Link |
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| CN (1) | CN116153906A (en) |
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