CN116153861B - Semiconductor structure and preparation method - Google Patents
Semiconductor structure and preparation method Download PDFInfo
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- CN116153861B CN116153861B CN202310423985.8A CN202310423985A CN116153861B CN 116153861 B CN116153861 B CN 116153861B CN 202310423985 A CN202310423985 A CN 202310423985A CN 116153861 B CN116153861 B CN 116153861B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000002360 preparation method Methods 0.000 title abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 128
- 239000002184 metal Substances 0.000 claims abstract description 127
- 239000010949 copper Substances 0.000 claims abstract description 116
- 229910052802 copper Inorganic materials 0.000 claims abstract description 109
- 239000000758 substrate Substances 0.000 claims abstract description 77
- -1 copper nitride Chemical class 0.000 claims abstract description 41
- 230000008439 repair process Effects 0.000 claims abstract description 39
- 238000001020 plasma etching Methods 0.000 claims abstract description 14
- 230000000149 penetrating effect Effects 0.000 claims abstract description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 69
- 238000000034 method Methods 0.000 claims description 50
- 150000004767 nitrides Chemical class 0.000 claims description 50
- 230000004888 barrier function Effects 0.000 claims description 45
- 239000002131 composite material Substances 0.000 claims description 21
- 238000000151 deposition Methods 0.000 claims description 20
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 18
- 238000009713 electroplating Methods 0.000 claims description 17
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 16
- 238000010438 heat treatment Methods 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 12
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 12
- 239000013077 target material Substances 0.000 claims description 12
- 238000000354 decomposition reaction Methods 0.000 claims description 11
- 239000010936 titanium Substances 0.000 claims description 11
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 8
- 229910052757 nitrogen Inorganic materials 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 7
- 229910052715 tantalum Inorganic materials 0.000 claims description 6
- 230000008859 change Effects 0.000 claims description 5
- 230000007423 decrease Effects 0.000 claims description 5
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 11
- 238000005979 thermal decomposition reaction Methods 0.000 abstract description 3
- 230000008569 process Effects 0.000 description 24
- 238000010586 diagram Methods 0.000 description 19
- 230000008021 deposition Effects 0.000 description 12
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 11
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 10
- 229910052786 argon Inorganic materials 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- IUYOGGFTLHZHEG-UHFFFAOYSA-N copper titanium Chemical compound [Ti].[Cu] IUYOGGFTLHZHEG-UHFFFAOYSA-N 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 239000002243 precursor Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000012298 atmosphere Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910001431 copper ion Inorganic materials 0.000 description 2
- CIYRLONPFMPRLH-UHFFFAOYSA-N copper tantalum Chemical compound [Cu].[Ta] CIYRLONPFMPRLH-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The application provides a semiconductor structure and a preparation method thereof, wherein a dielectric layer and a channel penetrating through the dielectric layer are formed on one side of a substrate, and a copper nitride layer is formed on the inner wall of the channel, the exposed surface of the substrate and one side of the dielectric layer away from the substrate; plasma etching the copper nitride layer to remove overhang of the copper nitride layer formed at the opening of the channel; performing thermal decomposition on the copper nitride layer to form a seed layer; and forming a repair layer and a main body layer on one side of the seed layer, which is far away from the substrate, in sequence, wherein the seed layer, the repair layer and the main body layer form a conductive layer of an interconnection structure. Because the density of the copper nitride layer is smaller than that of the corresponding pure metal, and the step coverage performance of the copper nitride layer is better than that of the corresponding pure metal, overhang formed at the opening of the channel is relatively smaller, the overhang is more convenient to remove, overhang removal efficiency is improved, the opening is increased, and further, the channel can be completely filled by subsequent electroplated metal, and defects such as cavities are not easy to form are overcome.
Description
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor structure and a method for fabricating the same.
Background
With the continuous development of integrated circuit processes, in order to reduce the delay caused by the resistance of the metal wires, the metal interconnection wires are changed from aluminum wires to copper wires, and meanwhile, the copper wires have better electromigration resistance than the aluminum wires.
Since copper cannot be etched to form a wire like aluminum, a copper damascene process is developed, and a channel is formed by photolithography and etching, and then copper is filled to form a metal wire.
The traditional method for filling copper adopts an electrochemical mode, namely, a wafer is used as a cathode to reduce copper ions for electroplating. Therefore, a copper seed layer needs to be grown before electroplating to ensure the conduction of cathode current during electroplating, and the copper seed layer is deposited in a magnetron sputtering mode.
With the continuous progress of the process, the depth-to-width ratio of the wire interconnection channel is increased, the requirement on the copper seed layer is higher and higher, so that the good step coverage rate is ensured to ensure that the subsequent electroplating is smoothly carried out, meanwhile, the situation that large overhang cannot be formed at the opening of the interconnection channel is ensured, and the subsequent electroplating is not easy to seal in advance to form a cavity.
Disclosure of Invention
In view of the above, this summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.
The purpose of the application is to provide a semiconductor structure and a preparation method, which improve the overhang removal efficiency, and further enable the follow-up electroplated metal to fill the channel completely, so that defects such as cavities are not easy to form are overcome.
In order to achieve the above purpose, the present application has the following technical scheme:
in a first aspect, an embodiment of the present application provides a method for preparing a semiconductor structure, including:
providing a substrate;
forming a dielectric layer on one side of the substrate;
etching the dielectric layer to form a channel penetrating through the dielectric layer so as to expose the surface of the substrate;
forming a copper nitride layer on the inner wall of the channel, the exposed surface of the substrate and one side of the dielectric layer far away from the substrate by magnetron sputtering target materials in a nitrogen atmosphere;
plasma etching the copper nitride layer to remove overhang of the copper nitride layer formed at the opening of the channel;
performing heating decomposition on the copper nitride layer to remove nitrogen element in the copper nitride layer, so as to form a seed layer;
and forming a repair layer and a main body layer on one side of the seed layer, which is far away from the substrate, in sequence, wherein the seed layer, the repair layer and the main body layer form a conductive layer of an interconnection structure.
In one possible implementation manner, after the etching the dielectric layer to form a channel penetrating the dielectric layer, before magnetron sputtering the target material in a nitrogen atmosphere, the method further includes:
forming a barrier layer on the inner wall of the channel, the exposed surface of the substrate and one side of the dielectric layer away from the substrate;
the material of the barrier layer comprises:
at least one of titanium, tantalum, titanium nitride and tantalum nitride.
In one possible implementation, the barrier layer includes a first metal element, and the target includes a copper element;
after forming the barrier layer, before forming the copper nitride layer, further comprising:
forming a composite metal nitride layer by magnetron sputtering of an intermediate target in a nitrogen atmosphere; the intermediate target includes the first metal element and the copper element. In one possible implementation, the content of the copper element is greater than the content of the first metal element in the composite metal nitride layer.
In one possible implementation manner, after forming the composite metal nitride layer, the method further includes:
and carrying out heating decomposition on the composite metal nitride layer to form a graded layer.
In one possible implementation, forming the repair layer includes: depositing a repair layer on a side of the seed layer away from the substrate under a radio frequency bias of a first power; the first power is greater than or equal to 120W and less than or equal to 200W.
In one possible implementation, forming the body layer includes: and electroplating and depositing a main body layer on one side of the repair layer, which is far away from the substrate, in the channel, wherein the main body layer fills the channel.
In a second aspect, embodiments of the present application provide a semiconductor structure, including:
the substrate and the dielectric layer is positioned on one side of the substrate, the dielectric layer comprises at least one channel penetrating through the dielectric layer, and the channel exposes the surface of the substrate;
an interconnect structure filling the channel; the interconnect structure includes: the device comprises a barrier layer, a gradual change layer and a conductive layer, wherein the conductive layer comprises a seed layer, a repair layer and a main body layer; the barrier layer covers the inner wall of the channel and the exposed surface of the substrate, and the gradual change layer is positioned between the barrier layer and the conductive layer;
the barrier layer comprises a first metal element, the conductive layer comprises a copper element, the graded layer comprises the first metal element and the copper element, and the content of the copper element in the graded layer is larger than that of the first metal element.
In one possible implementation manner, along the direction of the barrier layer pointing to the conductive layer, the content of the first metal element in the graded layer gradually decreases, and the content of the copper element in the graded layer gradually increases.
In one possible implementation, the graded layer is a composite metal layer including a nitride formed of the first metal element and a pure metal formed of the copper element.
Compared with the prior art, the embodiment of the application has the following beneficial effects:
the embodiment of the application provides a semiconductor structure and a preparation method thereof, wherein the method comprises the following steps: providing a substrate, and forming a dielectric layer on one side of the substrate; etching the dielectric layer to form a channel penetrating through the dielectric layer so as to expose the surface of the substrate; under the atmosphere of nitrogen, forming a copper nitride layer on the inner wall of the channel, the exposed surface of the substrate and one side of the dielectric layer far away from the substrate by magnetron sputtering target materials; plasma etching the copper nitride layer to remove overhang of the copper nitride layer formed at the opening of the channel; performing heating decomposition on the copper nitride layer to remove nitrogen element in the copper nitride layer and form a seed layer; and forming a repair layer and a main body layer on one side of the seed layer, which is far away from the substrate, in sequence, wherein the seed layer, the repair layer and the main body layer form a conductive layer of an interconnection structure. The density of the copper nitride layer formed through magnetron sputtering is smaller than that of corresponding pure metal, the step coverage performance of the copper nitride layer is superior to that of the corresponding pure metal, overhang at the opening of the channel is smaller than that formed by the traditional pure metal, overhang is more convenient to remove, overhang removal efficiency is improved, the opening is increased, and further the subsequent electroplated metal can completely fill the channel and is difficult to form defects such as holes.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
The above and other features, advantages, and aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. The same or similar reference numbers will be used throughout the drawings to refer to the same or like elements. It should be understood that the figures are schematic and that elements and components are not necessarily drawn to scale.
FIG. 1 illustrates a schematic diagram of copper deposition in an interconnect via provided in an embodiment of the present application;
FIG. 2 is a schematic diagram of an interconnect structure formed by copper deposition in an interconnect via according to an embodiment of the present application;
fig. 3 is a flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of the present application;
FIG. 4 illustrates a schematic diagram of a semiconductor structure provided in an embodiment of the present application;
FIG. 5 illustrates a schematic diagram of yet another semiconductor structure provided by embodiments of the present application;
FIG. 6 illustrates a schematic diagram of another semiconductor structure provided by embodiments of the present application;
fig. 7 shows a schematic view of yet another semiconductor structure provided in an embodiment of the present application;
FIG. 8 illustrates a schematic diagram of yet another semiconductor structure provided by embodiments of the present application;
fig. 9 shows a schematic diagram of yet another semiconductor structure provided in an embodiment of the present application;
FIG. 10 illustrates a schematic diagram of another semiconductor structure provided by embodiments of the present application;
FIG. 11 illustrates a schematic diagram of yet another semiconductor structure provided by embodiments of the present application;
fig. 12 shows a schematic view of yet another semiconductor structure provided in an embodiment of the present application;
fig. 13 shows a schematic diagram of a semiconductor structure according to an embodiment of the present application.
Detailed Description
In order to make the above objects, features and advantages of the present application more comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present application is not limited to the specific embodiments disclosed below.
Just like the related art, in order to solve the problem that in the process of forming an interconnection structure by copper deposition, overhang is easily formed at an opening position, and then a cavity is formed by sealing in advance, the application provides an interconnection structure and a preparation method thereof.
Referring to fig. 1, a schematic diagram of copper deposition in an interconnect channel is shown, a dielectric layer 2 is formed on a substrate 1, and a copper seed layer 3 is deposited in the interconnect channel of the dielectric layer 2.
The deposition of the copper seed layer 3 is largely divided into two steps, the first step being to deposit a portion of copper under a low power radio frequency [120w,200w ] bias; the second step is to use high power radio frequency [600W,800W ] bias voltage to deposit in order to improve the step coverage rate of the side wall of the interconnection channel, under the effect of the high bias voltage, copper ions have higher kinetic energy, can accelerate to reach the bottom of the interconnection channel, and sputter copper at the bottom to the side wall so as to improve the coverage rate of the side wall. The overhang 4 at the opening will then still be present and will have a great influence on the subsequent electroplating.
Referring to fig. 2, a schematic view of a copper interconnect structure formed in an interconnect via by the two-step deposition method is shown, and as the process further progresses, the feature size further decreases, and a larger overhang 4 is easily formed at the via opening by the copper seed layer 3 deposited by the method, and the overhang 4 at the interconnect via opening inevitably causes a void 5 formed by sealing in advance with the subsequent electroplated copper.
In order to meet the requirement of the prior process, the machine can be continuously modified and adjusted, which can certainly greatly raise the equipment cost of the factory.
Based on the above technical problems, embodiments of the present application provide a semiconductor structure and a method for manufacturing the same, where the method includes: providing a substrate, and forming a dielectric layer on one side of the substrate; etching the dielectric layer to form a channel penetrating through the dielectric layer so as to expose the surface of the substrate; forming a metal nitride layer on the inner wall of the channel, the exposed surface of the substrate and one side of the dielectric layer far away from the substrate by magnetron sputtering of the target material in a nitrogen atmosphere; plasma etching the metal nitride layer to remove overhang of the metal nitride layer formed at the opening of the channel; performing heating decomposition on the metal nitride layer to remove nitrogen element in the metal nitride layer and form a seed layer; and forming a repair layer and a main body layer on one side of the seed layer, which is far away from the substrate, in sequence, wherein the seed layer, the repair layer and the main body layer form a conductive layer of an interconnection structure. The density of the metal nitride layer formed through magnetron sputtering is smaller than that of corresponding pure metal, the step coverage performance of the metal nitride layer is superior to that of the corresponding pure metal, overhang formed at the opening of the channel is smaller than that formed by the traditional pure metal, overhang is more convenient to remove, overhang removal efficiency is improved, the opening is increased, and further the subsequent electroplated metal can completely fill the channel and is difficult to form defects such as holes.
For a better understanding of the technical solutions and technical effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.
Referring to fig. 3, fig. 3 is a flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present application, including:
s101: providing a substrate;
s102: forming a dielectric layer on one side of the substrate;
s103: and etching the dielectric layer to form a channel penetrating through the dielectric layer so as to expose the surface of the substrate.
In the embodiment of the present application, referring to fig. 4, a schematic diagram of a semiconductor structure provided in the embodiment of the present application is shown, where the substrate 1 may be a semiconductor substrate, for example, may be a Si substrate, a Ge substrate, a SiGe substrate, an SOI (silicon on insulator ), a GOI (germanium on insulator, germanium On Insulator), or the like. In other embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, such as GaAs, inP, siC, or the like, may also be a stacked structure, such as Si/SiGe, or the like, and may also be other epitaxial structures, such as SGOI (silicon germanium on insulator), or the like. In this embodiment, the substrate 1 is a bulk silicon substrate.
The dielectric layer 2 may be made of an insulating material, and the material of the dielectric layer 2 may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer, for example, and in this embodiment, the dielectric layer 2 is a silicon oxide layer.
For the subsequent formation of the interconnection structure, the embodiment of the present application may etch the dielectric layer 2 to form a channel 31 penetrating the dielectric layer, where the channel 31 penetrates the dielectric layer 2 in the thickness direction to expose the upper surface of the substrate 1.
Alternatively, the channel 31 may include a through hole or a trench, which is not specifically limited herein, and may be specifically set by a person skilled in the art according to the shape of the actual interconnect structure.
S104: forming a metal nitride layer on the inner wall of the channel, the exposed surface of the substrate and one side of the dielectric layer far away from the substrate by magnetron sputtering target materials in a nitrogen atmosphere;
s105: and plasma etching the metal nitride layer to remove overhang of the metal nitride layer formed at the opening of the channel.
Referring to fig. 5, a schematic diagram of another semiconductor structure according to an embodiment of the present application is shown.
That is, in the embodiment of the present application, the target material may be magnetron sputtered under a nitrogen atmosphere, so that the metal nitride layer 6 may be formed on the inner wall of the channel 31, the exposed surface of the substrate 1, and the side of the dielectric layer 2 away from the substrate 1.
Because the density of the metal nitride layer 6 formed by magnetron sputtering is smaller than that of the corresponding pure metal, and the step coverage performance of the metal nitride layer 6 is better than that of the corresponding pure metal, the overhang 4 formed at the opening of the interconnection channel is smaller than that formed by the traditional pure metal, the overhang 4 is more convenient to remove, the removal efficiency of the overhang 4 is improved, the opening is increased, and further, the subsequent electroplated metal can completely fill the interconnection channel and is not easy to form defects such as holes.
For example, the target material provided in the embodiments of the present application may include a metal with better conductivity, such as metallic copper, and the formed metal nitride layer 6 may include a copper nitride layer with a density (5.84 g/cm 3 ) Less than pure copper (8.96 g/cm) 3 ）。
Specifically, in the present embodiment, plasma etching of the metal nitride layer 6 may be used to remove overhang 4 of the metal nitride layer 6 formed at the opening of the via 31.
For example, plasma etching may be performed under a high bias by introducing argon gas to thin the metal nitride layer 6 at the opening of the via 31, thereby reducing overhang 4 of the metal nitride layer 6. Alternatively, the plasma etch may be performed with a radio frequency bias voltage having a power greater than or equal to 600W and less than or equal to 800W.
Namely, the overhang 4 at the opening of the channel 31 is reduced through the optimization of the process, so that the existing equipment can meet the metal deposition requirement of a more advanced process, and the defect of the subsequent metal electroplating process caused by insufficient machine capability is avoided.
Compared with the prior art, the method provided by the embodiment can meet the requirement of filling metal under the condition of larger depth-to-width ratio of the channel 31, and greatly expands the process window; the machine for depositing the film layer has the capability of plasma etching, so that the existing machine is not required to be modified, and the process cost is not increased.
In addition, in the embodiment of the present application, a part of the metal nitride layer 6 may be deposited by using a low power (greater than or equal to 120W and less than or equal to 200W) rf bias, and then the reverse sputter deposition may be performed by using a high power (greater than or equal to 600W and less than or equal to 800W) rf bias, where under the effect of the high bias, the metal ions have a higher kinetic energy, and can accelerate to reach the bottom of the interconnect channel 31, and sputter the metal at the bottom to the sidewall, thereby improving the coverage rate of the sidewall.
S106: and carrying out heating decomposition on the metal nitride layer to remove nitrogen element in the metal nitride layer, so as to form a seed layer.
In an embodiment of the present application, referring to fig. 6, a schematic diagram of another semiconductor structure provided in an embodiment of the present application is shown.
To form a seed layer for subsequent bulk deposition of metal. The metal nitride layer 6 may be heated to remove nitrogen element in the metal nitride layer 6, forming the seed layer 7.
For example, when the metal nitride layer 6 is a copper nitride layer, the decomposition process of heating the copper nitride layer is: 2Cu 3N-6 Cu+N2 +.; the temperature for heating the copper nitride layer cannot be too high, otherwise, the performance of other semiconductor devices cannot be affected, the decomposition of the copper nitride layer cannot be completely reduced, and the conductivity of the copper nitride layer is poor, so that the overall conductivity of the interconnection structure can be affected.
Thus, alternatively, the copper nitride layer may be thermally decomposed in vacuum in embodiments of the present application at a temperature greater than or equal to 200 ℃ and less than or equal to 450 ℃. The heating temperature is lower than 200 ℃, the copper nitride layer may not be completely decomposed, and the performance of other semiconductor devices is affected by the excessive temperature, so that the copper nitride decomposition temperature is selected to be suitable from 200 ℃ to 450 ℃ in the embodiment, and the preferable decomposition temperature range is 300 ℃ to 450 ℃.
Alternatively, the thickness of the seed layer 7 formed in the embodiment of the present application may be greater than or equal to 1nm and less than or equal to 10nm.
Step S107: and forming a repair layer and a main body layer on one side of the seed layer, which is far away from the substrate, in sequence, wherein the seed layer, the repair layer and the main body layer form a conductive layer of an interconnection structure.
In this embodiment, as shown in fig. 7, during the process of etching the metal nitride layer by using the argon plasma, a slight damage may be caused to the surface structure of the film layer (such as the copper nitride layer), and further, damage may occur in the copper seed layer 7 formed after thermal decomposition. After the formation of the copper seed layer 7, a copper repair layer 71 is deposited on the side of the seed layer 7 remote from the substrate 1 under a radio frequency bias of a first power; the first power is greater than or equal to 120W and less than or equal to 200W. By using the low radio frequency bias to deposit the copper repair layer 71, the copper repair layer 71 can be ensured to be slowly deposited on the surface of the copper seed layer 7, the repair of the damage on the surface of the copper seed layer 7 can be well completed, and the reliability of the device structure can be improved.
After the copper repair layer 71 is formed, a large number of copper metal body layers 72 are formed by electroplating deposition to fill the interconnect channels; the resulting structure is then planarized by a chemical mechanical polishing (CMP, chemical mechanical polish) process, which removes the excess film structure over the dielectric layer 2. Referring to fig. 8, the copper seed layer 7, the copper repair layer 71 and the copper metal body layer 72 located in the interconnect via 31 collectively form an interconnect structure having good electrical conductivity.
In one possible implementation, referring to fig. 9, a schematic diagram of another semiconductor structure provided in an embodiment of the present application is shown.
In the embodiment of the present application, after etching the dielectric layer 2 to form the channel 31 penetrating the dielectric layer 2, before magnetron sputtering the target material in the nitrogen atmosphere, the method provided in the embodiment of the present application may further include:
a barrier layer 8 is formed on the inner walls of the channel 31, the exposed surface of the substrate 1 and the side of the dielectric layer 2 remote from the substrate 1. The barrier layer 8 may prevent the diffusion of the material of the subsequent magnetron sputtering into the substrate 1 and also prevent the diffusion of the impurities in the substrate 1 into the film structure of the subsequent deposition, and optionally, the material of the barrier layer 8 provided in the embodiments of the present application may include: at least one of titanium, tantalum, titanium nitride and tantalum nitride.
The above material has higher step coverage rate, can be better deposited on the inner wall of the channel 31, and the material of the barrier layer 8 can be: ti, ta, tiN, taN, ti/TiN, ta/TaN, ti/TiN/Ti, tiN/Ti/TiN, ta/TaN/Ta, taN/Ta/TaN, tiN/TaN, tiN/Ta/TaN, tiN/Ti/TaN, etc.; the thickness of the barrier layer 8 may be adjusted according to the actual process, for example, the thickness of the barrier layer 8 may be greater than or equal to 0.1nm and less than or equal to 5nm; the barrier layer 8 may be prepared using chemical vapor deposition (CVD, chemical Vapor Deposition), physical vapor deposition (PVD, physical Vapor Deposition), or atomic layer deposition (ALD, atomic Layer Deposition), among other processes.
In another possible implementation manner, referring to fig. 10, a schematic diagram of a structure in a manufacturing process of another semiconductor structure according to an embodiment of the present application is shown.
In the embodiment of the present application, the barrier layer 8 may include a first metal element, and the target material may include a second metal element.
After forming the barrier layer 8 and before forming the metal nitride layer 6, the method provided in the embodiment of the present application may further include:
the intermediate target, which may include a first metal element and a second metal element, is magnetron sputtered under a nitrogen atmosphere to form the composite metal nitride layer 91.
In one possible implementation, the content of the second metal element is greater than the content of the first metal element in the composite metal nitride layer 91.
For example, taking the composite metal nitride layer 91 as a copper-titanium nitride layer, the first metal element is titanium element, and the second metal element is copper element. The copper titanium nitride layer can be formed by first depositing a copper target and a titanium target which are simultaneously subjected to magnetron sputtering in a nitrogen atmosphere as an intermediate target. In the process of forming the copper titanium nitride layer, as the impedance of titanium is larger, the conductivity of copper is better, and the content of titanium can be gradually reduced and the content of copper can be gradually increased in the process of forming, so that in the finally formed copper titanium nitride layer, the content of copper element is larger than the content of titanium element, namely the copper titanium nitride layer TixCuyN, wherein x is gradually reduced and y is gradually increased.
Similarly, if the copper-tantalum nitride layer is finally formed, the content of copper element in the copper-tantalum nitride layer is larger than that of tantalum element. I.e., the titanium copper nitride layer, taxCuyN, wherein x gradually decreases and y gradually increases.
In one possible implementation, referring to fig. 11, a schematic diagram of another semiconductor structure provided in an embodiment of the present application is shown.
After forming the composite metal nitride layer 91, the method provided in the embodiment of the present application may further include:
the composite metal nitride layer 91 is thermally decomposed to form a graded layer 92.
That is, in the embodiment of the present application, the composite metal nitride layer 91 may be heated, so that the nitrogen element and the metal element in the composite metal nitride layer 91 are also decomposed to form the graded layer 92.
For example, the TixCuyN may be thermally decomposed in vacuum at a temperature greater than or equal to 200 ℃ and less than or equal to 450 ℃, so that the CuN in the TixCuyN is also decomposed to form the TiN Cu graded layer 92. Similarly, a TaN Cu graded layer 92 may be formed.
Due to the graded layer 92, the interface connectivity between the subsequently formed seed layer 7 and the barrier layer 8 may be improved, thereby reducing contact resistance and improving the electrical performance of the device.
The graded layer 92 may have a thickness of greater than or equal to 1nm and less than or equal to 5nm; the graded layer 92 may be formed by sputtering a target material of an alloy (for example, tiCu alloy), or by introducing an atmosphere containing Ti or Ta into the reaction chamber during the sputtering process using a Cu target material, and reacting the reaction chamber with the surface of the substrate 1 to form a TixCuyN layer or a taxouyn layer.
In another possible embodiment, after forming the composite metal nitride layer 91, the metal nitride layer is further deposited and formed, followed by forming the graded layer 92 and the seed layer 7 by a one-step heating process.
For example, the formed composite metal nitride layer 91 may be a TixCuyN layer or a txcuyn layer, the formed metal nitride layer is a copper nitride layer, after forming the TixCuyN layer and the copper nitride layer, or forming the txcuyn layer and the copper nitride layer, heat treatment is performed at a temperature ranging from 200 ℃ to 450 ℃ in vacuum, and in the one-step heating process, the copper nitride layer is thermally decomposed to form a pure metal copper seed layer, the TixCuyN layer is thermally decomposed to form a TiN Cu graded layer 92, or the txcuyn layer is thermally decomposed to form a TaN Cu graded layer 92. The formation of the graded layer 92 and the seed layer 7 is realized through a one-step heating process, so that the manufacturing process is simplified, the energy consumption in the actual manufacturing process is greatly reduced, and the production cost is saved. Moreover, the compactness of the copper seed layer 7 formed by thermal decomposition and the coverage of the inner wall of the channel are good, the subsequent electroplating is facilitated to rapidly deposit a copper metal main body layer, and the conductivity of the interconnection structure is effectively ensured.
In one possible implementation manner, in an embodiment of the present application, referring to fig. 12, which is a schematic diagram of still another semiconductor structure provided in an embodiment of the present application, a method provided in an embodiment of the present application may further include: depositing a repair layer 71 on a side of the seed layer 7 remote from the substrate 1 under radio frequency bias of a first power; the first power is greater than or equal to 120W and less than or equal to 200W.
That is, since damage may be caused to the film layer during the removal of the overhang 4 by plasma etching, a thin repair layer 71 may be deposited to repair the film layer defect caused during the plasma etching, thereby improving the reliability of the device.
Finally, the body layer 72 is deposited by electroplating on the side of the repair layer 71 away from the substrate 1 in the channel 31, so that the channel 31 is completely filled, and the subsequent formation of the interconnection structure is facilitated. Specifically, as shown in fig. 12, the copper metal formed by electroplating fills the remaining space of the via 31 and covers the surface of the repair layer 71. Then flattening the formed structure by utilizing a Chemical Mechanical Polishing (CMP) process, and polishing to remove the redundant film structure above the dielectric layer 2; the film structure above the dielectric layer 2 comprises: barrier layer 8, graded layer 92, seed layer 7, repair layer 71 and bulk layer 72; after CMP removes these film structures, the remaining barrier layer 8, graded layer 92, seed layer 7, repair layer 71 and bulk layer 72 within channel 31 collectively form an interconnect structure, as shown in fig. 13.
The embodiment of the application provides a preparation method of a semiconductor structure, the density of a metal nitride layer formed through magnetron sputtering is smaller than that of corresponding pure metal, the step coverage performance of the metal nitride layer is better than that of the corresponding pure metal, overhang formed at a channel opening is smaller than that formed by traditional metal, and therefore when etching is performed by utilizing argon plasma, overhang of the opening is more convenient to remove, overhang removal efficiency is improved, the opening is increased, further, the channel can be completely filled by subsequent electroplated metal, and defects such as cavity formation in an interconnection structure are avoided.
Referring to fig. 13, fig. 13 is a schematic diagram of a semiconductor structure according to an embodiment of the present application, including:
the substrate 1 and the dielectric layer 2 located on one side of the substrate 1, the dielectric layer 2 comprises at least one channel 31 penetrating the dielectric layer 2, and the channel 31 exposes the surface of the substrate 1.
An interconnect structure filling the channel 31; the interconnection structure comprises: barrier layer 8, graded layer 92 and conductive layer, the conductive layer including seed layer 7, repair layer 71 and bulk layer 72; the barrier layer 8 covers the inner walls of the channels 31 and the exposed surface of the substrate 1, and the graded layer 92 is located between the barrier layer 8 and the conductive layer;
wherein the barrier layer 8 includes a first metal element, the conductive layer includes a second metal element, the graded layer 92 includes the first metal element and the second metal element, and the content of the second metal element in the graded layer 92 is greater than the content of the first metal element. In this embodiment, the second metal element may be copper element, the first metal element may be titanium element or tantalum element, the barrier layer 8 may be TiN or TaN, the graded layer 92 may be a composite metal layer of tin×cu or tan×cu, the seed layer 7 and the repair layer 71 may be pure copper metal layers, and the body layer 71 may be pure copper metal layers formed by electroplating deposition.
The barrier layer 8 provided by the embodiment of the application can prevent the material of the subsequent magnetron sputtering from diffusing into the substrate 1, and also prevent impurities in the substrate 1 from diffusing into the film structure of the subsequent deposition, so that the reliability of the device structure is ensured.
Due to the existence of the graded layer 92, the content of the second metal element in the graded layer 92 is larger than that of the first metal element, so that the interface connectivity between the subsequently formed seed layer 7 and the barrier layer 8 can be improved, the contact resistance is reduced, and the electrical performance of the device is improved.
The seed layer 7 deposited according to the embodiments of the present application can ensure the conduction of the cathode current during the subsequent electroplating, so that the bulk layer 72 is subsequently deposited in large quantities.
Meanwhile, in the embodiment of the application, the repair layer 71 can repair the film layer defect caused in the plasma etching process, so that the reliability of the device is improved, and a large amount of subsequent main body layers can be deposited. In this embodiment, in order to reduce the influence of overhang formed at the opening position of the interconnect channel in the film deposition process, an argon ion etching manner is adopted, after the precursor layer (copper nitride layer) of the seed layer (copper metal layer) is deposited, plasma etching is performed on overhang formed at the opening position, partial damage of the precursor layer may be caused in the etching process, especially, the precursor layer formed on the side wall of the channel may be thinned or even broken by plasma etching, and these damage sites still exist when the seed layer is formed by heat treatment of the subsequent precursor layer, so that deposition of the copper main layer may be affected in the electroplating process, and bad defects are formed in the interconnect structure. Therefore, after the copper seed layer is formed, a copper repair layer 71 is deposited, and damage sites generated in the suspension process due to argon ion etching are repaired by using the repair layer 71, so that the inner wall of the interconnection channel can be completely covered by copper metal, smooth proceeding of the subsequent electroplating deposition of the copper main body layer is ensured, and void defects in the interconnection structure are avoided.
In one possible implementation, referring to fig. 13, the content of the first element in the graded layer 92 gradually decreases and the content of the second element in the graded layer 92 gradually increases along the direction in which the barrier layer 8 is directed toward the conductive layer.
Thus, gradual change from the barrier layer 8 to the conductive layer can be realized, and interface connectivity between the conductive layer and the barrier layer 8 can be improved, so that contact resistance is reduced, and electrical performance of the device is improved.
Alternatively, the graded layer 92 is a composite metal layer comprising a nitride formed of a first metal element and a pure metal formed of a second metal element. So as to further improve the interfacial connectivity between the barrier layer 8 and the conductive layer. In this embodiment, the graded layer 92 is located between the barrier layer 8 and the seed layer 7, and the graded layer may be tin×cu or tan×cu, where the content of Ti element or Ta element in the graded layer close to the barrier layer 8 is higher, and the content of Cu element in the graded layer close to the seed layer 7 is higher, so that the interface connection performance between the barrier layer and the seed layer is improved through the transition effect of the graded layer, the problem of poor interface connection caused by direct contact between the TiN or TaN barrier layer and the Cu seed layer is avoided, and the overall conductivity of the interconnection structure is improved.
In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for structural embodiments, since they are substantially similar to method embodiments, the description is relatively simple, and reference is made to the description of method embodiments for relevant points.
The foregoing is merely a preferred embodiment of the present application, and although the present application has been disclosed in the preferred embodiment, it is not intended to limit the present application. Any person skilled in the art may make many possible variations and modifications to the technical solution of the present application, or modify equivalent embodiments, using the methods and technical contents disclosed above, without departing from the scope of the technical solution of the present application. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present application, which do not depart from the content of the technical solution of the present application, still fall within the scope of the technical solution of the present application.
Claims (10)
1. A method of fabricating a semiconductor structure, comprising:
providing a substrate;
forming a dielectric layer on one side of the substrate;
etching the dielectric layer to form a channel penetrating through the dielectric layer so as to expose the surface of the substrate;
forming a copper nitride layer on the inner wall of the channel, the exposed surface of the substrate and one side of the dielectric layer far away from the substrate by magnetron sputtering target materials in a nitrogen atmosphere;
plasma etching the copper nitride layer to remove overhang of the copper nitride layer formed at the opening of the channel;
performing heating decomposition on the copper nitride layer to remove nitrogen element in the copper nitride layer, so as to form a seed layer;
and forming a repair layer and a main body layer on one side of the seed layer, which is far away from the substrate, in sequence, wherein the seed layer, the repair layer and the main body layer form a conductive layer of an interconnection structure.
2. The method of claim 1, further comprising, after etching the dielectric layer to form a channel through the dielectric layer, prior to magnetron sputtering the target under a nitrogen atmosphere:
forming a barrier layer on the inner wall of the channel, the exposed surface of the substrate and one side of the dielectric layer away from the substrate; the material of the barrier layer comprises: at least one of titanium, tantalum, titanium nitride and tantalum nitride.
3. The method of claim 2, wherein the barrier layer comprises a first metallic element and the target comprises a copper element;
after forming the barrier layer, before forming the copper nitride layer, further comprising:
forming a composite metal nitride layer by magnetron sputtering of an intermediate target in a nitrogen atmosphere; the intermediate target includes the first metal element and the copper element.
4. A method according to claim 3, wherein the copper element is present in the composite metal nitride layer in an amount greater than the first metal element.
5. The method of claim 3, further comprising, after forming the composite metal nitride layer:
and carrying out heating decomposition on the composite metal nitride layer to form a graded layer.
6. The method of any one of claims 1-5, wherein forming the repair layer comprises: depositing a repair layer on a side of the seed layer away from the substrate under a radio frequency bias of a first power; the first power is greater than or equal to 120W and less than or equal to 200W.
7. The method of any one of claims 1-5, wherein forming the bulk layer comprises: and electroplating and depositing a main body layer on one side of the repair layer, which is far away from the substrate, in the channel, wherein the main body layer fills the channel.
8. A semiconductor structure prepared by the method of claim 1, the structure comprising:
the substrate and the dielectric layer is positioned on one side of the substrate, the dielectric layer comprises at least one channel penetrating through the dielectric layer, and the channel exposes the surface of the substrate;
an interconnect structure filling the channel; the interconnect structure includes: the device comprises a barrier layer, a gradual change layer and a conductive layer, wherein the conductive layer comprises a seed layer, a repair layer and a main body layer; the barrier layer covers the inner wall of the channel and the exposed surface of the substrate, and the gradual change layer is positioned between the barrier layer and the conductive layer;
the barrier layer comprises a first metal element, the conductive layer comprises a copper element, the graded layer comprises the first metal element and the copper element, and the content of the copper element in the graded layer is larger than that of the first metal element.
9. The structure according to claim 8, wherein a content of the first metal element in the gradation layer gradually decreases and a content of the copper element in the gradation layer gradually increases along a direction in which the barrier layer is directed toward the conductive layer.
10. The structure according to claim 8 or 9, wherein the graded layer is a composite metal layer comprising a nitride formed of the first metal element and a pure metal formed of the copper element.
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