CN116151186A - Time sequence optimization method and device and electronic equipment - Google Patents
Time sequence optimization method and device and electronic equipment Download PDFInfo
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Abstract
The embodiment of the disclosure provides a time sequence optimization method, which comprises the following steps: performing static time sequence analysis on the integrated circuit, and acquiring a path to be processed in the integrated circuit; determining a wire net to be processed based on the path to be processed, the wire net to be processed comprising wire nets present on the path to be processed; load isolation is carried out on the loads in each wire network to be processed, wherein the load isolation comprises load classification processing on the loads in the wire network to be processed, classification results comprise critical loads and non-critical loads, and buffer units are added around the non-critical loads; the load classification processing comprises the steps of trying different load marking schemes, estimating time delay change conditions of each marking result, and taking the optimal scheme to classify the load. By the processing scheme, the timing sequence convergence efficiency on the critical path can be improved.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a load mask-based timing optimization method, and more particularly, to a load mask-based timing optimization method, apparatus, and electronic device.
Background
Timing is a key element in an integrated circuit, and the integrated circuit can work normally only when the timing requirement is met, and timing optimization is particularly important in the field of physical design automation of very large scale integrated circuits.
An important method for optimizing the timing characteristics is to reduce the fan-out number on a critical path, and the traditional fan-out optimization aims at the problem of high fan-out in a circuit, such as having tens, hundreds and even more load number nets, generally, loads are divided into a plurality of groups by using some constraints as classification basis (such as position information, capacitance and resistance on the wire net and the like) through a clustering algorithm, and new buffering is added to drive the load, so that the effect of reducing the high fan-out is achieved. Such high fan-out optimization is typically a global optimization, considering that the higher fan-out nets in the circuit do not take into account the timing path that the current net is in. Obviously, for fan-out optimization on critical paths, the benefit is higher than for fan-out optimization on non-critical paths.
Based on this, the conventional fan-out optimization method has the problem of low timing convergence efficiency on a critical path, and a method capable of efficiently optimizing the timing characteristics of a circuit is needed.
Disclosure of Invention
In view of this, embodiments of the present disclosure provide a load mask-based timing optimization method, which at least partially solves the problems in the prior art.
According to an aspect of the disclosed embodiments, there is provided a timing optimization method applied to an integrated circuit, including:
performing static time sequence analysis on the integrated circuit, and acquiring a path to be processed in the integrated circuit;
determining a wire net to be processed based on the path to be processed, the wire net to be processed comprising wire nets present on the path to be processed;
load isolation processing is carried out on the load in each wire network to be processed, and the load isolation processing comprises the following steps of
Carrying out load classification processing on loads in the network to be processed, wherein classification results comprise critical loads and non-critical loads,
buffer units are added around the non-critical load.
According to a specific implementation manner of the embodiment of the present disclosure, the load classification processing for the load in the network to be processed further includes:
initializing a marking scheme, comprising obtaining timing margin of all loads in a network to be processed, marking the load with the smallest timing margin as a critical load, marking other loads as non-critical loads,
in the current marking scheme, after the buffer units are added around the non-critical loads, the time delay change condition from a driving unit to each load in the network to be processed is estimated, and the time delay change condition is recorded;
updating a marking scheme, namely changing the marking of the load with the smallest timing margin in the currently marked non-critical loads into a critical load, and repeating the step until the marking results of all the loads in the network to be processed are the critical loads;
comparing the time delay change conditions recorded in each marking scheme, and adding buffer units around the non-critical load based on the buffer unit addition condition when the time delay change condition is minimum.
According to a specific implementation manner of the embodiment of the present disclosure, before performing load isolation processing on the load in each of the to-be-processed nets, the method further includes:
acquiring the frequency of the wire network to be processed on the path to be processed;
sorting the wire nets to be processed based on the number of times the wire nets to be processed appear on the path to be processed;
and determining the sequence of carrying out load isolation processing on the loads in each wire network to be processed based on the sequencing result.
According to a specific implementation manner of the embodiment of the present disclosure, the sorting the loads in the to-be-processed wire network includes:
acquiring a timing margin on a path of each load in the network to be processed;
and sorting the loads from small to large based on the timing margin of the path of each load, wherein the smaller the timing margin of the load is, the earlier the sorting is.
According to a specific implementation of an embodiment of the disclosure, in estimating the current marking scheme, before adding the buffer unit around the non-critical load, the method includes:
calculating a minimum spanning tree of a driving unit and a non-critical load of the wire network, wherein the minimum spanning tree comprises the steps of taking coordinates of the driving unit as a root node position, taking coordinates of the non-critical load as leaf node positions, and constructing a minimum Manhattan distance spanning tree;
and taking the Steiner point of the minimum spanning tree as a candidate position to determine the position of the buffer unit in the wire net to be processed.
According to a specific implementation manner of the embodiment of the present disclosure, the adding a buffer unit around the non-critical load further includes:
clustering the non-critical loads according to different numbers of coordinate positions, wherein the number of clusters is smaller than 4;
and comparing the contour coefficients of different number of clustering schemes, and taking the scheme with the minimum contour coefficient as the optimal number of clustering schemes.
According to a specific implementation manner of the embodiment of the present disclosure, the adding a buffer unit around the non-critical load further includes:
traversing the addition results using different types of buffer cells in a process library, including
For each different buffer unit type of attempt, firstly estimating the delay variation of the buffer unit after adding according to the positions corresponding to the non-critical load and the buffer unit to be placed;
and selecting the buffer unit type with the smallest delay change after the buffer unit is added as the buffer unit type added around the non-critical load.
According to a specific implementation manner of the embodiment of the present disclosure, the load isolation processing for the load in each of the to-be-processed nets further includes:
performing time sequence updating on the processed circuit;
and performing static time sequence analysis processing on the circuit subjected to time sequence updating to obtain a processing result.
In a second aspect, embodiments of the present disclosure provide a timing optimization apparatus, including a timing optimization method according to the first aspect of the present disclosure or any implementation manner thereof.
In a third aspect, an embodiment of the present disclosure provides an electronic device, including a timing optimization method according to the first aspect of the present disclosure or any implementation manner thereof, or including a timing optimization apparatus according to the second aspect of the present disclosure.
The embodiment of the disclosure provides a time sequence optimization method, which comprises the following steps: performing static time sequence analysis on the integrated circuit, and acquiring a path to be processed in the integrated circuit; determining a wire net to be processed based on the path to be processed, the wire net to be processed comprising wire nets present on the path to be processed; carrying out load isolation processing on the loads in each wire network to be processed, wherein the load isolation processing comprises classifying the loads in the wire network to be processed, the classification result comprises a critical load and a non-critical load, and buffer units are added around the non-critical load; the load classification processing comprises the steps of trying different load marking schemes, estimating time delay change conditions of each marking result, and taking the optimal scheme to classify the load. By the processing scheme, the timing sequence convergence efficiency on the critical path can be improved, and the timing sequence optimization effect is more obvious.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.
Fig. 1 is a schematic flow chart of a timing optimization method according to an embodiment of the disclosure;
FIG. 2 is a flow chart of another timing optimization method according to an embodiment of the disclosure;
fig. 3 is a schematic diagram of buffer unit clustering of a timing optimization method according to an embodiment of the disclosure.
Detailed Description
Embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
Other advantages and effects of the present disclosure will become readily apparent to those skilled in the art from the following disclosure, which describes embodiments of the present disclosure by way of specific examples. It will be apparent that the described embodiments are merely some, but not all embodiments of the present disclosure. The disclosure may be embodied or practiced in other different specific embodiments, and details within the subject specification may be modified or changed from various points of view and applications without departing from the spirit of the disclosure. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. All other embodiments, which can be made by one of ordinary skill in the art without inventive effort, based on the embodiments in this disclosure are intended to be within the scope of this disclosure.
It is noted that various aspects of the embodiments are described below within the scope of the following claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the present disclosure, one skilled in the art will appreciate that one aspect described herein may be implemented independently of any other aspect, and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number of the aspects set forth herein. In addition, such apparatus may be implemented and/or such methods practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should also be noted that the illustrations provided in the following embodiments merely illustrate the basic concepts of the disclosure by way of illustration, and only the components related to the disclosure are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided in order to provide a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details.
Description of the partial concepts:
the embodiment of the disclosure is mainly applied to the technical field of very large scale integrated circuit (VLSI) physical design automation.
Static timing analysis: all time sequence paths existing in the whole circuit are obtained by adopting an exhaustive analysis method, the propagation delay of signals on the paths is calculated, whether the set-up time and the hold time of the signals meet the time sequence requirement is checked, and a method for violating the time sequence constraint errors is found out by analyzing the maximum and minimum path delays.
Time margin: the actual arrival time of the timing path data signal minus the required arrival time of the data signal is referred to as the time margin (slot), with a path time margin less than 0 representing a timing violation.
Timing critical path: the collection of paths with poor time margin in all time sequence paths of the circuit is generally used for representing the lower limit of time sequence characteristics in the whole circuit, the time sequence critical path directly influences the working frequency of the circuit, and the smaller the time margin value of the time sequence critical path is, the lower the highest frequency of the circuit is.
Key load: all loads in the net with timing margin values below the standard timing margin.
Number of clusters: the newly added buffer drives the load number.
Profile coefficient: and evaluating the index of the clustering effect, wherein the value range is [ -1,1], and the closer to 1, the better the clustering effect is indicated. The formula is as follows:
wherein a (i) is the average distance between i and other sample points in the cluster to which i belongs; b (i) is the minimum of the average distance of i from the samples of the other clusters.
Manhattan distance minimum spanning tree: given some points of a two-dimensional plane, the spanning tree with the shortest manhattan distance is formed after all points are connected.
In order to make the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
First, referring to fig. 1, fig. 1 is a flow chart of a timing optimization method according to an embodiment of the disclosure, including:
and step 101, performing static time sequence analysis on the integrated circuit and acquiring a path to be processed in the integrated circuit.
It is easy to understand that, compared with the conventional technology, for performing high fan-out optimization on the global, the embodiment of the disclosure starts from the fan-out optimization of the critical path, and compared with the non-critical path, the net on the critical path is generally more sensitive to the number of fan-outs, and the time sequence of the whole critical path is possibly greatly deteriorated by increasing the fan-out of some nets; in turn, reducing the fan-out of the net, the critical paths can typically be significantly optimized, even to achieve timing closure effects. Therefore, the embodiment starts from the critical path, and performs fan-out optimization on the wire net on the critical path, so that the optimization efficiency of the circuit time sequence characteristic can be effectively improved. In the disclosed embodiment, static timing analysis is performed on an integrated circuit first, and a path to be processed in the circuit, that is, a critical path to be subjected to timing optimization in the disclosed embodiment, can be obtained.
It will be appreciated that the net present on the critical path can directly affect the timing characteristics of the critical path, and thus the net to be processed is the net present on the path to be processed.
And 103, carrying out load isolation processing on the load in each wire network to be processed.
Load isolation processing is performed on all loads in the network to be processed, and the embodiment improves the time sequence characteristic by performing load isolation processing on the critical path. In this embodiment, load isolation processing is required for each net to be processed.
The core strategy for load isolation is: the connection of critical loads is kept unchanged, and non-critical loads are driven by adding new buffers to reduce the fanout of the net.
The load isolation process, i.e., separating critical loads in the critical path.
The load isolation process includes:
In this embodiment, a greedy strategy is mainly adopted, and first, the critical load and the non-critical load are classified and correspondingly marked. In different embodiments, the classification criteria for the critical load and the non-critical load are different, so that in this embodiment, no excessive limitation is made, and only the load needs to be classified into the critical load and the non-critical load by a certain rule.
In this step, the buffer units are added around the non-critical load, that is, new buffer units are added to drive the non-critical load, that is, the fan-out of the net can be reduced, that is, the timing optimization of the net corresponding to the critical path is achieved.
In one embodiment, as shown in fig. 2, fig. 2 is a flow chart of another timing optimization method provided in an embodiment of the disclosure. As shown, before adding the buffer unit around the non-critical load, further comprising:
And step 303, updating a marking scheme, namely changing the marking of the load with the smallest timing margin in the currently marked non-critical loads into a critical load, and repeating the step until the marking results of all the loads in the network to be processed are the critical loads.
And step 304, comparing the time delay change conditions recorded in each marking scheme, and adding buffer units around the non-critical load based on the buffer unit addition condition when the time delay change condition is minimum.
In this embodiment, it is necessary to determine an optimal solution to add buffer units around non-critical loads; it is easy to understand that the embodiment adopts a greedy strategy, calculates the time delay change conditions after buffer units are added around different numbers of non-critical loads by calculating the combination of the plurality of critical loads and the non-critical loads, and records each time delay change condition as a solution of each load isolation. And then the solution with the minimum time delay variation is used as the optimal solution of load isolation. If the time delay change is negative, namely the circuit time sequence is poor after load isolation, the method indicates that load isolation cannot be carried out, and if the time delay change is not negative, a solution with the minimum time delay change is taken as an optimal solution of load isolation.
In another embodiment of the present disclosure, before performing load isolation processing on the load in each of the networks to be processed, the method further comprises: acquiring the number of times of the wire network to be processed on a path to be processed; sorting the wire nets to be processed based on the number of times the wire nets to be processed appear on the paths to be processed; based on the sequencing result, the order of carrying out load isolation processing on the loads in each wire network to be processed is determined.
In this embodiment, since the load isolation process is required for each of the loads in the net to be processed in step 103, and in the general embodiment, the processes of the nets to be processed are required to be performed in a certain order, the process order of the nets to be processed is specified in this embodiment. It can be appreciated that the higher the number of occurrences of the net on the critical path, the more frequently it has a higher impact on the critical path timing optimization. Therefore, in this embodiment, the main factors for the net sequencing weights are: the number of times the net to be processed appears on all critical paths. And then, carrying out load isolation processing on the load in each wire net to be processed based on the sequence of the sequencing result.
In one embodiment of the present disclosure, ordering loads in a net to be processed includes: and sorting the loads from small to large based on the timing margin of the path of each load, wherein the smaller the timing margin of the load is, the earlier the sorting is.
In this embodiment, the standard for ordering the load marks is a timing margin, and it is easy to understand that, in the scope of understanding of the ordinary skilled person, the lower the timing margin, the greater the influence of modifying the connection relationship of the load on the net, the more critical the net, and the less space is optimized for the load. Based on this, the present embodiment first obtains the timing margin on the path where each load in the present network is located, and then, based on the timing margin on the path where each load is located, the smaller the timing margin, the higher the rank of the load.
In one embodiment of the present disclosure, in estimating the current signature scheme, before adding the buffer units around the non-critical load, comprising: calculating a minimum spanning tree of a driving unit and a non-critical load of the wire network, wherein the minimum spanning tree comprises the steps of taking coordinates of the driving unit as a root node position, taking coordinates of the non-critical load as leaf node positions, and constructing a minimum Manhattan distance spanning tree; and taking the Steiner point of the minimum spanning tree as a candidate position to determine the position of the buffer unit in the wire net to be processed.
In this embodiment, each buffer drives which loads have been determined. And constructing a Manhattan distance minimum spanning tree by taking the coordinates of a driving unit of the wire net as a root node position and the coordinates of non-critical loads as leaf node positions, and on the basis of the Manhattan distance minimum spanning tree, ensuring that the whole wire length is minimum by constructing the Manhattan distance minimum spanning tree. In the calculation result of the Manhattan distance minimum spanning tree, the buffer unit is placed at the Steiner branching point nearest to the driving unit.
In one embodiment of the present disclosure, the adding a buffer unit around the non-critical load further includes: clustering the non-critical loads according to different numbers of coordinate positions, wherein the number of clusters is smaller than 4; and comparing the contour coefficients of different number of clustering schemes, and taking the scheme with the minimum contour coefficient as the optimal number of clustering schemes.
As shown in fig. 3, fig. 3 is a schematic diagram of buffer unit clustering of the timing optimization method according to an embodiment of the disclosure. In the present embodiment, the number of clusters is determined to be optimal by evaluating the contour coefficient, or is set to 4 or below, for example: 1. 2, 3, based on which the problem of overlarge output capacitance of the buffer units caused by too dispersed load driven by the newly added single buffer unit can be avoided to a great extent.
In one embodiment of the present disclosure, the adding a buffer unit around the non-critical load further includes: and traversing the adding results of the buffer units of different types in the process library, wherein the adding results comprise the attempt of each different buffer unit type, firstly estimating the time delay change of the buffer units after adding according to the positions corresponding to the non-critical load and the buffer units to be placed, and selecting the buffer unit type with the minimum time delay change after adding the buffer units as the buffer unit type added around the non-critical load.
It will be appreciated that buffer units are of different types, with different types of buffer units having different latency effects on non-critical loads for different non-critical loads. Based on the above, it is necessary to traverse the addition results of different types of buffer units in the process library, compare the different addition results, and select the buffer unit type corresponding to the addition result with the smallest time delay variation.
In another embodiment of the present disclosure, performing load isolation processing on the load in each of the nets to be processed further comprises: performing time sequence updating on the processed circuit; and performing static time sequence analysis processing on the circuit subjected to time sequence updating to obtain a processing result.
It is easy to understand that in this embodiment, after load isolation processing is performed on each net to be processed, a timing report of the modified netlist needs to be obtained to verify the timing optimization result, so that the processed circuit needs to be updated in timing first, and then static timing analysis processing is performed on the processed integrated circuit to obtain the processing result of this time.
Based on the above embodiments of the present disclosure, there are several advantages over existing fan-out optimization based techniques:
1) The run time is shorter. Compared with high fan-out optimization of global scanning, the method only considers the critical path, and the processed net is smaller in scale, so that the running time is shorter.
2) The optimization effect is more obvious. The timing characteristics on the critical paths are more sensitive to the number of fan-outs, and particularly, the net with higher occurrence frequency on the critical paths has larger profit after optimization, which is equal to the optimization of a plurality of critical paths at the same time.
Furthermore, as can be appreciated by those skilled in the art, the timing optimization method according to the present disclosure may be used for timing optimization of an integrated circuit or electronic device. The electronic devices include, but are not limited to, intermediate products such as a radio frequency front end and a filtering and amplifying module, terminal products such as a mobile phone, a WIFI and an unmanned aerial vehicle, or other communication device products such as a communication base station and a router.
Based on the above, the embodiments of the present disclosure propose the following schemes:
1. a timing optimization method for an integrated circuit, comprising:
performing static time sequence analysis on the integrated circuit, and acquiring a path to be processed in the integrated circuit;
determining a wire net to be processed based on the path to be processed, the wire net to be processed comprising wire nets present on the path to be processed;
load isolation processing is carried out on the load in each wire network to be processed, and the load isolation processing comprises the following steps of
Carrying out load classification processing on loads in the network to be processed, wherein classification results comprise critical loads and non-critical loads,
buffer units are added around the non-critical load.
2. The time sequence optimizing method according to 1, wherein the load classifying processing for the load in the network to be processed further comprises:
initializing a marking scheme, comprising obtaining timing margin of all loads in a network to be processed, marking the load with the smallest timing margin as a critical load, marking other loads as non-critical loads,
in the current marking scheme, after the buffer units are added around the non-critical loads, the time delay change condition from a driving unit to each load in the network to be processed is estimated, and the time delay change condition is recorded;
updating a marking scheme, namely changing the marking of the load with the smallest timing margin in the currently marked non-critical loads into a critical load, and repeating the step until the marking results of all the loads in the network to be processed are the critical loads;
comparing the time delay change conditions recorded in each marking scheme, and adding buffer units around the non-critical load based on the buffer unit addition condition when the time delay change condition is minimum.
3. The time sequence optimizing method according to 1, before the load isolation processing is performed on the load in each wire network to be processed, further comprising:
acquiring the frequency of the wire network to be processed on the path to be processed;
sorting the wire nets to be processed based on the number of times the wire nets to be processed appear on the path to be processed;
and determining the sequence of carrying out load isolation processing on the loads in each wire network to be processed based on the sequencing result.
4. The timing optimization method according to 2, wherein the marking the load in the net to be processed comprises:
acquiring a timing margin on a path of each load in the network to be processed;
and sorting the loads from small to large based on the timing margin of the path of each load, wherein the smaller the timing margin of the load is, the earlier the sorting is.
5. The timing optimization method according to claim 2, wherein in estimating the current marking scheme, before adding the buffer units around the non-critical load, the method comprises:
calculating a minimum spanning tree of a driving unit and a non-critical load of the wire network, wherein the minimum spanning tree comprises the steps of taking coordinates of the driving unit as a root node position, taking coordinates of the non-critical load as leaf node positions, and constructing a minimum Manhattan distance spanning tree;
and taking the Steiner point of the minimum spanning tree as a candidate position to determine the position of the buffer unit in the wire net to be processed.
6. The timing optimization method according to 2, wherein adding a buffer unit around the non-critical load further comprises:
clustering the non-critical loads according to different numbers of coordinate positions, wherein the number of clusters is smaller than 4;
and comparing the contour coefficients of different number of clustering schemes, and taking the scheme with the minimum contour coefficient as the optimal number of clustering schemes.
7. The timing optimization method according to 2, wherein the adding the buffer unit around the non-critical load further comprises:
traversing the addition results using different types of buffer cells in a process library, including
For each different buffer unit type of attempt, firstly estimating the delay variation of the buffer unit after adding according to the positions corresponding to the non-critical load and the buffer unit to be placed;
and selecting the buffer unit type with the smallest delay change after the buffer unit is added as the buffer unit type added around the non-critical load.
8. The time sequence optimizing method according to 1, wherein the load isolation processing for the load in each wire network to be processed further comprises:
performing time sequence updating on the processed circuit;
and performing static time sequence analysis processing on the circuit subjected to time sequence updating to obtain a processing result.
9. A timing optimization apparatus comprising the timing optimization method according to any one of claims 1 to 8.
10. An electronic device comprising the timing optimization method according to any one of claims 1 to 8 or comprising the timing optimization apparatus according to claim 9.
The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the disclosure are intended to be covered by the protection scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (10)
1. A timing optimization method for an integrated circuit, comprising:
performing static time sequence analysis on the integrated circuit, and acquiring a path to be processed in the integrated circuit;
determining a wire net to be processed based on the path to be processed, the wire net to be processed comprising wire nets present on the path to be processed;
load isolation processing is carried out on the load in each wire network to be processed, and the load isolation processing comprises the following steps of
Carrying out load classification processing on loads in the network to be processed, wherein classification results comprise critical loads and non-critical loads,
buffer units are added around the non-critical load.
2. The timing optimization method of claim 1, wherein the load classification process for the load in the net to be processed further comprises:
initializing a marking scheme, comprising obtaining timing margin of all loads in a network to be processed, marking the load with the smallest timing margin as a critical load, marking other loads as non-critical loads,
in the current marking scheme, after the buffer units are added around the non-critical loads, the time delay change condition from a driving unit to each load in the network to be processed is estimated, and the time delay change condition is recorded;
updating a marking scheme, namely changing the marking of the load with the smallest timing margin in the currently marked non-critical loads into a critical load, and repeating the step until the marking results of all the loads in the network to be processed are the critical loads;
comparing the time delay change conditions recorded in each marking scheme, and adding buffer units around the non-critical load based on the buffer unit addition condition when the time delay change condition is minimum.
3. The timing optimization method of claim 1, wherein before performing load isolation processing on the load in each of the nets to be processed, further comprises:
acquiring the frequency of the wire network to be processed on the path to be processed;
sorting the wire nets to be processed based on the number of times the wire nets to be processed appear on the path to be processed;
and determining the sequence of carrying out load isolation processing on the loads in each wire network to be processed based on the sequencing result.
4. The timing optimization method of claim 2, wherein the ordering the loads in the net to be processed comprises:
acquiring a timing margin on a path of each load in the network to be processed;
and sorting the loads from small to large based on the timing margin of the path of each load, wherein the smaller the timing margin of the load is, the earlier the sorting is.
5. The timing optimization method of claim 2, wherein in estimating a current signature scheme, before adding the buffer units around the non-critical load, comprises:
calculating a minimum spanning tree of a driving unit and a non-critical load of the wire network, wherein the minimum spanning tree comprises the steps of taking coordinates of the driving unit as a root node position, taking coordinates of the non-critical load as leaf node positions, and constructing a minimum Manhattan distance spanning tree;
and taking the Steiner point of the minimum spanning tree as a candidate position to determine the position of the buffer unit in the wire net to be processed.
6. The timing optimization method of claim 2, wherein adding buffer units around non-critical loads further comprises:
clustering the non-critical loads according to different numbers of coordinate positions, wherein the number of clusters is smaller than 4;
and comparing the contour coefficients of different number of clustering schemes, and taking the scheme with the minimum contour coefficient as the optimal number of clustering schemes.
7. The timing optimization method of claim 2, wherein the adding buffer units around non-critical loads further comprises:
traversing the addition results using different types of buffer cells in a process library, including
For each different buffer unit type of attempt, firstly estimating the delay variation of the buffer unit after adding according to the positions corresponding to the non-critical load and the buffer unit to be placed;
and selecting the buffer unit type with the smallest delay change after the buffer unit is added as the buffer unit type added around the non-critical load.
8. The timing optimization method of claim 1, wherein said load isolation processing of the load in each of said nets to be processed further comprises:
performing time sequence updating on the processed circuit;
and performing static time sequence analysis processing on the circuit subjected to time sequence updating to obtain a processing result.
9. A timing optimization apparatus, characterized by comprising the timing optimization method according to any one of claims 1 to 8.
10. An electronic device characterized by comprising the timing optimization method according to any one of claims 1-8 or comprising the timing optimization apparatus according to claim 9.
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| CN117113915A (en) * | 2023-10-25 | 2023-11-24 | 深圳鸿芯微纳技术有限公司 | Buffer insertion method and device and electronic equipment |
| CN117113915B (en) * | 2023-10-25 | 2024-02-02 | 深圳鸿芯微纳技术有限公司 | Buffer insertion method and device and electronic equipment |
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