CN116149918A

CN116149918A - AHB bus matrix-based test method and system

Info

Publication number: CN116149918A
Application number: CN202310424378.3A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Shanghai Mindmotion Microelectronics Co ltd
Current assignee: Shanghai Mindmotion Microelectronics Co ltd
Priority date: 2023-04-20
Filing date: 2023-04-20
Publication date: 2023-05-23
Anticipated expiration: 2043-04-20
Also published as: CN116149918B

Abstract

The invention discloses a test method and a test system based on an AHB bus matrix, wherein the method comprises the following steps: inputting functional information into a script, and generating a test case corresponding to the verification function point by the script according to the functional information; the method comprises the steps that a perfusion excitation module for generating a test case is operated to send excitation to a bus matrix and main equipment, and expected values are generated according to functional information; when the master device receives excitation, a write-read instruction and preset data are sent to the slave device through a bus matrix; when the slave device receives a write-read instruction, the preset data is returned to the master device; and comparing the data received by the slave device with the returned data received by the master device to obtain a detection result, and outputting a verification result according to the detection result and the expected value. The invention realizes the multifunctional verification of the bus matrix by controlling the bus matrix through the script, and the test cases are automatically generated by the script, thereby reducing the probability of human error, and the invention can also realize the update of the verification function point by modifying the input function information without redesigning the script, and saving the development cost.

Description

AHB bus matrix-based test method and system

Technical Field

The invention relates to the field of integrated circuit verification test, in particular to a test method and a test system based on an AHB bus matrix.

Background

With the increasing demands of people for consumer electronics, automotive electronics, etc., chips with high performance and high reliability are attracting attention in the industry. The AHB bus matrix can realize parallel transmission of data to increase bus bandwidth, greatly improve the efficiency of a bus system and become one of research hotspots in the technical field of current integrated circuits. The conventional AHB bus matrix only enables access of data, instructions, addresses between devices. Due to the development of chip technology, the electronic equipment continuously upgrades and updates the AHB bus matrix with more and more complex functions, and at present, the randomized verification method is still used in the industry for verifying the connectivity of the bus matrix and the priority of the main equipment, so that the method not only takes a long time and is only suitable for the bus matrix with a simple structure, but also has insufficient verification function points, and the success rate of one-time chip streaming is low. Therefore, there is a need for an efficient and widely applicable method and system for testing an AHB bus matrix with comprehensive verification function.

Disclosure of Invention

In order to solve the technical problems, the invention provides a test method and a test system based on an AHB bus matrix.

Specifically, the technical scheme of the invention is as follows:

in a first aspect, the present invention provides a test method based on an AHB bus matrix, including:

Inputting the function information of the master/slave device and the bus matrix into an automation script, and generating a test case corresponding to a verification function point by the automation script according to the function information of the master/slave device and the bus matrix; wherein, the verification function point includes: bus matrix connectivity verification, and/or master device priority verification, and/or default slave device verification, and/or synchronous frequency module verification, and/or remapping module verification, and/or virtual clock module verification;

running the test case to generate a priming excitation module, wherein the priming excitation module sends excitation to a bus matrix and a master device and generates an expected value according to the functional information of the master/slave device and the bus matrix;

when the bus matrix receives a write-read instruction, the bus matrix selects slave equipment corresponding to the address of the slave equipment according to the write-read instruction, and sends the write-read instruction and preset data to the slave equipment; the write-read instruction includes: the write instruction and the read instruction are sent to the bus matrix by the master device according to an AHB bus protocol when the master device receives the excitation;

when the slave device receives the writing instruction, the slave device takes the received preset data as master device data; when the slave device receives the reading instruction, preset data in the slave device are transmitted back to the master device through the bus matrix, and the transmitted back master device data are used as slave device data;

And obtaining a detection result according to the main equipment data and the auxiliary equipment data, and outputting a verification result according to a comparison result of the detection result and the expected value.

According to the method, the function information of the master/slave device and the bus matrix is input into the automation script to generate verification function points, so that the AHB bus matrix can flexibly verify a plurality of function points required in the verification process, then, through the perfusion excitation module, excitation is sent to different master/slave devices at different function verification points, different expected values are generated, and verification of corresponding function points is achieved by judging whether detection results of slave device data and master device data accord with the expected values or not.

In some embodiments of AHB bus matrix based test methods,

the functional information of the master/slave device and the bus matrix includes: master access rights, slave name, slave address, master priority, default slave address, master/slave connection to synchronous frequency module, master/slave connection to remapping module, master/slave connection to virtual clock module.

The embodiment provides the specific content of the functional information of the master device, the slave device and the bus matrix, and the functional information of the master device, the slave device and the bus matrix can be obtained through the automatic script of the specific content of the functional information, so that the automatic script can control the master device, the slave device and the bus matrix according to the functional information, and verification of the functional points is realized.

In some embodiments of the test method based on the AHB bus matrix, after obtaining a detection result according to the master device data and the slave device data and outputting a verification result according to a comparison result between the detection result and the expected value, the method further includes:

when the bus matrix connectivity verification is executed, the test case is a case that a single master device traverses all slave devices; according to the verification result, the perfusion excitation module randomly generates a plurality of random slave device addresses of which the master devices have the slave device access rights;

replacing the slave device in the previous step with a random slave device corresponding to the random slave device address, and writing the preset data into the random slave device by the master device to obtain slave device data and master device data;

and outputting a result of the bus matrix connectivity verification by analyzing whether the slave device data corresponding to the random slave device address is consistent with the master device data.

After the verification result is obtained, the slave device with the access right of the master device which is verified from the verification result extracts a plurality of random addresses from the slave device with the access right, writes preset data into the random addresses, compares whether the written and read data are consistent, and obtains a final bus matrix connectivity verification result, so that bus matrix connectivity verification in the functional point is realized, redundant verification on the slave device without the access right is avoided, and the time for connectivity verification is saved.

In some embodiments of the AHB bus matrix-based test method, the running the test case generates a priming stimulus module, where the priming stimulus module sends stimulus to a bus matrix and a master device, and generates a desired value according to functional information of the master/slave device and the bus matrix, including:

when the master device priority verification is executed, the test case is operated to generate the priming excitation module, the priming excitation module simultaneously sends the excitation to a bus matrix and a plurality of master devices, and an expected value of the master device priority is generated according to the master device priority in the functional information of the master/slave devices and the bus matrix; the test case is a case that a plurality of master devices access the same slave device;

and/or, when executing the default slave device verification, running the test case to generate the priming excitation module, wherein the priming excitation module randomly generates a plurality of default addresses according to the default slave device addresses in the function information of the master/slave device and the bus matrix, sends the excitation to the bus matrix and the master device, and generates expected values of default slave devices according to the default slave device addresses; wherein the test case is a case in which the master device accesses a default slave device address, which is an address that is not within the master/slave device range;

And/or, when the synchronous frequency verification is executed, running the test case to generate the priming excitation module, wherein the priming excitation module modifies frequency division/multiplication values of the master device and the slave device, sends the excitation to the bus matrix and the master device under different frequency division/multiplication values, and generates expected values under different frequency division/multiplication conditions according to connection conditions of the master/slave device and the synchronous frequency module in the functional information of the master/slave device and the bus matrix; wherein, the test case is a case of master/slave device communication under different frequencies;

and/or when the remapping module is verified, running the test case to generate the priming excitation module, sending the excitation to the bus matrix and the master device by the priming excitation module, and generating a remapping expected value according to the connection condition of the master/slave device and the remapping module in the function information of the master/slave device and the bus matrix; wherein the test case is a verification case of the remapping module;

and/or when executing the verification of the virtual clock module, running the test case to generate the perfusion excitation module, wherein the perfusion excitation module controls the virtual clock module of the bus matrix to be turned off and turned on, sends the excitation to the bus matrix and the master device respectively under the condition that the virtual clock module is turned off and turned on, and generates a virtual clock expected value according to the connection condition of the master/slave device and the virtual clock module in the function information of the master/slave device and the bus matrix; wherein the test case is a verification case of a virtual clock.

The present embodiment specifically describes the master/slave devices required for the test cases to excite the function points by the priming excitation module and generating the corresponding expected values when executing different verification function points.

In some embodiments of the AHB bus matrix-based test method, when the slave device receives the write command, the slave device uses the received preset data as master device data; when the slave device receives the read instruction, preset data in the slave device is returned to the master device through the bus matrix, and the returned master device data is used as slave device data, which comprises the following steps:

when the master device priority verification is executed, when the slave device corresponding to the slave device address receives the write instruction, the received preset data are used as master device data, and when the slave device receives the read instruction, the master device data are sequentially returned to the master device through the bus matrix according to the master device priority; the master device data which are returned in sequence are used as slave device data, and the sequence of the slave device data is consistent with the priority of the master device;

And/or, when the default slave device receives the write instruction while performing the default slave device verification, taking the received preset data as master device data; when the default slave device receives the reading instruction, the master device data is returned to the master device, and the master device takes the returned master device data as default slave device data;

and/or, when the slave device receives the write instruction, the slave device uses the received preset data as master device data, and when the slave device receives the read instruction, the master device data is returned to the master device through the bus matrix; the master device takes the returned master device data as slave device data;

and/or when the remapping module is used for verification, when the remapping slave device receives the writing instruction, the received preset data is used as master device data, and when the slave device receives the reading instruction, the master device data is returned to the master device through the bus matrix; and the master device uses the returned master device data as remapped slave device data.

When executing different verification function points, the embodiment returns different master device data as slave device data.

In some embodiments of the AHB bus matrix-based test method, the obtaining a detection result according to the master device data and the slave device data, and outputting the verification result according to a comparison result between the detection result and the expected value includes:

the verification result comprises a result of the master device priority verification, and/or a result of the default slave device verification, and/or a result of the synchronous frequency module verification, and/or a result of the remapping module verification, and/or a result of the virtual clock module verification;

when the master device priority verification is executed, a verification result under the condition of the current master device priority is obtained through comparing the sequence of the slave device data with the expected value of the master device priority; traversing all the master device priority cases to obtain a plurality of verification results, and outputting the master device priority verification results according to the verification results;

and/or, when executing the default slave device verification, obtaining a detection result according to the default slave device data and the master device data, and outputting a result of the default slave device verification according to a comparison result of the detection result and the expected value;

And/or, when the synchronous frequency verification is executed, obtaining a detection result according to the master device data and the slave device data, and outputting a result of the synchronous frequency module verification according to a comparison result of the detection result and the expected value;

and/or, when the remapping module verification is executed, obtaining a detection result according to the main equipment data and the remapping slave equipment data, and outputting a remapping module verification result according to a comparison result of the detection result and the expected value;

and/or when the virtual clock module verification is executed, obtaining a detection result according to the master device data and the slave device data, and outputting a result of the virtual clock module verification according to a comparison result of the detection result and the expected value.

When executing different verification function points, the embodiment executes different steps to compare results, and obtains verification results of the respective verification function points.

In a second aspect, the present invention provides an AHB bus matrix-based test system, comprising:

an information input unit, configured to input function information of the master/slave device and the bus matrix to the automation script, and send the function information of the master/slave device and the bus matrix to a use case generating unit and an expected value generating unit;

The use case generating unit is connected with the information input unit and is used for generating a test use case corresponding to a verification function point according to the function information of the master/slave equipment and the bus matrix by the automation script and sending the test use case to the excitation generating unit; wherein, the verification function point includes: bus matrix connectivity verification, and/or master device priority verification, and/or default slave device verification, and/or synchronous frequency module verification, and/or remapping module verification, and/or virtual clock module verification;

the excitation generation unit is connected with the use case generation unit and is used for running the test use case to generate a perfusion excitation module, and the perfusion excitation module sends excitation to the read-write unit and the expected value generation unit;

the expected value generating unit is connected with the information input unit and the excitation generating unit and is used for generating expected values according to the function information of the master/slave device and the bus matrix when the excitation is received;

the reading and writing unit comprises a main equipment reading and writing subunit, wherein the main equipment reading and writing subunit is used for sending a writing and reading instruction to the bus matrix subunit according to an AHB bus protocol when the excitation is received, and the writing and reading instruction comprises a writing instruction and a reading instruction;

The read-write unit further comprises the bus matrix subunit, wherein the bus matrix subunit is used for sending the write-read instruction and preset data to the slave device read-write subunit according to the slave device address when the write-read instruction is received;

the read-write unit further comprises a slave read-write subunit, wherein the slave read-write subunit is used for taking the received preset data as main equipment data when the write instruction is received, and transmitting the main equipment data back to the main equipment read-write subunit and the result analysis unit when the read instruction is received;

the master device read-write subunit is further configured to use the master device data returned by the slave device read-write subunit as slave device data, and send the slave device data to the result analysis unit;

the result analysis unit is used for analyzing and obtaining a detection result according to the master equipment data and the slave equipment data, and outputting a verification result according to a comparison result of the detection result and the expected value.

In some implementations of AHB bus matrix based test systems,

the excitation generating unit is further configured to operate the test case to generate the priming excitation module when the master device priority verification is performed, where the priming excitation module sends the excitation to a plurality of master devices and the bus matrix subunit in the master device read-write subunit simultaneously; the test case is a case that a plurality of master devices access the same slave device;

And/or when executing the verification of the default slave device, running the test case to generate the priming excitation module, wherein the priming excitation module randomly generates a plurality of default addresses according to the default slave device addresses in the function information of the master/slave device and the bus matrix, and sends the excitation to the master device and the bus matrix subunit in the master device read-write subunit; wherein the test case is a case in which the master device accesses a default slave device address, which is an address that is not within the master/slave device range;

and/or, when the synchronous frequency verification is executed, running the test case to generate the priming excitation module, wherein the priming excitation module modifies frequency division/multiplication values of the master device and the slave device, and the master device and the bus matrix subunit in the master device read-write subunit send the excitation under different frequency division/multiplication values; wherein, the test case is a case of master/slave device communication under different frequencies;

and/or when the remapping module is verified, running the test case to generate the priming excitation module, wherein the priming excitation module sends the excitation to the master device and the bus matrix subunit in the master device read-write subunit, and generates a remapping expected value according to the connection condition of the master/slave device and the remapping module in the function information of the master/slave device and the bus matrix; wherein the test case is a verification case of the remapping module;

And/or, when the virtual clock module verification is executed, running the test case to generate a perfusion excitation module, wherein the perfusion excitation module controls the virtual clock module of the bus matrix to be closed and opened, and the excitation is sent to the main equipment and the bus matrix subunit in the main equipment read-write subunit under the condition that the virtual clock module is closed and opened respectively; wherein the test case is a verification case of a virtual clock.

In some implementations of AHB bus matrix based test systems,

the expected value generating unit is further configured to generate an expected value of the master device priority according to the master device priority in the function information of the master/slave device and bus matrix when performing the master device priority verification;

and/or generating expected values of default slave devices according to the default slave device addresses when the default slave device verification is performed;

and/or when the synchronous frequency verification is executed, generating expected values under different frequency division/multiplication conditions according to the connection condition of the master/slave device and the synchronous frequency module in the function information of the master/slave device and the bus matrix;

And/or when the remapping module is verified, generating a remapping expected value according to the connection condition of the master/slave device and the remapping module in the function information of the master/slave device and the bus matrix;

and/or generating a virtual clock expected value according to the connection condition of the master/slave device and the virtual clock module in the function information of the master/slave device and the bus matrix when the virtual clock module verification is executed.

In some implementations of AHB bus matrix based test systems,

the slave device read-write subunit is further configured to, when the master device priority verification is performed, take the received preset data as master device data when the slave device corresponding to the slave device address receives the write instruction, and when the slave device receives the read instruction, sequentially return the master device data to the master device read-write subunit and the result analysis unit according to the master device priority; the master device data which are returned in sequence are used as slave device data, and the sequence of the slave device data is consistent with the priority of the master device;

and/or, when the default slave device receives the write instruction while performing the default slave device verification, taking the received preset data as master device data; when the default slave device receives the reading instruction, the master device data is returned to the master device reading and writing subunit and the result analysis unit; the master device takes the returned master device data as default slave device data;

And/or, when the slave device receives the write instruction, the slave device uses the received preset data as master device data, and when the slave device receives the read instruction, the master device data is returned to the master device read-write subunit and the result analysis unit; the master device takes the returned master device data as slave device data;

and/or when the remapping module is used for verification, when the remapping slave device receives the reading instruction, the received preset data is used as main device data, and when the slave device receives the reading instruction, the main device data is returned to the main device reading and writing subunit and the result analysis unit through the bus matrix.

In some implementations of AHB bus matrix based test systems,

the result analysis unit is further configured to obtain a verification result under the current condition of the master device priority by comparing the sequence of the slave device data with an expected value of the master device priority when the master device priority verification is performed; traversing all the master device priority cases to obtain a plurality of verification results, and outputting the master device priority verification results according to the verification results;

Compared with the prior art, the invention has at least one of the following beneficial effects:

1. The invention provides a multifunctional AHB bus matrix is an SOC-level verification test system, functional information of master/slave equipment and the AHB bus matrix is input into an automation script to generate verification function points, so that the AHB bus matrix can flexibly verify a plurality of required function points in the verification process, then different master/slave equipment are excited at different function verification points through an excitation module, different expected values are generated, and verification of corresponding function points is realized by judging whether detection results of slave equipment data and master equipment data accord with the expected values or not.

2. The invention provides a method for verifying the connectivity of a bus matrix in a verification function point, which comprises the following two steps: the first step: the master device writes preset data into the highest address and the lowest address of all the slave devices on the bus matrix in sequence, and then compares whether the written and read data are consistent or not to obtain a first verification result; and a second step of: and the slave equipment with the access right of the master equipment which is verified from the first step of verification result extracts a plurality of random addresses from the slave equipment with the access right, writes preset data into the random addresses, compares whether the written and read data are consistent or not, and obtains a bus matrix connectivity verification result, thereby realizing bus matrix connectivity verification in the functional point. The connectivity verification method avoids redundant verification of the master device and the slave device which does not have access rights, and saves the time for performing connectivity verification.

3. The invention provides a method for verifying master equipment priority, default slave equipment, synchronous frequency verification, remapping module verification and virtual clock module verification in function points.

Drawings

The above features, technical features, advantages and implementation of the present invention will be further described in the following description of preferred embodiments with reference to the accompanying drawings in a clear and easily understood manner.

FIG. 1 is a flow chart of a first embodiment of an AHB bus matrix based test method of the present invention;

FIG. 2 is a flow chart of a second embodiment of an AHB bus matrix based test method of the present invention;

FIG. 3 is a flow chart of a third embodiment of an AHB bus matrix based test method of the present invention;

FIG. 4 is a flow chart of a fourth embodiment of an AHB bus matrix based test method of the present invention;

FIG. 5 is a flow chart of a fifth embodiment of an AHB bus matrix based test method of the present invention;

FIG. 6 is a flow chart of a sixth embodiment of an AHB bus matrix based test method of the present invention;

FIG. 7 is a flow chart of a seventh embodiment of an AHB bus matrix based test method of the present invention;

fig. 8 is a system block diagram of an AHB bus matrix based test system of the present invention.

Reference numerals illustrate: 10- -an information input unit; 20- -use case generation unit; 30- -an excitation generation unit; 40- -an expected value generation unit; 50- -a read/write unit; 51—a master read-write subunit; 52- -bus matrix subunit; 53—read-write subunit from device; 60- -result analysis unit.

Detailed Description

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will explain the specific embodiments of the present invention with reference to the accompanying drawings. It is evident that the drawings in the following description are only examples of the invention, from which other drawings and other embodiments can be obtained by a person skilled in the art without inventive effort.

For simplicity of the drawing, only the parts relevant to the invention are schematically shown in each drawing, and they do not represent the actual structure thereof as a product. Additionally, in order to simplify the drawing for ease of understanding, components having the same structure or function in some of the drawings are shown schematically with only one of them, or only one of them is labeled. Herein, "a" means not only "only this one" but also "more than one" case.

It should be further understood that the term "and/or" as used in this specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.

In this context, it should be noted that the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected, unless explicitly stated or limited otherwise; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.

In addition, in the description of the present application, the terms "first," "second," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.

Example 1

Referring to fig. 1 of the specification, the test method based on an AHB bus matrix provided by the invention includes:

s110, inputting the function information of the master/slave device and the bus matrix into an automation script, and generating a test case corresponding to the verification function point by the automation script according to the function information of the master/slave device and the bus matrix; wherein, verify the functional point and include: bus matrix connectivity verification, and/or master device priority verification, and/or default slave device verification, and/or synchronization frequency module verification, and/or remapping module verification, and/or virtual clock module verification.

In step S110, the automation script has strong expansibility and compatibility, and can verify the bus matrix with complex functions. If the verification function point needs to be updated, the automation script does not need to be redesigned, and only the test case related to the verification function point needs to be updated; if verification function points are reduced, the automation script does not need to be redesigned, and when the automation script receives the function information of the master/slave equipment and the bus matrix, the test cases relevant to the corresponding verification function points can be automatically closed, so that development cost is saved.

And S120, operating a test case generation perfusion excitation module, wherein the perfusion excitation module sends excitation to the bus matrix and the master device, and generates expected values according to the functional information of the master/slave device and the bus matrix.

In step S120, the priming excitation module generated by the test case sends a start signal to the bus matrix and the host device specified by the test case, and the priming excitation module also modifies the register on the bus matrix according to the test case to implement the functions of different test cases. For example: when executing the virtual clock module, the virtual clock module may be switched by modifying a switch register of the virtual clock module on the bus matrix. The expected value is derived from master access rights in the master/slave and bus matrix, for example: there are 7 slaves in total, the master 1 has access to slaves 1, 2, i.e. the number of slaves that the master 1 expects to have access to is 2, the slaves that it expects to have access to are numbered 1, 2;

S130, when the master device receives the excitation, a write-read instruction is sent to the bus matrix, wherein the write-read instruction comprises a write instruction and a read instruction.

And S140, when the bus matrix receives the write-read instruction, the bus matrix selects the slave device corresponding to the slave device address and sends the write-read instruction and preset data to the slave device.

In step S130 and step S140, the master device sends a write-read command to the bus matrix, so that the bus matrix selects the slave device to perform data interaction according to address information in the write-read command.

S150, when a slave device receives a write instruction, the slave device takes the received preset data as main device data; when the slave device receives the reading instruction, preset data in the slave device are transmitted back to the master device through the bus matrix, and the transmitted back master device data are used as slave device data;

in step S150, the data sent by the master device is used as master device data, and the backhaul data received by the master device is used as slave device data.

S160, obtaining a detection result according to the main equipment data and the auxiliary equipment data, and outputting a verification result according to a comparison result of the detection result and the expected value.

In step S160, the detection result is compared with the expected value obtained in step S120, and a verification result is output. The detection result is finally obtained by the test case generated by the automation script, for example: the test case is that the master device 1 sequentially performs write-read access to all the slave devices, wherein when only the slave devices 1 and 2 perform data interaction, the master device data is the same as the slave device data, namely the number of the slave devices which the master device 1 can actually access is 2, and the detection result is that the slave devices which the master device 1 can actually access are numbered 1 and 2.

In the embodiment, the function information of the master/slave device and the bus matrix is input into the automation script to generate the verification function point, so that the AHB bus matrix can flexibly verify the function points with multiple requirements in the verification process. And then, through the priming stimulus module, sending stimulus to different master/slave devices at different functional verification points, and generating different expected values. By judging whether the detection results of the slave device data and the master device data accord with expected values or not, verification of corresponding function points is achieved, and the access right of the master device to the slave device can be directly verified through the steps of the embodiment.

Example two

Based on the foregoing embodiment, referring to fig. 2 of the specification, a test method based on an AHB bus matrix is provided, and in the step S160: obtaining a detection result according to the main equipment data and the auxiliary equipment data, and outputting a verification result according to a comparison result of the detection result and an expected value, and further comprising:

s210, when the bus matrix connectivity verification is executed, the test case is a case that a single master device traverses all slave devices; and according to the verification result, the perfusion excitation module randomly generates a plurality of random slave device addresses of which the master devices have master device access rights.

S220, the priming excitation module sends excitation to the bus matrix and the master device, and generates expected values according to the function information of the master/slave device and the bus matrix.

S230, when the master device receives the excitation, a plurality of writing and reading instructions are sent to the bus matrix according to the AHB bus protocol, wherein the writing and reading instructions comprise random slave device addresses.

S240, when the bus matrix receives the write-read command, the bus matrix selects the slave device corresponding to the random slave device address, and sends the write-read command and preset data to the slave device.

S250, when the slave device receives a write-read instruction, taking the received preset data as main device data, and transmitting the main device data back to the main device through a bus matrix; the master device takes the returned master device data as slave device data.

S260, outputting a bus matrix connectivity verification result by analyzing whether the slave device data corresponding to the random slave device address is consistent with the master device data.

The embodiment provides a step of verifying the connectivity of the bus matrix in the verification function point, and after obtaining whether the verification master device has the access right of the slave device through steps S110 to S160, generating a plurality of random slave device addresses of the master device with the access right of the master device; the slave devices in steps S120 to S150 are replaced with random slave devices corresponding to the random slave device addresses, and verification is completed by repeating the execution. According to the embodiment, the situation that when connectivity verification is carried out, when the master device is directly tested to be normally communicated with all the slave devices, the slave devices which are not provided with access rights by the master device are tested in an superfluous mode is avoided, and verification time for carrying out the connectivity verification is saved. Specifically, after obtaining the random slave address, the master may also complete the verification using a continuous scan, for example: the master device 2 has the access rights of the slave devices 4 and 5, the addresses of the slave devices 4 are 0x1000_0000-0x2000_0000, the random slave device addresses 0x1100_0000,0x1300_0000 and 0x1400_0000 are randomly generated, and then the verification is completed by using a continuous scanning mode. The continuous scanning is that the main device continuously sends n writing and reading instructions to the bus matrix, writes random data to the slave device address A+n 4, then sends the random data to the slave device interface through the bus matrix, writes the random data into the slave device address A+n 4, then sends the continuous n writing and reading instructions to the bus matrix, reads the data from the slave device address A+n 4, sends the data in the slave device to the main device interface through the bus matrix, compares the data received by the main device interface with expected data, A is a random slave device address, and n is a numerical value which can be configured by oneself in an automation script.

Example III

On the basis of the foregoing embodiment, referring to fig. 3 of the specification, there is provided a test method based on an AHB bus matrix, when performing priority verification of a master device, after generating a test case corresponding to a verification function point according to function information of the master/slave device and the bus matrix, the method further includes:

s310, operating a test case generation perfusion excitation module, wherein the perfusion excitation module simultaneously transmits excitation to a bus matrix and a plurality of master devices, and generates an expected value of the priority of the master device according to the priority of the master device in the functional information of the master/slave device and the bus matrix; the test case is a case that a plurality of master devices access the same slave device.

S320, when a plurality of master devices receive excitation, the master devices respectively send write and read instructions to the bus matrix at the same time according to an AHB bus protocol.

S330, when the bus matrix receives the write-read command, the bus matrix selects the slave device corresponding to the slave device address, and sends the write-read command and different preset data to the slave device.

S340, when the slave device corresponding to the slave device address receives a write instruction, taking the received preset data as master device data, and when the slave device receives a read instruction, sequentially returning the master device data to the master device through a bus matrix according to the priority of the master device; and taking the sequentially returned master device data as slave device data, wherein the sequence of the slave device data is consistent with the priority of the master device.

S350, comparing the sequence of the slave device data with the expected value of the priority of the master device to obtain a verification result under the condition of the priority of the current master device; traversing all the master device priority cases to obtain a plurality of verification results, and outputting the master device priority verification results according to the verification results.

The embodiment provides a step of verifying the priority of the master device in the verification function point, after step S110, the master device writes preset data into the slave device through a plurality of master devices at the same time, and analyzes whether the sequence of the preset data returned by the slave device accords with the expected value, so as to obtain a master device priority verification result. For example: the master 1, 2, 3, 4 has access to the slave 1 and the automation script generates 1 test cases for verifying the access priority of the master. The perfusion excitation module sends excitation to the master devices 1, 2, 3 and 4 to enable the 4 master devices to initiate single read access to the slave device 1 at the same time, access 4 different addresses of the slave device 1, and obtain the priority order of the master devices by analyzing the time sequence of the returned data of the slave devices; comparing whether the priority of the main equipment is consistent with the expected value; then the perfusion excitation module sends excitation to the bus matrix to traverse all priority ranking sequences, namely 24 sequences; when the master priority of each order is consistent with the expected value, the master priority validates.

Example IV

On the basis of the foregoing embodiment, referring to fig. 4 of the present application, there is provided a test method based on an AHB bus matrix, where when performing default slave device verification, after generating a test case corresponding to a verification function point according to function information of a master/slave device and a bus matrix, the automatic script in step S110 further includes:

s410, running a test case to generate a perfusion excitation module, wherein the perfusion excitation module randomly generates a plurality of default slave device addresses according to the default slave device addresses in the function information of the master/slave devices and the bus matrix, transmits excitation to the bus matrix and the master device, and generates expected values of the default slave devices according to the default slave device addresses; wherein the test case is a case where the master accesses a default slave address, which is an address that is not within the master/slave range.

S420, when the master device receives the excitation, a plurality of write-read instructions are sent to the bus matrix according to the AHB bus protocol, wherein the plurality of write-read instructions comprise different default addresses.

And S430, when the bus matrix receives the write-read instruction, the bus matrix selects the slave device corresponding to the slave device address and sends the write-read instruction and preset data to the slave device.

S440, when the default slave device receives a write instruction, taking the received preset data as the master device data; when the default slave device receives a read instruction, the master device data is returned to the master device, and the master device takes the returned master device data as the default slave device data.

S450, obtaining a detection result according to the default slave device data and the master device data, and outputting a default slave device verification result according to a comparison result of the detection result and the expected value.

The present embodiment performs default slave device authentication in the authentication function point, which is authentication of a default slave device address that is not at the master device address or the slave device address. For example: the total address range is 0x0000_0000-0x1000_0000, the range of the master device address and the slave device address is 0x0000_0000-0x0a00_0000, and the default slave device address is 0x0a00_0000-0x1000_0000. When there are 4 master devices in total, the automation script generates 4 test cases for verifying the connectivity of the bus matrix corresponding to the master devices 1, 2, 3 and 4; taking a test case of the main equipment 1 as an example, the perfusion excitation module sends random excitation to the main equipment 1, so that the main equipment 1 sequentially performs single write-read operation on 500 random addresses which are not in the range of the main equipment and repeats the single write-read operation 5 times, and according to a five-step method, each write-in data is respectively 0xffffffff, 0x55555555, 0xaaaaaaa, 0xa55aa55a and 0x5aa55aa5; the expected value is obtained according to the default slave device address in the function information of the master/slave device and the bus matrix, and the default slave device address also comprises a reserved address and a blank address; when the master device 1 accesses a blank address, the master device 1 modifies the expected value to 0 and returns a normal signal; and analyzing the returned data of the slave device, and verifying the passing of the default slave device when the returned data is judged to be consistent with the expected value.

Example five

On the basis of the foregoing embodiment, referring to fig. 5 of the present specification, there is provided a test method based on an AHB bus matrix, where when performing synchronous frequency verification, after generating a test case corresponding to a verification function point according to function information of a master/slave device and the bus matrix, the automatic script in step S110 further includes:

s510, operating a test case to generate a perfusion excitation module, wherein the perfusion excitation module modifies frequency division/frequency multiplication values of the master device and the slave device, sends excitation to the bus matrix and the master device under different frequency division/frequency multiplication values, and generates expected values under different frequency division/frequency multiplication conditions according to connection conditions of the master/slave device and the synchronous frequency module in the functional information of the master/slave device and the bus matrix; wherein the test case is a case of communication of the master/slave device at different frequencies.

S520, when the master device receives the excitation, a plurality of write and read instructions are sent to the bus matrix according to the AHB bus protocol.

And S530, when the bus matrix receives the write-read instruction, the bus matrix selects the slave device corresponding to the slave device address, and sends the write-read instruction and preset data to the slave device.

S540, when the slave device receives a write instruction, the received preset data is used as main device data, and when the slave device receives a read instruction, the main device data is transmitted back to the main device through the bus matrix; the master device takes the returned master device data as slave device data.

S550, obtaining a detection result according to the main equipment data and the auxiliary equipment data, and outputting a verification result of the synchronous frequency module according to a comparison result of the detection result and the expected value.

When the synchronization frequency verification in the verification function point is performed, the detection results of the master device and the slave device are compared with the expected value under different frequency division/multiplication conditions. For example: analyzing the function information of the master/slave devices and the bus matrix to obtain 4 master devices in total, and generating 4 use cases of master/slave device communication under different frequencies by an automatic script to correspond to the master devices 1, 2, 3 and 4; taking a test case of the master device 3 as an example, the master device 3 has access rights of the slave devices 1, 2, 3, 5 and 6, the master device 3 is connected with the bus matrix through the synchronous frequency module, and the perfusion excitation module sends excitation to the bus matrix; the doubling/dividing value of the master 3 and the doubling/dividing values of the slaves 1, 2, 3, 5, 6 are modified. In the case of different multiples/divisions, for example: the clock frequency of the master device 3 is 80MHz, the clock frequency of the slave devices 1 and 2 is 40MHz, the clock frequency of the slave device 4 is 80MHz, the clock frequency of the slave devices 5 and 6 is 160MHz, the perfusion excitation module sends excitation to the master device 3, the master device 3 sequentially carries out single-time write-read operation and repeat 5 times on the highest address and the lowest address of the slave devices 1, 2, 3, 5 and 6 according to the sequence, and each write data is respectively 0xffffffff, 0x 5555555555, 0xaaaaaaa, 0xa55aa55a and 0x5aa55aa5. Under the condition of different frequency division and multiplication, comparing the detection result of each slave device with an expected value to obtain a preliminary verification result of the synchronous frequency module. Furthermore, the priming excitation module generates a plurality of random slave device addresses with access authority of the master device 3 according to the preset interval of the preliminary result, the master device 3 performs writing and reading operations in a continuous scanning mode, and under different frequency division and frequency multiplication conditions, the detection result and the expected value of the random slave device addresses are compared to obtain a complete verification result of the synchronous frequency module.

Example six

On the basis of the foregoing embodiment, referring to fig. 6 of the present specification, there is provided a test method based on an AHB bus matrix, where when executing verification of a remapping module, after generating a test case corresponding to a verification function point according to function information of a master/slave device and a bus matrix, the automated script in step S110 further includes:

s610, a test case generation perfusion excitation module is operated, the perfusion excitation module sends excitation to a bus matrix and a master device, and a remapping expected value is generated according to connection conditions of the master/slave device and a remapping module in the function information of the master/slave device and the bus matrix; the test case is a verification case of the remapping module.

S620, when the master device receives the stimulus, several write-read instructions are sent to the bus matrix, the several write-read instructions including different remapped slave device addresses.

S630, when the bus matrix receives the write-read command, the bus matrix selects the remapping slave corresponding to the address of the remapping slave, and sends the write-read command and preset data to the remapping slave.

S640, when the remapping slave device receives a write instruction, the received preset data is used as main device data, and when the slave device receives a read instruction, the main device data is returned to the main device through a bus matrix; the master device uses the returned master device data as remapped slave device data.

S650, obtaining a detection result according to the main equipment data and the remapping slave equipment data, and outputting a remapping module verification result according to a comparison result of the detection result and the expected value.

In the embodiment, when the remapping slave device in the verification function point is performed, the master device or the slave device with the remapping function can map a plurality of addresses. The bus matrix can be controlled by the remapping control bits which can be configured by self in the automation script to realize the change of the address space of the master/slave equipment, and the slave equipment a with three addresses has addresses of 0x1000_0000-0x2000_0000,0x3000_0000-0x4000_0000 and 0x5000_0000-0x6000_0000; if the remapping control bit is 0, slave a has three addresses; if the remapping control bit is 1, slave a has only two addresses 0x1000_0000-0x2000_0000,0x3000_0000-0x4000_0000; if the remapping control bit is 2, slave a has only one address 0x1000_0000-0x2000_0000, which can be modified by itself in the automation script. Taking the test case of the slave device 4 as an example, the slave device 4 oversubscription mapping module is connected to the bus and can map 3 blocks of address spaces respectively which are 0x08000000-0x09000000, 0x10000000-0x11000000 and 0x11000000-0x12000000, when the remapping control bit is 0, the slave device 4 has three addresses: 0x08000000-0x09000000, 0x10000000-0x11000000, 0x11000000-0x12000000, when the remapping control bit is 1, slave device 4 has two addresses: 0x08000000-0x09000000, 0x10000000-0x11000000, when the remapping control bit is 1, slave 4 has an address: 0x08000000-0x09000000, the bus matrix of the priming stimulus module sends a stimulus to traverse the remapping control bits from device 4. Under the condition of different remapping control bits, the perfusion excitation module sends excitation to enable the master equipment 1, 2, 3 and 4 to sequentially perform single-time write-read operation on the highest address and the lowest address of the slave equipment 4 and repeat for 5 times, each time of write data is respectively 0xffffffff, 0x55555555, 0xaaaaaaa, 0xa55aa55a and 0x5aa55aa5, whether the data read out by each time of write are consistent or not is compared, a detection result is obtained, the detection result is compared with an expected value, and whether the function of the remapping module is normal when the remapping control bits of the slave equipment 4 are 0, 1 and 2 is tested.

Example seven

On the basis of the foregoing embodiment, referring to fig. 7 of the specification, there is provided a test method based on an AHB bus matrix, where when executing virtual clock module verification, after generating a test case corresponding to a verification function point according to function information of a master/slave device and a bus matrix, the method further includes:

s710, operating the test case to generate a perfusion excitation module, wherein the perfusion excitation module controls the closing and opening of a bus matrix virtual clock module, sends excitation to a bus matrix and a master device respectively under the condition that the virtual clock module is closed and opened, and generates a virtual clock expected value according to the connection condition of the master/slave device and the virtual clock module in the function information of the master/slave device and the bus matrix; wherein the test case is a verification case of the virtual clock.

S720, when the master device receives the excitation, a write-read instruction is sent to the bus matrix, wherein the write-read instruction comprises the address of the slave device.

And S730, when the bus matrix receives the write-read instruction, the bus matrix selects the slave device corresponding to the slave device address and sends the write-read instruction and preset data to the slave device.

S740, when the slave device receives a write instruction, taking the received preset data as main device data, and when the slave device receives a read instruction, returning the main device data to the main device through a bus matrix; the master device takes the returned master device data as slave device data.

S750, obtaining a detection result according to the main equipment data and the auxiliary equipment data, and outputting a virtual clock module verification result according to a comparison result of the detection result and the expected value.

The present embodiment performs virtual clock verification in the verification function point. When a virtual clock is started by adopting a five-step verification method, each master device sends a write-read instruction to all slave devices, and whether write-in read data are consistent is compared; when the virtual clock is turned off, each master device sends a write-read instruction to all slave devices, and the slave devices with the virtual clock module read data to 0. And detecting whether the influence of the opening and closing of the virtual clock on the reading and writing of the slave device with the function accords with an expected value or not, wherein the expected value is obtained according to the connection condition of the master/slave device and the virtual clock module in the function information of the master/slave device and the bus matrix. For example: only the slave device 7 is connected with the virtual clock module, and when the virtual clock module is started, the master devices 1 and 2 can access the slave device 7 through the bus matrix, and the slave device data are consistent with the master device data; when the virtual clock module is turned off, the master 1, 2 cannot access the slave 7 through the bus matrix, the master data is 0, and the virtual clock module passes the verification.

Example eight

Referring to fig. 8 of the specification, the test system based on an AHB bus matrix according to the present invention is characterized by comprising:

an information input unit 10 for inputting the function information of the master/slave device and the bus matrix to the automation script, and transmitting the function information of the master/slave device and the bus matrix to the use case generating unit 20 and the expected value generating unit 40.

A case generation unit 20 connected to the information input unit 10, for generating a test case corresponding to the verification function point according to the function information of the master/slave device and the bus matrix by the automation script, and transmitting the test case to the excitation generation unit 30; wherein, verify the functional point and include: bus matrix connectivity verification, and/or master device priority verification, and/or default slave device verification, and/or synchronization frequency module verification, and/or remapping module verification, and/or virtual clock module verification.

The excitation generation unit 30 is connected to the case generation unit 20, and is configured to run a test case generation priming excitation module, where the priming excitation module sends excitation to the read/write unit 50 and the expected value generation unit 40.

The expected value generating unit 40 is connected to the information input unit 10 and the excitation generating unit 30, and is configured to generate expected values based on the function information of the master/slave device and the bus matrix when the excitation is received.

The read-write unit 50 includes a main device read-write subunit 51, where the main device read-write subunit 51 is configured by a main device connected to the AHB bus matrix, and is configured to send a write-read instruction to the bus matrix subunit 52 according to the AHB bus protocol when receiving the stimulus, where the write-read instruction includes a write instruction and a read instruction.

The read-write unit 50 further comprises a bus matrix subunit 52, and the bus matrix subunit 52 is configured to send, when receiving the write-read command, the write-read command and the preset data to the slave read-write subunit 53 according to the slave address.

The read-write unit 50 further includes a slave read-write subunit 53, where the slave read-write subunit 53 is configured by a slave device connected to the AHB bus matrix, and is configured to take the received preset data as the master device data when receiving a write instruction, and to return the master device data to the master device read-write subunit 51 and the result analysis unit 60 when receiving the read instruction.

The master read/write subunit 51 is further configured to take the master data returned by the slave read/write subunit 53 as slave data, and send the slave data to the result analysis unit 60.

And a result analysis unit 60 for obtaining a detection result according to the analysis of the master device data and the slave device data, and outputting a verification result according to the comparison result of the detection result and the expected value.

In this embodiment, the information input unit 10 inputs the function information of the master/slave device and the bus matrix into the expected value generating unit 40 and the automation script, and the use case generating unit 20 runs the automation script to generate a plurality of test cases. Then, the excitation generating unit 30 runs the test case generating perfusion excitation module, sends excitation to the expected value generating unit 40 and the read-write unit 50, and generates an expected value after the expected value generating unit 40 receives the excitation. After the read-write unit 50 receives the excitation, the master device sends the master device data to the slave device, the slave device receives the master device data, feeds back the slave device data, compares the master device data with the slave device data, obtains a detection result, and the result analysis unit 60 compares the detection result with the expected value to obtain a verification result. According to the embodiment, different functions are verified through different test cases, all the test cases are generated by the script, so that the probability of human errors is reduced, the method has strong expansibility and compatibility, a bus matrix with complex functions can be verified, and the method can also be directly updated in an automatic script, so that the development cost is saved.

Example nine

On the basis of the foregoing embodiment, there is provided a test system based on an AHB bus matrix, and the excitation generating unit 30 is further configured to run a test case to generate a priming excitation module when performing priority verification of a master device, where the priming excitation module sends excitation to a plurality of master devices in the master device read-write subunit 51 and the bus matrix subunit 52 simultaneously; the test case is a case that a plurality of master devices access the same slave device;

And/or, when executing default slave device verification, running a test case to generate a perfusion excitation module, wherein the perfusion excitation module randomly generates a plurality of default addresses according to default slave device addresses in the function information of the master/slave device and the bus matrix, and sends excitation to the master device and the bus matrix subunit 52 in the master device read-write subunit 51; wherein the test case is a case where the master accesses a default slave address, which is an address that is not within the master/slave range.

And/or, when synchronous frequency verification is executed, running a test case to generate a perfusion excitation module, wherein the perfusion excitation module modifies frequency division/frequency multiplication values of the master device and the slave device, and under different frequency division/frequency multiplication values, the master device in the master device read-write subunit 51 and the bus matrix subunit 52 send excitation; wherein the test case is a case of communication of the master/slave device at different frequencies.

And/or, when executing the verification of the remapping module, running the test case to generate a perfusion excitation module, wherein the perfusion excitation module sends excitation to the master device and the bus matrix subunit 52 in the master device read-write subunit 51, and generates a remapping expected value according to the connection condition of the master/slave device and the remapping module in the function information of the master/slave device and the bus matrix; the test case is a verification case of the remapping module.

And/or, when executing the verification of the virtual clock module, running the test case to generate a perfusion excitation module, wherein the perfusion excitation module controls the closing and opening of the bus matrix virtual clock module, and sends excitation to the main device in the main device read-write subunit 51 and the bus matrix subunit 52 under the condition that the virtual clock module is closed and opened respectively; wherein the test case is a verification case of the virtual clock.

The present embodiment provides that the stimulus generating unit 30 sends different stimuli to the master read-write subunit 51 at different functional verification points, so as to change the sending device of the preset data, and sends different stimuli to the bus matrix subunit 52, so that the bus matrix adjusts the registers on the bus matrix according to the stimuli. For example: the registers of the master device priorities may be modified so that when master device priority verification is performed, all master device priorities may be traversed to perform a test, and different stimuli may be sent to the expected value generating unit 40, so that the expected value generating unit 40 calculates a value when the verification function point passes through according to a test case.

Examples ten

On the basis of the foregoing embodiments, there is provided a test system based on an AHB bus matrix, the expected value generating unit 40 further configured to generate, when performing master priority verification, an expected value of a master priority according to a master priority in function information of a master/slave and the bus matrix.

And/or generating expected values of the default slave devices according to the default slave device addresses when performing default slave device verification.

And/or when the synchronous frequency verification is executed, generating expected values under different frequency division/multiplication conditions according to the connection condition of the master/slave device and the synchronous frequency module in the function information of the master/slave device and the bus matrix.

And/or generating a remapping expected value according to the connection condition of the master/slave device and the remapping module in the function information of the master/slave device and the bus matrix when the remapping module is verified.

The present embodiment specifically exemplifies the function of the expected value generating unit 40 to generate expected values of corresponding function points at different verification function points based on the function information of the master/slave device and the bus matrix.

Example eleven

On the basis of the foregoing embodiment, there is provided a test system based on an AHB bus matrix, and the master read-write subunit 51 is further configured to, when performing master priority verification, send, to the bus matrix subunit 52, read-write instructions and different preset data according to the AHB bus protocol, respectively, when a plurality of masters receive an excitation.

And/or, upon performing a default slave device verification, when the master device receives a stimulus, a number of write read instructions are sent to the bus matrix subunit 52 according to the AHB bus protocol, the write read instructions including a default address.

And/or, when the master device receives the stimulus while performing synchronous frequency verification/virtual clock module verification, a number of write read instructions are sent to the bus matrix subunit 52 according to the AHB bus protocol, the write read instructions including the slave device address.

And/or, upon performing remapping module verification, when the master receives a stimulus, a number of write read instructions are sent to the bus matrix subunit 52, the write read instructions including remapping the slave addresses.

The present embodiment specifically enumerates the functions of the master device read/write subunit 51 for selecting the corresponding slave device address to write the write/read command at different verification function points.

Example twelve

On the basis of the foregoing embodiment, there is provided a test system based on an AHB bus matrix, a slave read-write subunit 53 further configured to, when performing master priority verification, take received preset data as master data when a slave corresponding to a slave address receives a write instruction, and when the slave receives a read instruction, sequentially return the master data to the master read-write subunit 51 and the result analysis unit 60 according to the master priority; and taking the sequentially returned master device data as slave device data, wherein the sequence of the slave device data is consistent with the priority of the master device.

And/or when the default slave device receives a write instruction during the execution of the default slave device verification, taking the received preset data as the master device data; when the default slave device receives a read instruction, the master device data is returned to the master device read-write subunit 51 and the result analysis unit 60; the master device uses the returned master device data as default slave device data.

And/or, when the slave device receives the write command, the received preset data is used as master device data, and when the slave device receives the read command, the master device data is returned to the master device read-write subunit 51 and the result analysis unit 60; the master device takes the returned master device data as slave device data.

And/or, when the remapping module is verified, when the remapping slave device receives a read instruction, the received preset data is used as the master device data, and when the slave device receives the read instruction, the master device data is returned to the master device read-write subunit 51 and the result analysis unit 60 through the bus matrix.

The embodiment specifically enumerates the function of the slave read-write subunit 53 to return the corresponding data when executing different verification function points.

Example thirteen

On the basis of the foregoing embodiment, there is provided a test system based on an AHB bus matrix, and the result analysis unit 60 is further configured to obtain, when performing master priority verification, a verification result in the case of the current master priority by comparing the order of slave data with an expected value of the master priority; traversing all the master device priority cases to obtain a plurality of verification results, and outputting the master device priority verification results according to the verification results.

And/or when the default slave device verification is executed, obtaining a detection result according to the default slave device data and the master device data, and outputting a default slave device verification result according to a comparison result of the detection result and an expected value.

And/or when the synchronous frequency verification is executed, a detection result is obtained according to the main equipment data and the auxiliary equipment data, and a synchronous frequency module verification result is output according to a comparison result of the detection result and the expected value.

And/or when the remapping module verification is executed, obtaining a detection result according to the main equipment data and the remapping slave equipment data, and outputting the remapping module verification result according to a comparison result of the detection result and the expected value.

And/or when the virtual clock module verification is executed, a detection result is obtained according to the master device data and the slave device data, and a virtual clock module verification result is output according to a comparison result of the detection result and the expected value.

The present embodiment specifically exemplifies the function of the result analysis unit 60 for calculating the corresponding detection result when executing different verification function points.

It should be noted that, the embodiment of the test system based on the AHB bus matrix provided by the present invention and the embodiment of the test method based on the AHB bus matrix provided by the present invention are both based on the same inventive concept, so that the same technical effects can be obtained. Thus, for further details of embodiments of an AHB bus matrix based test system, reference may be made to the description of the embodiments of an AHB bus matrix based test method described above.

It should be noted that the above embodiments can be freely combined as needed. The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.

Claims

1. The test method based on the AHB bus matrix is characterized by comprising the following steps of:

When the slave device receives the writing instruction, the slave device takes the received preset data as master device data; when the slave device receives the reading instruction, the preset data in the slave device is transmitted back to the master device through the bus matrix, and the transmitted back master device data is used as slave device data;

2. The method for testing an AHB-based bus matrix as defined in claim 1, wherein,

3. The AHB bus matrix-based test method of claim 2, further comprising, after obtaining a detection result according to the master device data and the slave device data and outputting a verification result according to a comparison result between the detection result and the expected value:

When the bus matrix connectivity verification is executed, the test case is a case that a single master device traverses all slave devices; according to the verification result, the perfusion excitation module randomly generates a plurality of random slave device addresses of which the master devices have slave device access rights;

4. The AHB bus matrix-based test method of claim 3, wherein the running the test case generates a priming stimulus module, the priming stimulus module sends stimulus to a bus matrix and a master device, and generates a desired value according to functional information of the master/slave device and the bus matrix, comprising:

when the master device priority verification is executed, the test case is operated to generate the priming excitation module, the priming excitation module simultaneously sends the excitation to the bus matrix and a plurality of master devices, and an expected value of the master device priority is generated according to the master device priority in the functional information of the master/slave devices and the bus matrix; the test case is a case that a plurality of master devices access the same slave device;

And/or, when executing the default slave device verification, running the test case to generate the priming excitation module, wherein the priming excitation module randomly generates a plurality of default addresses according to the default slave device addresses in the function information of the master/slave device and the bus matrix, sends the excitation to the bus matrix and the master device, and generates expected values of the default slave devices according to the default slave device addresses; wherein the test case is a case in which the master device accesses a default slave device address, which is an address that is not within the master/slave device range;

5. The AHB bus matrix-based test method of claim 4, wherein the slave device takes the received preset data as master device data when the slave device receives the write command; when the slave device receives the read instruction, the preset data in the slave device is returned to the master device through the bus matrix, and the returned master device data is used as slave device data, including:

6. The AHB bus matrix-based test method of claim 5, wherein the obtaining a detection result according to the master device data and the slave device data, and outputting a verification result according to a comparison result between the detection result and the expected value, comprises:

7. An AHB bus matrix-based test system, comprising:

8. The AHB bus matrix based test system of claim 7, wherein,

and/or when the virtual clock module verification is executed, running the test case to generate the priming excitation module, wherein the priming excitation module controls the virtual clock module of the bus matrix to be turned off and turned on, and the excitation is sent to the main equipment and the bus matrix subunit in the main equipment read-write subunit under the condition that the virtual clock module is turned off and turned on respectively; wherein the test case is a verification case of a virtual clock.

9. The AHB bus matrix-based test system of claim 8, wherein,

10. The AHB bus matrix-based test system of claim 9, wherein,

11. The AHB bus matrix based test system of claim 10, wherein,