CN213780287U - Digital integrated circuit testing device and digital integrated circuit testing system - Google Patents
Digital integrated circuit testing device and digital integrated circuit testing system Download PDFInfo
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- CN213780287U CN213780287U CN202022917808.XU CN202022917808U CN213780287U CN 213780287 U CN213780287 U CN 213780287U CN 202022917808 U CN202022917808 U CN 202022917808U CN 213780287 U CN213780287 U CN 213780287U
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Abstract
The embodiment of the application provides a digital integrated circuit testing device and a digital integrated circuit testing system. The digital integrated circuit testing device comprises a storage module, a control module and a channel switching module. The storage module comprises a plurality of single-channel storage units. The control module includes a plurality of single channel control circuits. The plurality of single-channel storage units are connected with the plurality of single-channel control circuits in a one-to-one correspondence manner. Each single-channel control circuit and the single-channel storage unit connected with the single-channel control circuit form a single-channel resource group. The channel switching module is connected with the plurality of single-channel control circuits, so that the corresponding connection relation of each channel can be changed according to requirements; the initialization data and the control program of each channel can be set differently, thereby improving the flexibility of the digital integrated circuit testing device.
Description
Technical Field
The present invention relates to the field of integrated circuit testing technologies, and in particular, to a digital integrated circuit testing apparatus and a digital integrated circuit testing system.
Background
In the field of integrated circuit testing, a conventional digital integrated circuit testing system is generally a set of core control circuits and a set of storage modules, which control N (generally taking values of 8,16,32,64,128) channels. The multi-channel shared digital integrated circuit test system can cause the relevance among the channels to be close in the using process and cause application limitation in the using process.
SUMMERY OF THE UTILITY MODEL
In view of the above, it is desirable to provide a digital integrated circuit testing apparatus and a digital integrated circuit testing system.
A digital integrated circuit testing apparatus, comprising:
a storage module comprising a plurality of single-channel storage cells;
the control module comprises a plurality of single-channel control circuits, and the plurality of single-channel storage units are connected with the plurality of single-channel control circuits in a one-to-one correspondence manner; and
and the channel switching module is connected with the plurality of single-channel control circuits and is used for connecting the tested device.
In one embodiment, the single channel storage unit comprises a control data subunit, the single channel control circuit comprises a clock generator and a rate and address generator which are connected with each other, the control data subunit is respectively connected with the clock generator and the rate and address generator, and the control data subunit is used for controlling the rate and address generator to generate a rate and an access address and controlling the clock generator to generate a clock signal together with the rate and address generator.
In one embodiment, the single channel storage unit includes a vector data subunit, the single channel control circuit includes a waveform generator, the vector data subunit is connected to the waveform generator, the clock generator is connected to the waveform generator, the waveform generator is connected to the channel switching module, and clock signals generated by the vector data subunit and the clock generator are used for enabling the waveform generator to send driving waveform signals to the channel switching module.
In one embodiment, the single channel control circuit includes a waveform comparator, the vector data subunit is connected to the waveform comparator, the vector data subunit is configured to enable the waveform comparator to generate an expected waveform signal, and the waveform comparator is further connected to the channel switching module and configured to receive a response waveform signal, where the response waveform signal is obtained by the device under test under excitation of the driving waveform signal.
In one embodiment, the waveform generator is connected to the waveform comparator, and the vector data subunit is configured to cause the waveform comparator to generate the expected waveform signal through the waveform generator.
In one embodiment, the single-channel storage unit further comprises a result storage subunit, connected to the waveform comparator, for storing a comparison result of the expected waveform signal and the response waveform signal.
In one embodiment, the result storing subunit is configured to store an error result after comparing the expected waveform signal and the response waveform signal.
In one embodiment, the device under test further comprises a level driving comparison circuit, and the level driving comparison circuit is connected with the channel switching module and the device under test.
In one embodiment, the channel switching module includes a plurality of first multiplexers and a plurality of second multiplexers, the plurality of first multiplexers and the plurality of second multiplexers are connected with the level driving comparison circuit, and the plurality of first multiplexers and the plurality of second multiplexers are further connected with the control module;
each first multiplexer is used for selecting one of a plurality of driving waveform signals generated by the control module to be sent to the tested device through the level driving comparison circuit; each second multiplexer is used for selecting one of a plurality of response waveform signals returned from the level driving comparison circuit to be sent to the control module, wherein the response waveform signals are obtained by the tested device under the excitation of the driving waveform signals.
An embodiment of the present application further provides a digital integrated circuit test system, including:
the digital integrated circuit testing device;
and the control terminal is connected with the storage module, the control module and the channel switching module through buses and is used for realizing data interaction with the storage module, the control module and the channel switching module.
The embodiment of the application provides a digital integrated circuit testing device and a digital integrated circuit testing system. The digital integrated circuit testing device comprises a storage module, a control module and a channel switching module. The storage module comprises a plurality of single-channel storage units. The control module includes a plurality of single channel control circuits. The plurality of single-channel storage units are connected with the plurality of single-channel control circuits in a one-to-one correspondence manner. Each single-channel control circuit and the single-channel storage unit connected with the single-channel control circuit form a channel resource group. The channel switching module is connected with the single-channel control circuits, so that the connection relation between the IO of the single-channel control circuit and each channel IO of the channel switching module can be controlled by the channel switching module, and the flexibility of channel connection use of the digital integrated circuit testing device is improved.
The digital integrated circuit test system comprises a control terminal. The control terminal can be used for presetting programs in the digital integrated circuit testing device so as to control different channel resource groups of the digital integrated circuit testing device to independently start or stop. The control terminal writes different data into the single-channel storage unit, that is, different single-channel storage units can control the corresponding clock generator and the rate and address generator to operate at different rates, different addresses and different clocks. Different single-channel storage units in the storage module can independently store vectors of different formats, store and read the vectors from different initial positions, and run different instructions. Therefore, each channel of the digital integrated circuit test system can be flexibly configured, and the applicability of the digital integrated circuit test system is improved.
Drawings
FIG. 1 is a block diagram of a digital integrated circuit testing apparatus according to an embodiment of the present disclosure;
fig. 2 is a structural diagram of a single-channel storage unit and a single-channel control circuit according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a channel switching module according to an embodiment of the present application.
Description of reference numerals:
a digital integrated circuit test apparatus 10; a storage module 100; a single-channel storage unit 110; a control data subunit 112; a vector data subunit 114; a result storage subunit 116; a control module 200; a single channel control circuit 210; a clock generator 212; a rate and address generator 214; a waveform generator 216; a waveform comparator 218; a channel switching module 300; a first multiplexer 310; a second multiplexer 320; a level driving comparison circuit 400; the device under test 500.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. This application is capable of embodiments in many different forms than those described herein and those skilled in the art will be able to make similar modifications without departing from the spirit of the application and it is therefore not intended to be limited to the embodiments disclosed below.
The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings). In the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience in describing the present application and for simplicity in description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be considered as limiting the present application.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through intervening media. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
The inventor researches and discovers that the relevance among channels caused by a test system with a multi-channel shared core control circuit is close, and the application limitation caused by the test system in the use process is generally expressed in the following points: the traditional system N-channel digital integrated circuit test system shares a set of core control circuit, and each channel can only start measurement at the same time and run at the same speed; the traditional system N-channel digital integrated circuit test system shares a set of storage modules, and each channel can only store or read vectors at the same time and run the same instruction; the corresponding relation between the connection of N channels and devices IO [1-N ] to be tested in the traditional system N-channel digital integrated circuit test system is fixed, and the corresponding relation cannot be flexibly configured in the test process.
Referring to fig. 1, an embodiment of the present application provides a digital integrated circuit testing apparatus 10. The digital integrated circuit testing device 10 includes a storage module 100, a control module 200 and a channel switching module 300. The storage module 100 includes a plurality of single-channel storage units 110. The control module 200 includes a plurality of single channel control circuits 210. The plurality of single-channel storage units 110 and the plurality of single-channel control circuits 210 are connected in a one-to-one correspondence. The channel switching module 300 is connected to the plurality of single-channel storage units 110. The channel switching module 300 is used for connecting the device under test 500.
Various data can be stored in the single-channel storage unit 110. The type and form of data stored in the storage module 100 are not limited as long as the operation requirements of the digital integrated circuit testing device 10 can be met. The single-channel storage unit 110 may store data of the test result of the digital integrated circuit testing apparatus 10 on the device under test. The single-channel storage unit 110 may further store a preset program to control the operating state of the single-channel control circuit 210 in the control module 200. The type of data and the control program stored in each of the single-channel storage units 110 may be different.
The specific structure of the plurality of single-channel control circuits 210 may be the same or different. The specific structure in the single channel control circuit 210 may depend on different design requirements. It can be understood that the operating states of a plurality of the single-channel control circuits 210 can also be set as required to reflect the differentiation of different channels. The channel switching module 300 may be used to switch different channels, i.e. may set the connection relationship between the logic signal and the channel on the hardware. The channel switching module 300 can change the corresponding relationship between input and output according to the requirement.
The digital integrated circuit testing apparatus 10 provided in the embodiment of the present application includes a storage module 100, a control module 200, and a channel switching module 300. The storage module 100 includes a plurality of single-channel storage units 110. The control module 200 includes a plurality of single channel control circuits 210. The plurality of single-channel storage units 110 and the plurality of single-channel control circuits 210 are connected in a one-to-one correspondence. Each of the single-channel control circuits 210 and the single-channel storage units 110 connected thereto form a channel resource group. The channel switching module 300 is connected to the plurality of single-channel control circuits 210, so that the connection relationship between the IO of each single-channel control circuit 210 and each channel IO of the channel switching module 300 can be controlled by the channel switching module 300, thereby improving the flexibility of channel connection and use of the digital integrated circuit testing apparatus 10.
Referring to fig. 2, in one embodiment, the single-channel storage unit 110 includes a control data subunit 112. The single channel control circuit 210 includes a clock generator 212 and a rate and address generator 214 connected to each other. The control data subunit 112 is connected to the clock generator 212 and the rate and address generator 214, respectively. The control data subunit 112, in conjunction with the rate and address generator 214, controls the rate and address generator 214 to generate the rate and access addresses and controls the clock generator 212 to generate the clock signal.
In this embodiment, each of the single-channel storage units 110 includes one of the control data subunits 112. In a plurality of the single-channel storage units 110, the control program stored in each of the control data subunits 112 may be different. Therefore, the clock generator 212 and the rate and address generator 214 controlled by different control data subunits 112 may operate in different states and manners. In operation, the control data subunit 112 controls the rate and address generator 214 to generate the rate and access addresses. The control data subunit 112 controls the clock generator 212 to generate a clock signal. Wherein the clock generator 212 is acted upon by a rate which, in cooperation with the control data subunit 112, causes the clock generator 212 to generate a plurality of clock signals.
It will be appreciated that the rate in the rate and address generator 214 may be a periodic pulse generated when an accumulation counter is added to a user set rate interval value. The access address is a new address that is determined to be either a 1 accumulation or reset based on the rate pulses and the single channel storage unit 110. The clock generator 212 generates a clock pulse, i.e., a clock signal, according to the clock principle, when the count of the accumulation counter reaches a user setting value.
In one embodiment, the single channel storage unit 110 includes a vector data subunit 114. The single channel control circuit 210 includes a waveform generator 216. The vector data subunit 114 is connected to the waveform generator 216. The clock generator 212 is connected to the waveform generator 216. The waveform generator 216 is connected to the channel switching module 300. The clock signals generated by the vector data subunit 114 and the clock generator 212 are used to cause the waveform generator 216 to send driving waveform signals to the channel switching module 300.
In this embodiment, the vector data subunit 114 is connected to the waveform generator 216. The clock generator 212 is connected to the waveform generator 216. Thus, the plurality of clocks generated by the rate and control data subunit 112 act on the waveform generator 216 and operate with the magnitude data subunit to generate the drive waveform signal. The driving waveform signal can be input to the channel switching module 300, so that the driving waveform signal can be switched to a different channel IO interface in the channel switching module 300 and then input to the device under test.
In one embodiment, the single channel control circuit 210 includes a waveform comparator 218. The vector data subunit 114 is connected to the waveform comparator 218. The vector data subunit 114, in conjunction with the waveform generator 216, causes the waveform comparator 218 to generate a desired waveform signal. The waveform comparator 218 is also connected to the channel switching module 300. The waveform comparator 218 is configured to receive a response waveform signal through the channel switching module 300. The response waveform signal is obtained by the device under test 500 under the excitation of the driving waveform signal. It is understood that the vector data subunit 114 and the waveform comparator 218 may be directly connected or indirectly connected, as long as the waveform comparator 218 is enabled to generate the expected waveform signal.
In this embodiment, the waveform comparator 218 may be configured to compare the response waveform signal with the expected waveform signal for consistency when a user-specified sampling clock signal arrives. That is, the waveform comparator 218 is used to compare whether the data of the response waveform signal is consistent with the vector data value generated by the vector data subunit 114, and to latch the comparison result.
When the response waveform signal and the expected waveform signal are not consistent, it indicates that there is a problem with the performance of the device under test 500. The digital integrated circuit test apparatus 10 may store the comparison result. It will be appreciated that the vector data subunit 114 may send data information to the waveform comparator 218. The waveform comparator 218 is operable to generate the expected waveform signal. The expected waveform signal may be understood as a reference signal. The driving waveform signal sent by the waveform generator 216 is sent to the device under test 500 after passing through the channel switching module 300. The device under test 500 generates a response waveform signal when stimulated. The response waveform signal may carry information of the operating performance of the device under test 500. The response waveform signal may be fed back to the waveform comparator 218 after passing through the channel switching module 300. The response waveform signal may be compared to the expected waveform signal in the waveform comparator 218 to determine the performance of the device under test 500.
In one embodiment, the waveform generator 216 is connected to the waveform comparator 218, and the vector data subunit 114 is configured to enable the waveform comparator 218 to generate a desired waveform signal via the waveform generator 216. I.e., the data sent by the vector data subunit 114, is sent to the waveform comparator 218 via the waveform generator 216.
In one embodiment, the single-channel storage unit 110 further includes a result storage subunit 116. The result storage subunit 116 is connected to the waveform comparator 218. The result storage subunit 116 is configured to store a comparison result of the expected waveform signal and the response waveform signal. It is understood that each of the single-channel storage units 110 may include one of the result storage sub-units 116. Each of the result storage sub-units 116 may be configured to store a comparison result of the expected waveform signal and the response waveform signal. The comparison may reflect the performance of the device under test 500. In one embodiment, the comparison results may be read back at any time as needed.
In one embodiment, the result storage subunit 116 may be configured to store only the error result after comparing the expected waveform signal and the response waveform signal. The erroneous result is a result of the expected waveform signal and the response waveform signal being relatively inconsistent. It will be appreciated that storing only the erroneous result saves storage space in the result storage subunit 116. And the performance problem of the device under test 500 can be analyzed by analyzing the error result. Therefore, the result storage subunit 116 may be used to store only the error result after comparing the expected waveform signal with the response waveform signal, and may also store all the comparison results, so as to make the analysis data more detailed.
In one embodiment, the digital integrated circuit test device 10 further comprises a level driven comparison circuit 400. The level driving comparison circuit 400 is connected to the channel switching module 300 and the device under test 500. The level driving comparison circuit 400 can be used to level-convert the driving waveform signal output by the control module 200 into a level signal required by the device under test 500. After the device under test 500 is excited by the level signal, the generated response waveform signal passes through the level driving comparison circuit 400, and the response waveform signal is compared with a preset threshold signal. And outputting a high level or low level signal to the channel switching module 300 according to the comparison result, and sending the high level or low level signal to the control module 200 through the channel switching module 300.
Referring to fig. 3, in one embodiment, the channel switching module 300 includes a plurality of first multiplexers 310 and a plurality of second multiplexers 320. The plurality of first multiplexers 310 and the plurality of second multiplexers 320 are connected to the level driving comparison circuit 400. The plurality of first multiplexers 310 and the plurality of second multiplexers 320 are respectively connected with the device under test 500 through the level driving comparison circuit 400. The plurality of first multiplexers 310 and the plurality of second multiplexers 320 are also respectively connected with the control module 200. Each of the first multiplexers 310 is used for selecting one of the driving waveform signals generated by the control module 200 to be transmitted to the device under test 500 through the level driving comparison circuit 400. Each of the second multiplexers 320 is used for selecting one of the response waveform signals returned from the level-driven comparison circuit 400 to be sent to the control module 200. Wherein the response waveform signal is obtained by the device under test 500 under the excitation of the driving waveform signal.
It is to be understood that the plurality of first multiplexers 310 and the plurality of second multiplexers 320 are each data selectors. Each of the first multiplexers 310 and each of the second multiplexers 320 may have a plurality of input terminals and an output terminal. Each of the first multiplexers 310 and each of the second multiplexers 320 may receive a plurality of signals and select one signal to transmit.
The first multiplexer 310 and the second multiplexer 320 each include a plurality of circuits, and any one of the circuits can be selected to be connected as required. Each of the first multiplexers 310 and each of the second multiplexers 320 may select different circuits to communicate with each other according to requirements. For example, a first multiplexer may select drive waveform 4 for output to channel IO [1], and a second first multiplexer may select drive waveform 8 for output to channel IO [2 ]; similarly, the first second multiplexer can select channel IO [2] to output to compare waveform 1, and the second multiplexer can select channel IO [3] to output to compare waveform 2. It is to be understood that the driving waveform is the driving waveform signal and the comparison waveform is the response waveform signal.
After the control module 200 generates the driving waveform signal, the first multiplexer 310 may be controlled to enable a certain path of the driving waveform signal to form a connection relationship through a certain channel to test the device 500 under test. It is understood that the input terminal of the first multiplexer 310 may be plural, and thus may receive plural driving waveform signals. By the control of the first multiplexer 310, different driving waveform signals can be selected and output to the device under test 500. The device under test 500 generates the response waveform signal when stimulated by the driving waveform signal. The response waveform signal may be re-transmitted to the control module 200 through the second multiplexer 320, and the response waveform signal and the expected waveform signal may be compared at the control module 200. It is understood that there may be a plurality of inputs of each of the second multiplexers 320. That is, each of the second multiplexers 320 may input a plurality of the response waveform signals. Each of the second multiplexers 320 may select a different one of the response waveform signals to pass through and enter the control module 200 as desired.
In one embodiment, each of the first multiplexers 310 is controlled by a drive select signal. That is, the driving selection signal may control a specific one of the first multiplexers 310 to select a channel. The control data of the driving selection signal may be preset.
In one embodiment, each of the second multiplexers 320 is controlled by a comparison selection signal. I.e. the comparison select signal may control the second multiplexer 320 to select a certain channel. The control logic for comparing the selection signals may be preset.
In one embodiment, the control module 200 includes N of the single channel control circuits 210. The storage module 100 includes N single-channel storage units 110. The channel switching module 300 includes N first multiplexers 310 and N second multiplexers 320. Wherein N is an integer of 1 or more. The single channel control circuit 210, the storage module 100, the first multiplexer 310, and the second multiplexer 320 are connected as required by presetting a selection signal. Therefore, the signal path in the logic and the channel on the hardware can be flexibly configured, and the applicability of the digital integrated circuit testing device 10 is improved.
The embodiment of the application also provides a digital integrated circuit test system. The digital integrated circuit test system comprises the digital integrated circuit test device 10. The digital integrated circuit test system also comprises a control terminal. The control terminal can be a single chip microcomputer, an upper computer, a cloud end or a computer. The control terminal is connected with the digital integrated circuit testing device 10 through a bus.
The control terminal is connected with the storage module, the control module and the channel switching module through buses. The control terminal is used for realizing data interaction with the storage module, the control module and the channel switching module. It is understood that the control terminal can interact with other modules through one bus module. The control terminal can interact control data and vector data with the storage module through a bus. The control terminal can interact initialization data and preparation data before testing with the control module through a bus. The control terminal can interact the selection data of channel switching with the channel switching module through a bus. The control terminal is also connected to the level-driven comparison circuit 400 through a bus, and the level-driven comparison circuit 400 can be configured with relevant data through the control terminal.
It is understood that the control terminal may be used to pre-program the digital integrated circuit test apparatus 10 to control the different channels of the digital integrated circuit test apparatus 10 to start or stop independently. The control terminal writes different data into the single-channel storage unit 110, that is, different single-channel storage units 110 may control the corresponding clock generator 212 and the rate and address generator 214 to operate at different rates, different start addresses, and different clocks. Different single-channel storage units 110 in the storage module 100 can independently store vectors of different formats, store and read vectors from different initial positions, and run different instructions. Therefore, each channel of the digital integrated circuit test system can be flexibly configured, and the applicability of the digital integrated circuit test system is improved.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A digital integrated circuit testing apparatus, comprising:
a storage module comprising a plurality of single-channel storage cells;
the control module comprises a plurality of single-channel control circuits, and the plurality of single-channel storage units are connected with the plurality of single-channel control circuits in a one-to-one correspondence manner; and
and the channel switching module is connected with the plurality of single-channel control circuits and is used for connecting the tested device.
2. The digital integrated circuit test device of claim 1, wherein the single channel storage unit comprises a control data subunit, the single channel control circuit comprises a clock generator and a rate and address generator connected to each other, the control data subunit is connected to the clock generator and the rate and address generator respectively, and the control data subunit is used for controlling the rate and address generator to generate the rate and access addresses and controlling the clock generator to generate the clock signal together with the rate and address generator.
3. The digital integrated circuit test apparatus of claim 2, wherein the single channel storage unit includes a vector data subunit, the single channel control circuit includes a waveform generator, the vector data subunit is coupled to the waveform generator, the clock generator is coupled to the waveform generator, the waveform generator is coupled to the channel switching module, and clock signals generated by the vector data subunit and the clock generator are used to cause the waveform generator to send driving waveform signals to the channel switching module.
4. The digital integrated circuit testing apparatus of claim 3, wherein the single channel control circuit comprises a waveform comparator, the vector data subunit being coupled to the waveform comparator, the vector data subunit being configured to cause the waveform comparator to generate a desired waveform signal, the waveform comparator being further coupled to the channel switching module to receive a response waveform signal, the response waveform signal being derived by the device under test when stimulated by the drive waveform signal.
5. The digital integrated circuit test apparatus of claim 4, wherein the waveform generator is coupled to the waveform comparator, the vector data subunit being configured to cause the waveform comparator to generate a desired waveform signal via the waveform generator.
6. The digital integrated circuit test apparatus of claim 4, wherein the single channel storage unit further comprises a result storage subunit connected to the waveform comparator for storing a result of the comparison of the expected waveform signal and the response waveform signal.
7. The digital integrated circuit test apparatus of claim 6, wherein the result storage subunit is configured to store an error result after comparing the expected waveform signal and the response waveform signal.
8. The digital integrated circuit test apparatus of claim 1, further comprising a level-driven comparison circuit connected to the channel switching module and the device under test.
9. The digital integrated circuit test apparatus of claim 8, wherein the channel switching module comprises a plurality of first multiplexers and a plurality of second multiplexers, the plurality of first multiplexers and the plurality of second multiplexers being connected to the level-driven comparison circuit, the plurality of first multiplexers and the plurality of second multiplexers being further connected to the control module;
each first multiplexer is used for selecting one of a plurality of driving waveform signals generated by the control module to be sent to the tested device through the level driving comparison circuit; each second multiplexer is used for selecting one of a plurality of response waveform signals returned from the level driving comparison circuit to be sent to the control module, wherein the response waveform signals are obtained by the tested device under the excitation of the driving waveform signals.
10. A digital integrated circuit test system, comprising:
a digital integrated circuit test apparatus as claimed in any one of claims 1 to 9;
and the control terminal is connected with the storage module, the control module and the channel switching module through buses and is used for realizing data interaction with the storage module, the control module and the channel switching module.
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| CN116860536A (en) * | 2023-09-05 | 2023-10-10 | 武汉凌久微电子有限公司 | Rapid FT test system, test equipment and test method of GPU chip |
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| CN116860536A (en) * | 2023-09-05 | 2023-10-10 | 武汉凌久微电子有限公司 | Rapid FT test system, test equipment and test method of GPU chip |
| CN116860536B (en) * | 2023-09-05 | 2023-11-28 | 武汉凌久微电子有限公司 | Rapid FT test system, test equipment and test method of GPU chip |
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