CN115877914B - Signal control method, sampling method, device, system and electronic equipment - Google Patents
Signal control method, sampling method, device, system and electronic equipment Download PDFInfo
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Abstract
The disclosure provides a signal control method, a sampling method, a device, a system and electronic equipment, and aims to ensure that a controller can accurately sample a data signal and control the period of a clock signal not to be larger. In the present disclosure, for each alternative offset time, performing offset configuration on the control clock signal by using the alternative offset time, performing data sampling based on the control clock signal after offset configuration, and if the data is correctly sampled, determining the alternative offset time as a candidate offset time; and under the condition that a plurality of candidate offset times exist, determining the optimal offset time from all the candidate offset times according to the ratio of the clock frequency of the master clock signal to the clock frequency of the control clock signal, and performing offset configuration on the control clock signal by utilizing the optimal offset time.
Description
Technical Field
The present disclosure relates to the field of clock signal control technologies, and in particular, to a method for controlling a control clock signal, a method for sampling firmware data, a device for controlling a control clock signal, a device for sampling firmware data, a graphics processing system, and an electronic device.
Background
In the related art, various controllers within a chip need to read data from a storage medium inside or outside the chip during the start-up or operation of the chip, specifically, at each falling edge or rising edge of a control clock signal, the data signal is updated to the next data, in other words, the data is maintained for one control clock period until the falling edge or rising edge of the next control clock signal comes, so that the controller needs to correctly sample the data signal once in each control clock signal.
However, if the delay from the controller's control clock generator to the storage medium and from the storage medium to the controller's data sampling module is large, the control clock period needs to be long enough to ensure that the controller can accurately sample the data signal. But if the control clock period is large, the data reading efficiency is affected.
Disclosure of Invention
The invention aims to provide a method for controlling a control clock signal, a method for sampling firmware data, a device for controlling the control clock signal, a device for sampling the firmware data, a graphics processing system and electronic equipment, and aims to ensure that a controller can accurately sample the data signal and the period of the control clock signal is not larger.
According to one aspect of the present disclosure, there is provided a method of controlling a control clock signal, the method comprising:
determining a plurality of alternative offset times; the plurality of alternative offset times are in an arithmetic sequence, and the difference value of two adjacent alternative offset times is equal to the clock period of the main clock signal; the clock period of the control clock signal is N times of the clock period of the main clock signal, and N is an integer greater than or equal to 2;
performing offset configuration on the control clock signal by utilizing the alternative offset time for each alternative offset time, performing data sampling on the control clock signal after the offset configuration, and determining the alternative offset time as a candidate offset time if the data is correctly sampled;
when there are a plurality of candidate offset times, the optimal offset time is determined from all the candidate offset times according to the ratio of the clock frequency of the master clock signal to the clock frequency of the control clock signal, and the control clock signal is offset configured by using the optimal offset time.
In one possible implementation of the present disclosure, the clock frequency of the control clock signal is equal to the update frequency of the data signal to be sampled.
In one possible implementation of the present disclosure, the step of determining a plurality of alternative offset times includes:
And determining N+1 alternative offset times according to the ratio N of the clock period of the control clock signal to the clock period of the main clock signal, wherein the first alternative offset time is 0.
In one possible implementation of the present disclosure, the step of determining the optimal offset time from all candidate offset times according to a ratio of a clock frequency of the master clock signal to a clock frequency of the control clock signal includes:
rounding up or rounding down for one half of the ratio of the clock frequency of the master clock signal to the clock frequency of the control clock signal to obtain an integer m;
under the condition that the minimum candidate offset time in all candidate offset times is equal to 0, judging whether the subtraction result of the ratio Tmax and the integer m is larger than 0, wherein the ratio Tmax is the ratio of the maximum candidate offset time to the clock period of the master clock signal; if yes, determining the optimal offset time according to the subtraction result; if not, determining the optimal offset time to be 0;
judging whether the ratio Tmin of the minimum candidate offset time to the clock period of the master clock signal is larger than an integer m or not under the condition that the maximum candidate offset time in all the candidate offset times is equal to the clock period of the control clock signal; if yes, determining the clock period of the control clock signal as the optimal offset time; if not, determining the optimal offset time according to the addition result of the ratio Tmin and the integer m.
According to another aspect of the present disclosure, there is also provided a method of sampling firmware data, the method including:
for each of a plurality of alternative offset times, performing offset configuration on a control clock signal of a sampling controller by using the alternative offset time, sampling target data based on the control clock signal after offset configuration, and if the target data is correctly sampled, determining the alternative offset time as a candidate offset time;
in the case that a plurality of candidate offset times exist, determining the optimal offset time from all the candidate offset times according to the ratio of the clock frequency of the master clock signal to the clock frequency of the control clock signal;
and performing offset configuration on the control clock signal by utilizing the optimal offset time, and sampling the firmware data based on the control clock signal after offset configuration.
In one possible implementation of the present disclosure, the clock frequency of the control clock signal is equal to the update frequency of the firmware data signal.
In one possible implementation of the present disclosure, the plurality of alternative offset times are in an arithmetic series, and a difference between two adjacent alternative offset times is equal to a clock period of the master clock signal; the clock period of the control clock signal is N times the clock period of the master clock signal, N being an integer greater than or equal to 2.
In a possible implementation manner of the present disclosure, the method further includes:
a plurality of alternative offset times are determined according to the ratio of the clock period of the control clock signal to the clock period of the master clock signal, wherein the first alternative offset time is equal to 0 and the last alternative offset time is equal to the clock period of the control clock signal.
In one possible implementation of the present disclosure, the step of determining the optimal offset time from all candidate offset times according to a ratio of a clock frequency of the master clock signal to a clock frequency of the control clock signal includes:
rounding up or rounding down for one half of the ratio of the clock frequency of the master clock signal to the clock frequency of the control clock signal to obtain an integer m;
under the condition that the minimum candidate offset time in all candidate offset times is equal to 0, judging whether the subtraction result of the ratio Tmax and the integer m is larger than 0, wherein the ratio Tmax is the ratio of the maximum candidate offset time to the clock period of the master clock signal; if yes, determining the optimal offset time according to the subtraction result; if not, determining the optimal offset time to be 0;
judging whether the ratio Tmin of the minimum candidate offset time to the clock period of the master clock signal is larger than an integer m or not under the condition that the maximum candidate offset time in all the candidate offset times is equal to the clock period of the control clock signal; if yes, determining the clock period of the control clock signal as the optimal offset time; if not, determining the optimal offset time according to the addition result of the ratio Tmin and the integer m.
In one possible implementation of the present disclosure, before the offset configuration of the control clock signal with the alternative offset time, the method further includes:
after the chip is electrified, sampling target data based on a control clock signal with a preset clock frequency, and storing the target data;
for each of a plurality of alternative offset times, performing offset configuration on a control clock signal of a sampling controller by using the alternative offset time, and performing target data sampling based on the control clock signal after offset configuration, if the target data is correctly sampled, determining the alternative offset time as a candidate offset time includes:
switching the clock frequency of the control clock signal from a preset clock frequency to a target clock frequency, wherein the target clock frequency is higher than the preset clock frequency;
for each of a plurality of alternative offset times, performing offset configuration on a control clock signal of a target clock frequency by using the alternative offset time, sampling target data based on the control clock signal after offset configuration, comparing the sampled target data with stored target data, if the sampled target data and the stored target data are equal, determining that the target data are correctly sampled, and determining the alternative offset time as a candidate offset time;
The step of performing offset configuration on the control clock signal by using the optimal offset time and sampling the firmware data based on the control clock signal after offset configuration comprises the following steps:
and performing offset configuration on the control clock signal under the target frequency by utilizing the optimal offset time, and sampling the firmware data based on the control clock signal after offset configuration.
In one possible implementation of the present disclosure, the target data is ID data of a firmware data storage device.
In one possible implementation of the present disclosure, when sampling target data based on a control clock signal after offset configuration, the target data is updated based on an original control clock signal; when the firmware data is sampled based on the control clock signal after the offset configuration, the firmware data is updated based on the original control clock signal.
According to another aspect of the present disclosure, there is also provided an apparatus for controlling a control clock signal, the apparatus including:
an alternative offset time determining module for determining a plurality of alternative offset times; the plurality of alternative offset times are in an arithmetic sequence, and the difference value of two adjacent alternative offset times is equal to the clock period of the main clock signal; the clock period of the control clock signal is N times of the clock period of the main clock signal, and N is an integer greater than or equal to 2;
The candidate offset time determining module is used for performing offset configuration on the control clock signal by utilizing each candidate offset time, performing data sampling on the control clock signal after the offset configuration, and determining the candidate offset time as a candidate offset time if the data is correctly sampled;
and the optimal offset time determining module is used for determining the optimal offset time from all the candidate offset times according to the ratio of the clock frequency of the master clock signal to the clock frequency of the control clock signal under the condition that a plurality of candidate offset times exist, and performing offset configuration on the control clock signal by utilizing the optimal offset time.
According to another aspect of the present disclosure, there is also provided an apparatus for sampling firmware data, the apparatus including:
the candidate offset time determining module is used for performing offset configuration on the control clock signal of the sampling controller according to each of a plurality of candidate offset times, performing target data sampling based on the control clock signal after offset configuration, and determining the candidate offset time as a candidate offset time if the target data is correctly sampled;
The optimal offset time determining module is used for determining the optimal offset time from all candidate offset times according to the ratio of the clock frequency of the master clock signal to the clock frequency of the control clock signal under the condition that a plurality of candidate offset times exist;
the firmware data adopting module is used for carrying out offset configuration on the control clock signal by utilizing the optimal offset time and sampling the firmware data based on the control clock signal after the offset configuration.
According to another aspect of the present disclosure, there is also provided a graphics processing system including the above-described apparatus for controlling a control clock signal, or including the above-described apparatus for sampling firmware data. In some use cases, the product form of the graphics processing system is embodied as a graphics card; in other use cases, the product form of the graphics processing system is embodied as a CPU motherboard.
According to another aspect of the present disclosure, there is also provided an electronic device including the graphics processing system described above. In some use scenarios, the product form of the electronic device is a portable electronic device, such as a smart phone, a tablet computer, a VR device, etc.; in some use cases, the electronic device is in the form of a personal computer, a game console, or the like.
Drawings
FIG. 1 is a schematic diagram of a related art chip reading firmware data;
FIG. 2 is a diagram showing the updating of data signals in the related art;
FIG. 3 is a flow chart of a method for controlling a control clock signal according to an embodiment of the present disclosure;
FIG. 4 is a flow chart of a method for sampling firmware data according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of sampling firmware data provided by an embodiment of the present disclosure;
FIG. 6 is an apparatus for controlling a control clock signal provided by an embodiment of the present disclosure;
fig. 7 is an apparatus for sampling firmware data according to an embodiment of the present disclosure.
Detailed Description
Before describing embodiments of the present disclosure, it should be noted that:
some embodiments of the disclosure are described as process flows, in which the various operational steps of the flows may be numbered sequentially, but may be performed in parallel, concurrently, or simultaneously.
The terms "first," "second," and the like may be used in embodiments of the present disclosure to describe various features, but these features should not be limited by these terms. These terms are only used to distinguish one feature from another.
The term "and/or," "and/or" may be used in embodiments of the present disclosure to include any and all combinations of one or more of the associated features listed.
It will be understood that when two elements are described in a connected or communicating relationship, unless a direct connection or direct communication between the two elements is explicitly stated, connection or communication between the two elements may be understood as direct connection or communication, as well as indirect connection or communication via intermediate elements.
In order to make the technical solutions and advantages of the embodiments of the present disclosure more apparent, the following detailed description of exemplary embodiments of the present disclosure is provided in conjunction with the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present disclosure, not all embodiments of which are exhaustive. It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other.
In the related art, various controllers within a chip need to read data from a storage medium inside or outside the chip during the start-up or operation of the chip. As shown in fig. 1, taking an example that executable firmware data needs to be read from a storage medium outside the chip and put into SRAM or DRAM inside the chip for execution in the on-chip power-on stage, the SPI (Serial Perripheral Interface, serial peripheral interface) controller in fig. 1 includes a control clock generator spi_sck and a data sampling module spi_si, which are all registers in practice. Executable firmware data is stored in the storage medium Flash outside the chip. After the chip is powered up, as shown in fig. 2, the data signal is updated to the next data on each falling edge of the control clock signal SCK. In other words, the data will remain for one SCK period until the next SCK falling edge. The SPI controller needs to sample the data signal correctly once per SCK period.
However, as shown in FIG. 1, in reading executable firmware data, the data path delays include: chip output delay Pad0, PCB Board level delay Board0, flash internal response delay Tflash, PCB Board level delay Board1 and chip input delay Pad1. To ensure chip start-up stability, the frequency of the control clock signal must not be too high, i.e. the period of the control clock signal needs to be large enough, at least greater than the total data path delay, to allow the input data to remain long enough to be sampled correctly. However, decreasing the frequency of the control clock signal affects the data reading efficiency, thereby increasing the chip start time. It should be noted that, the related art shown in fig. 1 is only understood as the background art of the present disclosure, but the related art shown in fig. 1 is not directly understood as the disclosed prior art.
The invention aims to provide a method for controlling a control clock signal, a method for sampling firmware data, a device for controlling the control clock signal, a device for sampling the firmware data, a graphics processing system and electronic equipment, and aims to ensure that a controller can accurately sample the data signal and the period of the control clock signal is not larger.
Referring to fig. 3, fig. 3 is a flowchart of a method for controlling a control clock signal according to an embodiment of the disclosure. As shown in fig. 3, the method comprises the steps of:
s310: determining a plurality of alternative offset times; the plurality of alternative offset times are in an arithmetic sequence, and the difference value of two adjacent alternative offset times is equal to the clock period of the main clock signal; the clock period of the control clock signal is N times the clock period of the master clock signal, N being an integer greater than or equal to 2.
In the present disclosure, the control clock signal may be generated by a control clock generator of a controller (for example, the SPI controller) in the chip, and the control clock generator takes the master clock signal clk as an input, and generates the control clock signal according to the master clock signal clk. For example, the frequency of the master clock signal is 600MHz, the control clock generator takes the master clock signal as an input, and outputs the control clock signal after dividing it by six, the frequency of the control clock signal is 100MHz, and the clock period of the control clock signal is 6 times that of the master clock signal.
In some embodiments of the present disclosure, the clock frequency of the control clock signal is equal to the update frequency of the data signal to be sampled. In particular, the storage medium storing the data to be sampled takes as input a control clock signal, and updates the data to be sampled once on each rising or falling edge of the control clock signal.
In some embodiments of the present disclosure, the step of determining a plurality of alternative offset times comprises: and determining N+1 alternative offset times according to the ratio N of the clock period of the control clock signal to the clock period of the main clock signal, wherein the first alternative offset time is 0.
For ease of understanding, continuing with the description of the frequency of the master clock signal being 600MHz and the frequency of the control clock signal being 100MHz, the ratio of the clock period of the control clock signal to the clock period of the master clock signal is equal to 6, thus determining 7 alternative offset times, which are 0, 1T, 2T, 3T, 4T, 5T, 6T in order from small to large, where T is equal to the clock period of the master clock signal, i.e., 1/600MHz seconds.
S320: and for each alternative offset time, performing offset configuration on the control clock signal by using the alternative offset time, sampling data based on the control clock signal after offset configuration, and determining the alternative offset time as a candidate offset time if the data is correctly sampled.
In some embodiments of the present disclosure, the control clock signal is configured with an offset using the alternative offset time, which may specifically be configured with an offset of the phase of the control clock signal. In other words, the control clock signal is delayed with the alternative offset time. For ease of understanding, the description will be continued with the frequency of the master clock signal being 600MHz and the frequency of the control clock signal being 100 MHz. When the alternative offset time is equal to 0, the control clock signal is not actually delayed. When the alternative offset time is equal to 1T, the control clock signal needs to be delayed by IT, i.e. the control clock signal after the offset configuration is delayed by 1 period of the master clock signal compared to the original control clock signal. When the alternative offset time is equal to 2T, the control clock signal needs to be delayed by 2T, i.e. the control clock signal after the offset configuration is delayed by 2 cycles of the master clock signal compared to the original control clock signal, and so on.
After the control clock signal is offset configured with the alternative offset time, the preset data may be read from the target storage medium based on the offset configured control clock signal. The target storage medium is used for storing target data which needs a lot of processing later, for example, the target storage medium can be an off-chip Flash memory Flash for storing firmware. The preset data is data with a data volume far smaller than that of the target data, for example, the preset data may be ID information of the Flash memory. It should be noted that, since the objective of S320 is to verify which alternative offset times can support correct sampling into data, the data amount of the preset data does not need to be too large.
After the control clock signal after offset configuration is sampled to the preset data, the sampled preset data can be compared with the pre-stored and accurate preset data, and if the sampled preset data and the pre-stored and accurate preset data are equal, the current control clock signal is correctly sampled to the data.
S330: when there are a plurality of candidate offset times, the optimal offset time is determined from all the candidate offset times according to the ratio of the clock frequency of the master clock signal to the clock frequency of the control clock signal, and the control clock signal is offset configured by using the optimal offset time.
In the present disclosure, when there is only one candidate offset time, the control clock signal is offset configured directly by using the candidate offset time.
In the present disclosure, a plurality of candidate offset times are determined, each candidate offset time is utilized to perform offset configuration on a control clock signal, so that a data sampling test is performed based on the control clock signal after offset configuration, if data can be correctly sampled, the current candidate offset time is determined to be an offset time capable of supporting correct data sampling, so that the current candidate offset time is determined to be a candidate offset time, and finally, one candidate offset time is selected from the determined candidate offset times as an optimal offset time to perform offset configuration on the control clock signal.
According to the method, the offset configuration is carried out on the control clock signal, and the control clock signal after the offset configuration can support correct sampling of target data without reducing the frequency of the control clock signal. Therefore, the method and the device can ensure that the controller can accurately sample the target data and meanwhile, the period of the control clock signal is not larger.
In addition, in the present disclosure, when there are multiple candidate offset times, the optimal offset time is further determined from the multiple candidates according to the ratio of the clock frequency of the master clock signal to the clock frequency of the control clock signal, so as to further improve the sampling effect of the target data.
In some embodiments of the present disclosure, determining the optimal offset time from all candidate offset times based on a ratio of a clock frequency of the master clock signal to a clock frequency of the control clock signal includes:
s330-1: and rounding up or rounding down for one half of the ratio of the clock frequency of the master clock signal to the clock frequency of the control clock signal to obtain an integer m.
S330-2: under the condition that the minimum candidate offset time in all candidate offset times is equal to 0, judging whether the subtraction result of the ratio Tmax and the integer m is larger than 0, wherein the ratio Tmax is the ratio of the maximum candidate offset time to the clock period of the master clock signal; if yes, determining the optimal offset time according to the subtraction result; if not, the optimal offset time is determined to be 0.
S330-3: judging whether the ratio Tmin of the minimum candidate offset time to the clock period of the master clock signal is larger than an integer m or not under the condition that the maximum candidate offset time in all the candidate offset times is equal to the clock period of the control clock signal; if yes, determining the clock period of the control clock signal as the optimal offset time; if not, determining the optimal offset time according to the addition result of the ratio Tmin and the integer m.
For ease of understanding, the description will be continued with the frequency of the master clock signal being 600MHz and the frequency of the control clock signal being 100 MHz.
Firstly, calculating the ratio of the clock frequency 600MHz of the main clock signal to the ratio of the clock frequency of the control clock signal of 100MHz, wherein the ratio is equal to 6, and then carrying out up rounding or down rounding on one half of 6 to obtain an integer m, wherein the integer m is equal to 3.
Then, if the candidate offset times of 0, 1T, 2T, 3T, 4T, 5T, and 6T are tested in sequence, the determined candidate offset times are 0, 1T, and 2T. Then, since the minimum candidate offset time is equal to 0, tmax is calculated, which is equal to the maximum candidate offset time 2T divided by the clock period T of the master clock signal, i.e., tmax is equal to 2, and the integer m is subtracted from Tmax to obtain a subtraction result equal to-1, the subtraction result is not greater than 0, and thus the optimum offset time is determined to be 0.
It should be noted that, data sampling is performed at the center time of the data stabilization period, so that the data can be kept stable for a long time before and after sampling, and the data sampling effect can be improved. When the candidate offset time is 0, 1T, 2T, the maximum offset of the data can be correctly sampled by 2T, which is equivalent to the upper boundary of the data stabilization period, and the total duration of the data stabilization period is equal to the period of the control clock signal (i.e. 1/100MHz, that is, 6T), so that 0 is closest to the center time of the data stabilization period in the candidate offset times 0, 1T, 2T, so that 0 is selected as the optimal offset time, and the data can be kept stable for a long period of time before and after sampling, thereby improving the data sampling effect.
Or if the candidate offset times are tested in sequence for 0, 1T, 2T, 3T, 4T, 5T, 6T, the candidate offset times are determined to be 0, 1T, 2T, 3T, 4T. Then, since the minimum candidate offset time is equal to 0, tmax is calculated, where Tmax is equal to the maximum candidate offset time 4T divided by the clock period T of the master clock signal, that is, tmax is equal to 4, and the integer m is subtracted from Tmax to obtain a subtraction result equal to 1, and the subtraction result is greater than 0, so that the optimum offset time is determined according to the subtraction result, that is, the optimum offset time is 1T.
It should be noted that, data sampling is performed at the center time of the data stabilization period, so that the data can be kept stable for a long time before and after sampling, and the data sampling effect can be improved. When the candidate offset time is 0, 1T, 2T, 3T, 4T, the maximum offset of the data can be correctly sampled by 4T, which is equivalent to the upper boundary of the data stabilization period, and the total duration of the data stabilization period is equal to the period of the control clock signal (i.e. 1/100MHz, that is, 6T), so that 1T is closest to the center time of the data stabilization period in the candidate offset times 0, 1T, 2T, 3T, 4T, and 1T is selected as the optimal offset time, so that the data can be kept stable for a longer period of time before and after sampling, thereby improving the data sampling effect.
Or if the candidate offset times are tested in sequence for 0, 1T, 2T, 3T, 4T, 5T, 6T, the candidate offset times are determined to be 2T, 3T, 4T, 5T, 6T. Then, since the maximum candidate offset time 6T is equal to the clock period of the control clock signal, tmin is calculated as the minimum candidate offset time 2T divided by the clock period T of the master clock signal, i.e. Tmin is equal to 2, and since Tmin is not greater than m, the optimum offset time is determined from the addition of the ratio Tmin to the integer m, i.e. the optimum offset time is equal to (tmin+m) T, i.e. 5T.
It should be noted that, data sampling is performed at the center time of the data stabilization period, so that the data can be kept stable for a long time before and after sampling, and the data sampling effect can be improved. When the candidate offset time is 2T, 3T, 4T, 5T, 6T, the minimum offset that can correctly sample the data is 2T, which is equivalent to the lower boundary of the data stabilization period, and the total duration of the data stabilization period is equal to the period of the control clock signal (i.e. 1/100MHz, that is, 6T), so that the candidate offset time is 2T, 3T, 4T, 5T, 6T, and 5T is closest to the central moment of the data stabilization period, so that the 5T is selected as the optimal offset time, so that the data can be kept stable for a longer period of time before and after sampling, and the data sampling effect is improved.
Or if the candidate offset times are tested for 0, 1T, 2T, 3T, 4T, 5T, 6T in sequence, the candidate offset times are determined to be 5T, 6T. Then Tmin is calculated as the minimum candidate offset time 5T divided by the clock period T of the master clock signal, i.e. Tmin is equal to 5, since the maximum candidate offset time 6T is equal to the clock period of the control clock signal, and the optimum offset time is determined as the clock period of the control clock signal, i.e. 6T, since Tmin is greater than m.
It should be noted that, data sampling is performed at the center time of the data stabilization period, so that the data can be kept stable for a long time before and after sampling, and the data sampling effect can be improved. When the candidate offset time is 5T or 6T, the minimum offset of the data can be correctly sampled by 5T, which is equivalent to the lower boundary of the data stabilization period, and the total duration of the data stabilization period is equal to the period of the control clock signal (i.e. 1/100MHz, that is, 6T), so that 6T is closest to the center time of the data stabilization period in the candidate offset times 5T and 6T, and therefore 6T is selected as the optimal offset time, so that the data can be kept stable for a long period of time before and after sampling, and the data sampling effect is improved.
In the above, the present disclosure provides, by one or more embodiments, one or more methods of controlling a control clock signal. In the following, the present disclosure proposes a method of sampling firmware data based on the same inventive concept. It should be noted that, since the following firmware data sampling method and the control method for controlling the control clock signal are based on the same inventive concept, in order to avoid repetition, in the following embodiments, a part of the content of the firmware data sampling method is briefly described, and the related embodiments may refer to the control method for controlling the control clock signal.
Referring to fig. 4, fig. 4 is a flowchart of a method for sampling firmware data according to an embodiment of the present disclosure. As shown in fig. 4, the method comprises the steps of:
step S410: for each of a plurality of alternative offset times, performing offset configuration on a control clock signal of the sampling controller by using the alternative offset time, and performing target data sampling based on the control clock signal after offset configuration, if the target data is correctly sampled, determining the alternative offset time as a candidate offset time.
Step S420: in the case where there are a plurality of candidate offset times, the optimum offset time is determined from all the candidate offset times according to the ratio of the clock frequency of the master clock signal to the clock frequency of the control clock signal.
Step S430: and performing offset configuration on the control clock signal by utilizing the optimal offset time, and sampling the firmware data based on the control clock signal after offset configuration.
In the present disclosure, when there is only one candidate offset time, the control clock signal is offset configured directly by using the candidate offset time.
By executing the steps S410 to S430, the control clock signal is offset configured by using each candidate offset time, so that a data sampling test is performed based on the control clock signal after the offset configuration, if the data can be correctly sampled, the current candidate offset time is determined to be an offset time capable of supporting the correct sampling of the data, so that the current candidate offset time is determined to be a candidate offset time, and finally, one candidate offset time is selected from the determined candidate offset times as the optimal offset time to perform offset configuration on the control clock signal.
The firmware data is sampled in the mode, the frequency of the control clock signal does not need to be reduced, and the control clock signal is subjected to offset configuration, so that the control clock signal after offset configuration can support correct sampling of the firmware data. Therefore, the method and the device can ensure that the period of the control clock signal is not larger while ensuring that the controller can accurately sample the firmware data, thereby ensuring that the chip can be started efficiently and stably.
In addition, in the present disclosure, when there are multiple candidate offset times, the optimal offset time is further determined from the multiple candidates according to the ratio of the clock frequency of the master clock signal to the clock frequency of the control clock signal, so as to further improve the sampling effect of the firmware data.
In some embodiments of the present disclosure, the clock frequency of the control clock signal is equal to the update frequency of the firmware data signal. In particular, the storage medium for firmware data takes as input a control clock signal, and updates the firmware data once on each rising or falling edge of the control clock signal.
In some embodiments of the present disclosure, the plurality of alternative offset times are in an arithmetic series, and a difference between adjacent two alternative offset times is equal to a clock period of the master clock signal; the clock period of the control clock signal is N times the clock period of the master clock signal, N being an integer greater than or equal to 2.
In some embodiments of the present disclosure, the method further comprises: a plurality of alternative offset times are determined according to the ratio of the clock period of the control clock signal to the clock period of the master clock signal, wherein the first alternative offset time is equal to 0 and the last alternative offset time is equal to the clock period of the control clock signal.
In some embodiments of the present disclosure, determining the optimal offset time from all candidate offset times based on a ratio of a clock frequency of the master clock signal to a clock frequency of the control clock signal includes:
s420-1: and rounding up or rounding down for one half of the ratio of the clock frequency of the master clock signal to the clock frequency of the control clock signal to obtain an integer m.
S420-2: under the condition that the minimum candidate offset time in all candidate offset times is equal to 0, judging whether the subtraction result of the ratio Tmax and the integer m is larger than 0, wherein the ratio Tmax is the ratio of the maximum candidate offset time to the clock period of the master clock signal; if yes, determining the optimal offset time according to the subtraction result; if not, the optimal offset time is determined to be 0.
S420-3: judging whether the ratio Tmin of the minimum candidate offset time to the clock period of the master clock signal is larger than an integer m or not under the condition that the maximum candidate offset time in all the candidate offset times is equal to the clock period of the control clock signal; if yes, determining the clock period of the control clock signal as the optimal offset time; if not, determining the optimal offset time according to the addition result of the ratio Tmin and the integer m.
In some embodiments of the present disclosure, prior to offset configuring the control clock signal with the alternative offset time, the method further comprises: and after the chip is electrified, sampling target data based on a control clock signal with a preset clock frequency, and storing the target data.
The target data may be ID data of the firmware data storage device, and the preset clock frequency may be a lowest frequency supported by a controller (e.g., an SPI controller). For example, frequencies supported by the SPI controller include 17.5MHz, 50MHz and 100MHz, after the chip is powered on, based on a control clock signal of 17.5MHz, ID information of the Flash is Read from the off-chip Flash memory Flash by executing a Read ID command (i.e. Read ID command), and the ID information is stored. In the method, after the chip is powered on, the ID information is read back by using the control clock signal with the lowest frequency, so that the ID information can be ensured to be correctly read back due to the fact that the lowest frequency of the control clock corresponds to the longest clock period, and the ID data can be used as reference data in the subsequent test of the alternative offset time. On the other hand, the present disclosure does not store the ID data of the storage device in the chip in advance in a nonvolatile manner, but the chip needs to temporarily read the ID data from the off-chip Flash memory Flash after each power-on, so that the present disclosure can be flexibly applied to various types/types of off-chip Flash memory Flash, and is not limited to a certain type of off-chip Flash memory Flash.
In some embodiments of the present disclosure, when performing the step S410, the clock frequency of the control clock signal is specifically switched from the preset clock frequency to the target clock frequency, where the target clock frequency is higher than the preset clock frequency; and performing offset configuration on the control clock signal of the target clock frequency by utilizing each alternative offset time in the multiple alternative offset times, sampling target data based on the control clock signal after offset configuration, comparing the sampled target data with stored target data, determining that the target data is correctly sampled if the sampled target data and the stored target data are equal, and determining the alternative offset time as a candidate offset time.
In the execution of the above step S430, specifically, the control clock signal at the target frequency is offset configured by using the optimal offset time, and the firmware data is sampled based on the control clock signal after the offset configuration.
The target frequency refers to a frequency that is required to be used by the control clock signal when sampling the firmware data, so that the target frequency should be higher (or far higher) than a preset frequency in order to ensure firmware loading efficiency. For ease of understanding, continuing with the above example, frequencies supported by the SPI controller include 17.5MHz, 50MHz, and 100MHz. After ID information of the Flash memory outside the chip is read based on a control clock signal of 17.5MHz, the clock frequency of the control clock signal is switched from 17.5MHz to 100MHz, and then the control clock signal of 100MHz is offset configured by utilizing an alternative offset time, and a data sampling test is carried out. After the optimal offset time is determined, the control clock signal under 100MHz is offset configured by utilizing the optimal offset time, so that the firmware data is sampled based on the offset configured control clock signal.
In one possible implementation of the present disclosure, when sampling target data based on a control clock signal after offset configuration, the target data is updated based on an original control clock signal; when the firmware data is sampled based on the control clock signal after the offset configuration, the firmware data is updated based on the original control clock signal. In other words, the off-chip Flash memory Flash storing the target data and the firmware data always performs data update based on the original control clock signal, and the SPI controller samples the firmware data based on the control clock signal after offset configuration using the optimal offset time.
Referring to fig. 5, fig. 5 is a schematic diagram of sampling firmware data according to an embodiment of the present disclosure. In fig. 5, the optimal offset time generated by the test is equal to n master clock cycles, n is any integer greater than or equal to 0 and less than or equal to 6, and the offset configuration module generates the control clock signal SCK ' according to the optimal offset time, where the control clock signal SCK ' and the original control clock signal SCK are both 100MHz, but the control clock signal SCK ' is delayed by n master clock cycles (i.e. the optimal offset time) compared to the original control clock signal SCK. The original control clock signal SCK is used for controlling the off-chip Flash memory Flash to update the firmware data, and the control clock signal SCK' is used for controlling the data sampling module spi_si to sample the firmware data.
Referring to fig. 6, fig. 6 is an apparatus for controlling a control clock signal according to an embodiment of the present disclosure, the apparatus including:
an alternative offset time determination module 610 for determining a plurality of alternative offset times; the plurality of alternative offset times are in an arithmetic sequence, and the difference value of two adjacent alternative offset times is equal to the clock period of the main clock signal; the clock period of the control clock signal is N times the clock period of the master clock signal, N being an integer greater than or equal to 2.
The candidate offset time determining module 620 is configured to perform offset configuration on the control clock signal according to each candidate offset time, perform data sampling based on the control clock signal after the offset configuration, and determine the candidate offset time as a candidate offset time if the data is correctly sampled.
The best offset time determining module 630 is configured to determine, when there are a plurality of candidate offset times, the best offset time from all the candidate offset times according to a ratio of a clock frequency of the master clock signal to a clock frequency of the control clock signal, and perform offset configuration on the control clock signal using the best offset time.
In some embodiments of the present disclosure, the clock frequency of the control clock signal is equal to the update frequency of the data signal to be sampled.
In some embodiments of the present disclosure, the alternative offset time determination module 610 is specifically configured to, when determining a plurality of alternative offset times: and determining N+1 alternative offset times according to the ratio N of the clock period of the control clock signal to the clock period of the main clock signal, wherein the first alternative offset time is 0.
In some embodiments of the present disclosure, the optimal offset time determination module 630 is specifically configured to, when determining an optimal offset time from all candidate offset times based on a ratio of a clock frequency of the master clock signal to a clock frequency of the control clock signal: rounding up or rounding down for one half of the ratio of the clock frequency of the master clock signal to the clock frequency of the control clock signal to obtain an integer m; under the condition that the minimum candidate offset time in all candidate offset times is equal to 0, judging whether the subtraction result of the ratio Tmax and the integer m is larger than 0, wherein the ratio Tmax is the ratio of the maximum candidate offset time to the clock period of the master clock signal; if yes, determining the optimal offset time according to the subtraction result; if not, determining the optimal offset time to be 0; judging whether the ratio Tmin of the minimum candidate offset time to the clock period of the master clock signal is larger than an integer m or not under the condition that the maximum candidate offset time in all the candidate offset times is equal to the clock period of the control clock signal; if yes, determining the clock period of the control clock signal as the optimal offset time; if not, determining the optimal offset time according to the addition result of the ratio Tmin and the integer m.
Referring to fig. 7, fig. 7 is an apparatus for sampling firmware data according to an embodiment of the present disclosure, the apparatus including:
the candidate offset time determining module 710 is configured to perform offset configuration on the control clock signal of the sampling controller according to each of a plurality of candidate offset times, and perform target data sampling based on the control clock signal after offset configuration, and determine the candidate offset time as a candidate offset time if the target data is correctly sampled.
The best offset time determining module 720 is configured to determine the best offset time from all the candidate offset times according to a ratio of the clock frequency of the master clock signal to the clock frequency of the control clock signal when there are a plurality of candidate offset times.
The firmware data adoption module 730 is configured to perform offset configuration on the control clock signal by using the optimal offset time, and sample the firmware data based on the control clock signal after the offset configuration.
In some embodiments of the present disclosure, the clock frequency of the control clock signal is equal to the update frequency of the firmware data signal.
In some embodiments of the present disclosure, the plurality of alternative offset times are in an arithmetic series, and a difference between adjacent two alternative offset times is equal to a clock period of the master clock signal; the clock period of the control clock signal is N times the clock period of the master clock signal, N being an integer greater than or equal to 2.
In some embodiments of the present disclosure, the apparatus further comprises an alternative offset time determination module configured to determine a plurality of alternative offset times based on a ratio of a clock cycle of the control clock signal to a clock cycle of the master clock signal, wherein a first alternative offset time is equal to 0 and a last alternative offset time is equal to the clock cycle of the control clock signal.
In some embodiments of the present disclosure, the optimal offset time determination module 720 is specifically configured to: rounding up or rounding down for one half of the ratio of the clock frequency of the master clock signal to the clock frequency of the control clock signal to obtain an integer m; under the condition that the minimum candidate offset time in all candidate offset times is equal to 0, judging whether the subtraction result of the ratio Tmax and the integer m is larger than 0, wherein the ratio Tmax is the ratio of the maximum candidate offset time to the clock period of the master clock signal; if yes, determining the optimal offset time according to the subtraction result; if not, determining the optimal offset time to be 0; judging whether the ratio Tmin of the minimum candidate offset time to the clock period of the master clock signal is larger than an integer m or not under the condition that the maximum candidate offset time in all the candidate offset times is equal to the clock period of the control clock signal; if yes, determining the clock period of the control clock signal as the optimal offset time; if not, determining the optimal offset time according to the addition result of the ratio Tmin and the integer m.
In some embodiments of the present disclosure, the apparatus further includes a target data sampling module for sampling target data based on a control clock signal of a preset clock frequency and storing the target data.
The candidate offset time determination module 710 is specifically configured to: switching the clock frequency of the control clock signal from a preset clock frequency to a target clock frequency, wherein the target clock frequency is higher than the preset clock frequency; for each of a plurality of alternative offset times, performing offset configuration on a control clock signal of a target clock frequency by using the alternative offset time, sampling target data based on the control clock signal after offset configuration, comparing the sampled target data with stored target data, if the sampled target data and the stored target data are equal, determining that the target data are correctly sampled, and determining the alternative offset time as a candidate offset time.
The firmware data adoption module 730 specifically is configured to: and performing offset configuration on the control clock signal under the target frequency by utilizing the optimal offset time, and sampling the firmware data based on the control clock signal after offset configuration.
In some embodiments of the present disclosure, the target data is ID data of a firmware data storage device.
In one possible implementation of the present disclosure, when sampling target data based on a control clock signal after offset configuration, the target data is updated based on an original control clock signal; when the firmware data is sampled based on the control clock signal after the offset configuration, the firmware data is updated based on the original control clock signal.
The present disclosure also provides a graphics processing system including the above-described apparatus for controlling a control clock signal, or including the above-described apparatus for sampling firmware data. In some use cases, the product form of the graphics processing system is embodied as a graphics card; in other use cases, the product form of the graphics processing system is embodied as a CPU motherboard.
The disclosure also provides an electronic device comprising the graphics processing system. In some use scenarios, the product form of the electronic device is a portable electronic device, such as a smart phone, a tablet computer, a VR device, etc.; in some use cases, the electronic device is in the form of a personal computer, a game console, or the like.
While the preferred embodiments of the present disclosure have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the disclosure.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present disclosure without departing from the spirit or scope of the disclosure. Thus, the present disclosure is intended to include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (16)
1. A method of controlling a control clock signal, the method comprising:
determining a plurality of alternative offset times; the plurality of alternative offset times are in an arithmetic sequence, and the difference value of two adjacent alternative offset times is equal to the clock period of the main clock signal; the clock period of the control clock signal is N times of the clock period of the master clock signal, and N is an integer greater than or equal to 2; the control clock signal is generated from the master clock signal;
for each alternative offset time, performing offset configuration on the phase of the control clock signal by using the alternative offset time, thereby delaying the control clock signal, performing data sampling based on the control clock signal after offset configuration, and determining the alternative offset time as a candidate offset time if the data is correctly sampled;
And under the condition that a plurality of candidate offset times exist, determining the optimal offset time from all the candidate offset times according to the ratio of the clock frequency of the master clock signal to the clock frequency of the control clock signal, and performing offset configuration on the control clock signal by utilizing the optimal offset time.
2. The method of claim 1, the control clock signal having a clock frequency equal to an update frequency of a data signal to be sampled.
3. The method of claim 1, the step of determining a plurality of alternative offset times comprising:
and determining N+1 alternative offset times according to the ratio N of the clock period of the control clock signal to the clock period of the main clock signal, wherein the first alternative offset time is 0.
4. A method according to claim 3, said step of determining the best offset time from all candidate offset times based on the ratio of the clock frequency of the master clock signal to the clock frequency of the control clock signal comprising:
rounding up or rounding down for one half of the ratio of the clock frequency of the master clock signal to the clock frequency of the control clock signal to obtain an integer m;
Judging whether a subtraction result of a ratio Tmax and the integer m is larger than 0 under the condition that the minimum candidate offset time in all candidate offset times is equal to 0, wherein the ratio Tmax is the ratio of the maximum candidate offset time to the clock period of the master clock signal; if yes, determining the optimal offset time according to the subtraction result; if not, determining the optimal offset time to be 0;
judging whether the ratio Tmin of the minimum candidate offset time to the clock period of the master clock signal is larger than the integer m or not under the condition that the maximum candidate offset time in all candidate offset times is equal to the clock period of the control clock signal; if yes, determining the clock period of the control clock signal as the optimal offset time; if not, determining the optimal offset time according to the addition result of the ratio Tmin and the integer m.
5. A method of sampling firmware data, the method comprising:
for each of a plurality of alternative offset times, performing offset configuration on the phase of a control clock signal of a sampling controller by using the alternative offset time, thereby delaying the control clock signal, performing target data sampling based on the control clock signal after offset configuration, and determining the alternative offset time as a candidate offset time if the target data is correctly sampled; wherein the difference between two adjacent alternative offset times is equal to the clock period of a master clock signal, the control clock signal being generated from the master clock signal;
In the case that a plurality of candidate offset times exist, determining the optimal offset time from all the candidate offset times according to the ratio of the clock frequency of the master clock signal to the clock frequency of the control clock signal;
and performing offset configuration on the control clock signal by utilizing the optimal offset time, and sampling firmware data based on the control clock signal after offset configuration.
6. The method of claim 5, wherein the clock frequency of the control clock signal is equal to the update frequency of the firmware data signal.
7. The method of claim 5, the plurality of alternative offset times being an arithmetic series, a difference between adjacent two alternative offset times being equal to a clock period of the master clock signal; the clock period of the control clock signal is N times the clock period of the master clock signal, N being an integer greater than or equal to 2.
8. The method of claim 7, the method further comprising:
and determining the plurality of alternative offset times according to the ratio of the clock period of the control clock signal to the clock period of the master clock signal, wherein the first alternative offset time is equal to 0, and the last alternative offset time is equal to the clock period of the control clock signal.
9. The method of claim 8, the step of determining the optimal offset time from all candidate offset times based on a ratio of a clock frequency of a master clock signal to a clock frequency of the control clock signal comprising:
rounding up or rounding down for one half of the ratio of the clock frequency of the master clock signal to the clock frequency of the control clock signal to obtain an integer m;
judging whether a subtraction result of a ratio Tmax and the integer m is larger than 0 under the condition that the minimum candidate offset time in all candidate offset times is equal to 0, wherein the ratio Tmax is the ratio of the maximum candidate offset time to the clock period of the master clock signal; if yes, determining the optimal offset time according to the subtraction result; if not, determining the optimal offset time to be 0;
judging whether the ratio Tmin of the minimum candidate offset time to the clock period of the master clock signal is larger than the integer m or not under the condition that the maximum candidate offset time in all candidate offset times is equal to the clock period of the control clock signal; if yes, determining the clock period of the control clock signal as the optimal offset time; if not, determining the optimal offset time according to the addition result of the ratio Tmin and the integer m.
10. The method of claim 5, prior to offset configuring the control clock signal with the alternative offset time, the method further comprising:
after the chip is electrified, sampling target data based on a control clock signal with a preset clock frequency, and storing the target data;
the step of performing offset configuration on the control clock signal of the sampling controller by using the alternative offset time for each of the plurality of alternative offset times, and performing target data sampling based on the control clock signal after offset configuration, and if the target data is correctly sampled, determining the alternative offset time as the candidate offset time includes:
switching the clock frequency of the control clock signal from the preset clock frequency to a target clock frequency, wherein the target clock frequency is higher than the preset clock frequency;
for each of a plurality of alternative offset times, performing offset configuration on a control clock signal of a target clock frequency by using the alternative offset time, sampling target data based on the control clock signal after offset configuration, comparing the sampled target data with stored target data, if the sampled target data and the stored target data are equal, determining that the target data are correctly sampled, and determining the alternative offset time as a candidate offset time;
The step of performing offset configuration on the control clock signal by using the optimal offset time and sampling firmware data based on the control clock signal after offset configuration includes:
and performing offset configuration on the control clock signal under the target frequency by utilizing the optimal offset time, and sampling the firmware data based on the control clock signal after offset configuration.
11. The method of claim 10, the target data being ID data of a firmware data storage device.
12. The method of claim 5, wherein the target data is updated based on the original control clock signal when the target data is sampled based on the offset configured control clock signal; when firmware data is sampled based on the control clock signal after offset configuration, the firmware data is updated based on the original control clock signal.
13. An apparatus for controlling a control clock signal, the apparatus comprising:
an alternative offset time determining module for determining a plurality of alternative offset times; the plurality of alternative offset times are in an arithmetic sequence, and the difference value of two adjacent alternative offset times is equal to the clock period of the main clock signal; the clock period of the control clock signal is N times of the clock period of the master clock signal, and N is an integer greater than or equal to 2; the control clock signal is generated from the master clock signal;
The candidate offset time determining module is used for performing offset configuration on the phase of the control clock signal by utilizing each alternative offset time so as to delay the control clock signal, performing data sampling on the basis of the control clock signal after offset configuration, and determining the alternative offset time as a candidate offset time if the data is correctly sampled;
and the optimal offset time determining module is used for determining the optimal offset time from all the candidate offset times according to the ratio of the clock frequency of the master clock signal to the clock frequency of the control clock signal under the condition that a plurality of candidate offset times exist, and performing offset configuration on the control clock signal by utilizing the optimal offset time.
14. An apparatus for sampling firmware data, the apparatus comprising:
a candidate offset time determining module, configured to, for each of a plurality of candidate offset times, perform offset configuration on a phase of a control clock signal of a sampling controller by using the candidate offset time, thereby delaying the control clock signal, and perform target data sampling based on the control clock signal after offset configuration, and if the target data is correctly sampled, determine the candidate offset time as a candidate offset time; wherein the difference between two adjacent alternative offset times is equal to the clock period of a master clock signal, the control clock signal being generated from the master clock signal;
The optimal offset time determining module is used for determining the optimal offset time from all the candidate offset times according to the ratio of the clock frequency of the master clock signal to the clock frequency of the control clock signal when a plurality of candidate offset times exist;
and the firmware data adopting module is used for carrying out offset configuration on the control clock signal by utilizing the optimal offset time and sampling the firmware data based on the control clock signal after the offset configuration.
15. A graphics processing system comprising the apparatus for controlling a control clock signal of claim 13 or the apparatus for sampling firmware data of claim 14.
16. An electronic device comprising the graphics processing system of claim 15.
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