CN114489742B

CN114489742B - Upgrading method and system for improving FPGA online upgrading efficiency in ATE equipment

Info

Publication number: CN114489742B
Application number: CN202111677571.5A
Authority: CN
Inventors: 凌云; 邬刚
Original assignee: Hangzhou Acceleration Technology Co ltd
Current assignee: Hangzhou Acceleration Technology Co ltd
Priority date: 2021-12-31
Filing date: 2021-12-31
Publication date: 2023-09-05
Anticipated expiration: 2041-12-31
Also published as: CN114489742A

Abstract

The invention provides an upgrading method and a system for improving the online upgrading efficiency of an FPGA in ATE equipment, wherein the method comprises the following steps: acquiring an FPGA address to be upgraded and version data; analyzing all Flash addresses and version data to be written; addressing all Flash corresponding to the Flash address, and writing version data into each Flash respectively; the written data in each Flash is read and compared with the version data to judge whether each Flash passes the data verification; if a certain Flash passes the data verification, the corresponding FPGA loads data from the Flash to finish online upgrading. According to the invention, the version data of the FPGA is written into the Flash in a parallel mode, so that a plurality of Flash can be written simultaneously, the time for downloading the version data into the Flash is greatly shortened, and the efficiency of ATE equipment on online upgrading of the FPGA is greatly improved. Meanwhile, the data verification method is optimized, data of data reading and data comparison are greatly reduced, and data verification efficiency is improved while data transmission quantity is reduced.

Description

Upgrading method and system for improving FPGA online upgrading efficiency in ATE equipment

Technical Field

The invention relates to the field of semiconductor chip testing, in particular to an upgrading method and system for improving the online upgrading efficiency of an FPGA in ATE equipment.

Background

ATE (Automatic Test Equipment) is an automatic test equipment, which is an aggregate of test instruments controlled by a high-performance computer, which is a test system composed of a tester and a computer, which controls test hardware by running instructions of a tester program. Semiconductor chip ATE is used for detecting the integrity of functions and performances of integrated circuits, and is an important device for ensuring the quality of integrated circuits in the integrated circuit production and manufacturing process, and four processes of tester programming, program compiling, vector loading and test are usually required to be performed on the integrated circuits.

In ATE equipment, each service board is configured with two FPGAs, so that different functions are realized respectively. In practical application, the debugging of the FPGA during production is generally carried out by burning and debugging through a JATG interface. When the FPGA is actually applied to a product, the JATG interface is too complicated to operate, and once the FPGA program needs to be updated, the online updating is needed, a new FPGA program is downloaded into the Flash, and under certain conditions, the FPGA loads the new FPGA program from the Flash to complete the online updating.

Because domestic ATE equipment develops rapidly, the version iteration speed of the FPGA is extremely high, a large amount of time is required for each version upgrading, and the upgrading efficiency is extremely low. In the prior art, when the FPGA is updated online, the downloading of the FPGA program to Flash is the most time-consuming step. Assuming that 30 seconds are required for writing an FPGA device into Flash, 2 FPGA devices are provided for one service board, and 20 service boards are provided for one ATE device, 2×20×30 seconds are required for upgrading the service boards for one ATE device. In addition, because the written data volume is large, the writing is easy to make mistakes, and the data needs to be read out for data comparison after being written into Flash, so that whether the data is correctly written is judged. The data volume of reading and writing is big, and the reading time is long, greatly influences the efficiency of online upgrading.

In summary, in the prior art, online upgrading of the FPGA generally has the disadvantages of low upgrading efficiency and long verification time.

Therefore, a related scheme related to the FPGA upgrade of a service board in an ATE device is urgently needed to solve the problem of low on-line FPGA upgrade efficiency.

Disclosure of Invention

In view of this, the invention provides an upgrading method and system for improving the online upgrading efficiency of an FPGA in ATE equipment, and the specific scheme is as follows:

the upgrading method for improving the online upgrading efficiency of the FPGA in the ATE equipment is suitable for the ATE equipment comprising a main control board, a back board and service boards, wherein each service board comprises a first FPGA provided with Flash0 and a second FPGA provided with Flash 1;

the upgrading method comprises the following steps:

acquiring an FPGA address to be upgraded and version data related to FPGA upgrading;

resolving first addresses corresponding to all Flash0 and second addresses corresponding to all Flash1 from the FPGA addresses to be upgraded, and resolving first version data to be written into Flash0 and second version data to be written into Flash1 from the version data;

addressing all Flash0 corresponding to the first address, and respectively writing the first version data into each Flash0 to obtain first writing data; addressing all Flash1 corresponding to the second address, and respectively writing the second version data into each Flash1 to obtain second writing data;

reading first write-in data in each Flash0, and comparing the first write-in data with the first version data to judge whether each Flash0 passes the data verification; reading second writing data in each Flash1, and comparing the second writing data with the second version data to judge whether each Flash1 passes the data verification;

if a certain Flash0 passes the data verification, loading first writing data from the Flash0 by a corresponding first FPGA to finish online upgrading; if a certain Flash1 passes the data verification, the corresponding second FPGA loads second writing data from the Flash1 to finish online upgrading.

In a specific embodiment, the "resolving the first addresses corresponding to all Flash0 and the second addresses corresponding to all Flash1 from the FPGA address to be upgraded" specifically includes:

resolving a service board address and a main board address corresponding to each FPGA to be upgraded from the FPGA addresses to be upgraded; the FPGA to be upgraded comprises the first FPGA and the second FPGA;

a virtual service board address is summarized according to the service board address, the virtual service board address can cover all service board addresses of the FPGA to be upgraded, and a virtual main board address is summarized according to the main board address, and the virtual main board address can cover all main board addresses of the FPGA to be upgraded;

on the basis of the virtual service board address and the virtual main board address, a first address is built by combining the Flash0 addresses, the first address can cover all Flash0 addresses of the first FPGA, a second address is built by combining the Flash1 addresses, and the second address can cover all Flash1 addresses of the second FPGA.

In a specific embodiment, the first address and the second address are each 4 bytes in size;

the size of the Flash0 address is 1Byte, the size of the Flash1 address is 1Byte, the size of the virtual service board address is 2Byte, and the size of the virtual main board address is 1Byte.

In a specific embodiment, the data verification specifically includes:

reading the data of each first writing data at a first preset position, comparing the data with the data of the first version data at the first preset position, and if the data of the first version data and a certain first writing data at the first preset position are the same, correctly writing the first version data into the Flash0, wherein the Flash0 passes the data verification;

and reading the data of each second writing data at a second preset position, comparing the data with the data of the second version data at the second preset position, and if the data of the second version data and a certain second writing data at the second preset position are the same, correctly writing the second version data into the Flash1, wherein the Flash1 passes the data verification.

In a specific embodiment, the first preset position and the second preset position are both randomly set;

the total amount of data of each first writing data at the first preset position is 16Byte;

the total amount of data of each second write data at the second preset position is 16Byte.

In a specific embodiment, the first FPGA and the second FPGA differ in functional mode, and the first version data and the second version data differ;

and according to the functional mode of the second FPGA, analyzing second version data which needs to be written into Flash1 from the second version data.

The upgrading system is suitable for the ATE equipment comprising a main control board, a back board and service boards, wherein each service board comprises a first FPGA provided with Flash0 and a second FPGA provided with Flash 1;

the upgrade system includes a system that,

a data acquisition unit: the method comprises the steps of acquiring an address of an FPGA to be upgraded and version data related to the upgrading of the FPGA;

a data analysis unit: the method comprises the steps of analyzing first addresses corresponding to all Flash0 and second addresses corresponding to all Flash1 from the FPGA address to be upgraded, and analyzing first version data to be written into Flash0 and second version data to be written into Flash1 from the version data;

a data writing unit: the Flash memory is used for addressing all Flash0 corresponding to the first address, and writing the first version data into each Flash0 respectively to obtain first writing data; addressing all Flash1 corresponding to the second address, and respectively writing the second version data into each Flash1 to obtain second writing data;

and a data verification unit: the method comprises the steps that first write-in data in each Flash0 are read, and data comparison is carried out between the first write-in data and the first version data, so that whether each Flash0 passes data verification or not is judged; reading second writing data in each Flash1, and comparing the second writing data with the second version data to judge whether each Flash1 passes the data verification;

a data loading unit: if a certain Flash0 passes the data verification, loading first writing data from the Flash0 by a corresponding first FPGA to finish online upgrading; if a certain Flash1 passes the data verification, the corresponding second FPGA loads second writing data from the Flash1 to finish online upgrading.

In a specific embodiment, the data parsing unit specifically includes:

In a specific embodiment, the data verification unit specifically includes:

The beneficial effects are that: the invention provides an upgrading method and system for improving the online upgrading efficiency of an FPGA in ATE equipment, which writes version data of the FPGA into Flash in a parallel mode, and compared with the traditional writing of Flash one by one, the method and system can realize the simultaneous writing of a plurality of Flash, greatly shorten the time for downloading the version data to the Flash and greatly improve the online upgrading efficiency of the ATE equipment on the FPGA. Meanwhile, the data verification method is optimized, the traditional verification of all data is changed into random verification of partial data, the data of data reading and data comparison are greatly reduced, the data transmission quantity is reduced, and meanwhile, the data verification efficiency is improved.

Drawings

FIG. 1 is a schematic flow chart of an upgrade method according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of the various stages of an ATE apparatus according to the present invention;

FIG. 3 is a schematic diagram of a communication protocol module according to an embodiment of the present invention;

fig. 4 is a schematic diagram of an upgrade system module according to an embodiment of the present invention.

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Reference numerals: 1-a data acquisition unit; 2-a data analysis unit; a 3-data writing unit; 4-a data verification unit; 5-data loading unit.

Detailed Description

Hereinafter, various embodiments of the present disclosure will be more fully described. The present disclosure is capable of various embodiments and its modifications and variations are possible in light of the above teachings. However, it should be understood that: there is no intention to limit the various embodiments of the present disclosure to the specific embodiments disclosed herein, but rather the present disclosure is to be understood to cover all modifications, equivalents, and/or alternatives falling within the spirit and scope of the various embodiments of the present disclosure.

The terminology used in the various embodiments of the disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the various embodiments of the disclosure. As used herein, the singular is intended to include the plural as well, unless the context clearly indicates otherwise. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present disclosure belong. The terms (such as those defined in commonly used dictionaries) will be interpreted as having a meaning that is identical to the meaning of the context in the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in the various embodiments of the disclosure.

Example 1

The embodiment 1 of the invention discloses an upgrading method for improving the online upgrading efficiency of an FPGA in ATE equipment, and realizes online upgrading of all FPGAs in a parallel writing mode. The upgrading method is shown in a flow chart and a block diagram in the specification of figure 1, and the specific scheme is as follows:

the upgrading method for improving the online upgrading efficiency of the FPGA in the ATE equipment is suitable for the ATE equipment comprising a main control board, a back board and service boards, wherein each service board comprises a first FPGA configured with Flash0 and a second FPGA configured with Flash1. In this embodiment, flash0 and Flash1 are both located in the storage location of the service board FPGA. The FPGA realizes the online upgrading of the FPGA by loading a new FPGA program from Flash.

The flow chart of the upgrading method of the embodiment is shown in fig. 1 of the specification, and the specific method flow comprises the following steps:

101. acquiring an FPGA address to be upgraded and version data related to FPGA upgrading;

102. resolving first addresses corresponding to all Flash0 and second addresses corresponding to all Flash1 from the FPGA addresses to be upgraded, and resolving first version data to be written into Flash0 and second version data to be written into Flash1 from the version data;

103. addressing all Flash0 corresponding to the first address, and respectively writing the first version data into each Flash0 to obtain first writing data; addressing all Flash1 corresponding to the second address, and respectively writing the second version data into each Flash1 to obtain second writing data;

104. reading the first writing data in each Flash0, and comparing the first writing data with the first version data to judge whether each Flash0 passes the data verification; reading the second writing data in each Flash1, and comparing the second writing data with the second version data to judge whether each Flash1 passes the data verification;

105. if a certain Flash0 passes the data verification, loading first writing data from the Flash0 by a corresponding first FPGA to finish online upgrading; if a certain Flash1 passes the data verification, the corresponding second FPGA loads second writing data from the Flash1 to finish online upgrading.

In the embodiment, the version data of the FPGA are written into the Flash in a parallel mode, so that compared with the traditional Flash-by-Flash addressing writing, the method realizes simultaneous writing of a plurality of Flash, greatly shortens the time for downloading the version data into the Flash, and greatly improves the efficiency of ATE equipment on online upgrading of the FPGA. Meanwhile, when the data is written into the Flash, the data error is a whole packet error, namely all the data written into the Flash are in error. According to the characteristics, the data verification method is optimized, the traditional verification of all data is changed into the random verification of part data, the data quantity of data reading and data comparison is greatly reduced, the data transmission quantity is reduced, and meanwhile, the data verification efficiency is improved.

It should be noted that the upgrade method provided in this embodiment is applicable to ATE equipment including two FPGAs in one service board. In practical application, a plurality of service boards are configured on each main board, two FPGAs are configured on each service board, and Flash is configured on each FPGA. And sending version data related to FPGA updating through a host, and writing the corresponding version data into Flash of each FPGA to be upgraded by combining the address of the FPGA to be upgraded. The structure of Flash in the ATE device is shown in fig. 2 of the specification, flash in the first FPGA of each service board is named as Flash0, and Flash in the second FPGA of each service board is named as Flash1. The data is the same in all Flash0 and the data is the same in all Flash1. However, since the functions of the first FPGA and the second FPGA are different, the version information to be written is also different, so that the data of Flash0 and Flash1 are not identical.

101. And acquiring the address of the FPGA to be upgraded and version data related to the upgrading of the FPGA. The FPGA address to be upgraded is the service board where the FPGA to be upgraded is located and the main board where the service board is located. The version data of the FPGA comprises a first version data and a second version data.

102. And resolving the first addresses corresponding to all the Flash0 and the second addresses corresponding to all the Flash1 from the FPGA addresses to be upgraded, and resolving the first version data to be written into the Flash0 and the second version data to be written into the Flash1 from the version data.

Step 102 mainly parses the data in step 101, and specifically includes:

10201. and resolving the service board address and the main board address corresponding to each FPGA to be upgraded from the FPGA addresses to be upgraded. The FPGA to be upgraded comprises a first FPGA and a second FPGA. According to the first FPGA, the first version data which needs to be written into Flash0 is analyzed from the version data, and according to the second FPGA, the second version data which needs to be written into Flash1 is analyzed from the second version data.

10202. And according to the service board address, a virtual service board address which can cover the service board addresses of all the FPGAs to be upgraded is summarized, and according to the main board address, a virtual main board address which can cover the main board addresses of all the FPGAs to be upgraded is summarized.

10203. On the basis of the virtual service board address and the virtual main board address, a first address which can cover all Flash0 addresses of the first FPGA is built by combining the Flash0 address, and a second address which can cover all Flash1 addresses of the second FPGA is built by combining the Flash1 address.

Assuming that there are four motherboards, the addresses of the motherboards are 0x1, 0x2, 0x4, and 0x8, respectively, the four addresses of the motherboards can be summarized by 0xF, and 0xF is the virtual motherboard address. Assuming that 5 service boards are configured on each main board, and the service board addresses are respectively 0x1, 0x2, 0x4, 0x8 and 0x10, the 5 service board addresses can be summarized by 0x1F, and 0x1F is the virtual service board address.

The first address comprises a Flash0 address, a virtual service board address and a virtual main board address, and the first address comprises a Flash1 address, a virtual service board address and a virtual main board address. After the virtual service board address and the virtual main board address are obtained, the first address and the second address can be obtained only by adding the Flash0 address and the Flash1 address. In practice, the present embodiment replaces the FPGA address with Flash0 address and Flash1 address. The first address comprises all first FPGA addresses to be upgraded, and the second address comprises all second FPGA addresses to be upgraded.

In this embodiment. The first address and the second address are both 4Byte in size; the Flash0 address is 1Byte, the Flash1 address is 1Byte, the virtual service board address is 2Byte, and the virtual main board address is 1Byte. The communication protocol corresponding to the first address and the second address is shown in figure 3 of the specification.

103. Addressing all Flash0 corresponding to the first address, and respectively writing the first version data into each Flash0 to obtain first writing data; addressing all Flash1 corresponding to the second address, and writing the second version data into each Flash1 to obtain second writing data. The embodiment mainly adjusts the addressing mode, and addressing actually refers to searching the bit state of the service board, and the bit state is known when software is started, so that Flash can be controlled to be written simultaneously.

For example, assume that there are 4 motherboards, motherboard 0, motherboard 1, motherboard 2, motherboard 3, motherboard addresses 0x1, 0x2, 0x4, 0x8, respectively. Each motherboard is provided with 5 service boards, namely a service board 0, a service board 1, a service board 2, a service board 3 and a service board 4, and addresses of the service boards are respectively 0x1, 0x2, 0x4, 0x8 and 0x10. And each service board is respectively provided with a first FPGA and a second FPGA. A total of 40 FPGAs need to be upgraded.

In the prior art, addressing and writing are needed for forty times only through addressing one by one FPGA, so that online upgrading of all FPGAs can be realized, and the specific scheme is as follows:

step1, address motherboard 0, service board 0, flash0, address 0x1000101, write the first version data into Flash0.

Step2, address motherboard 0, service board 0, flash1, address 0x1000102, write the second version of data to Flash1.

Step3, address motherboard 0, service board 1, flash0, address 0x1000201, write the first version of data to Flash0.

Step......

Step40, address motherboard 3, service board 4, flash1, address 0x8001001, write the second version of data to Flash1.

By adopting the upgrading method of the embodiment, the online upgrading of all FPGAs can be realized only by addressing and writing twice, the data writing times are 1/20 of the original times, and the efficiency is greatly improved. The specific scheme is as follows:

step1, addressing all first FPGAs with Flash0 addresses of 0xF001F01, and writing the first version data into all Flash 0;

step2, addressing all second FPGAs with Flash1 addresses of 0xF001F02, and writing the second version data into all Flash1.

the data verification is a judging method for whether the data is correctly written or not, and because the FPGA has high data requirement during upgrading, special steps are required to be set for data verification. In practical tests, the data writing errors are all whole-packet errors, namely, the data of the whole Flash are all errors, and the situation that individual position errors exist is avoided. The existing data verification method is to read all the written data, and the data volume is usually up to several KB.

Based on this, the present embodiment optimizes the data verification, verifying only part of the write data. Compared with the prior art, the data size is reduced to a few bits by a plurality of KB to carry out data, so that the data transmission is greatly reduced, and the data verification efficiency is improved. The data verification specifically comprises the following steps:

reading the data of each first writing data at a first preset position, comparing the data with the data of the first version data at the first preset position, and if the data of the first version data is the same as the data of a certain first writing data at the first preset position, correctly writing the first version data into the Flash0, wherein the Flash0 passes the data verification;

and reading the data of each second writing data at a second preset position, comparing the data with the data of the second version data at the second preset position, and if the data of the second version data is the same as the data of a certain second writing data at the second preset position, correctly writing the second version data into the Flash1, wherein the Flash1 passes the data verification.

It should be noted that, in some cases, a conventional data verification method may be adopted, that is, all the first writing data are read out, and data comparison is performed with the first version data, and all the second writing data are read out, and data comparison is performed with the second version data.

Preferably, the first preset position and the second preset position are both randomly set. In some cases, the first preset position and the second preset position may also be fixedly set. For example, data at individual locations is important, and only that portion of data may be extracted for data verification.

Further preferably, each Flash only checks 16Byte of data at the time of data check. That is, the total amount of data of each first writing data at the first preset position is 16 bytes; the total amount of data of each second write data at the second preset position is 16Byte.16Byte can meet the vast majority of version data accuracy guarantees.

105. If a certain Flash0 passes the data verification, loading first writing data from the Flash0 by a corresponding first FPGA to finish online upgrading; if a certain Flash1 passes the data verification, the corresponding second FPGA loads second writing data from the Flash1 to finish online upgrading. And after loading corresponding data, the power-down restarting can be realized, and a new FPGA program is used to finish the online upgrading of the FPGA.

Assuming that 30 seconds are required for writing an FPGA device into Flash, 2 FPGA devices are provided for one service board, and 20 service boards are provided for one ATE device, 2×20×30 seconds are required for upgrading the service boards. The service board is upgraded by adopting the upgrading method of the embodiment only by 2 x 30 seconds, and the efficiency is improved by 20 times.

The embodiment provides an upgrading method for improving the online upgrading efficiency of an FPGA in ATE equipment, version data of the FPGA are written into Flash in a parallel mode, and compared with the traditional writing of Flash one by one, the method can achieve simultaneous writing of a plurality of Flash, greatly shortens the time for downloading the version data to the Flash, and greatly improves the online upgrading efficiency of the ATE equipment on the FPGA. Meanwhile, the data verification method is optimized, the traditional verification of all data is changed into random verification of partial data, the data of data reading and data comparison are greatly reduced, the data transmission quantity is reduced, and meanwhile, the data verification efficiency is improved.

Example 2

The embodiment 2 of the invention discloses an upgrading system for improving the online upgrading efficiency of an FPGA in ATE equipment, and the upgrading method of the embodiment 1 is systematic, the specific structure of the system is shown in a figure 4 of the specification, and the specific scheme is as follows:

the upgrading system for improving the online upgrading efficiency of the FPGA in the ATE equipment is characterized by being suitable for the ATE equipment comprising a main control board, a back board and service boards, wherein each service board comprises a first FPGA provided with Flash0 and a second FPGA provided with Flash 1;

the upgrade system includes a system that includes a plurality of components,

data acquisition unit 1: the method comprises the steps of acquiring an address of an FPGA to be upgraded and version data related to the upgrading of the FPGA;

data analysis unit 2: the method comprises the steps of analyzing first addresses corresponding to all Flash0 and second addresses corresponding to all Flash1 from an FPGA address to be upgraded, and analyzing first version data to be written into Flash0 and second version data to be written into Flash1 from version data;

a data writing unit 3: the method comprises the steps of addressing all Flash0 corresponding to a first address, and respectively writing first version data into each Flash0 to obtain first writing data; addressing all Flash1 corresponding to the second address, and respectively writing the second version data into each Flash1 to obtain second writing data;

data verification unit 4: the method comprises the steps that first writing data in each Flash0 are read, and data comparison is carried out between the first writing data and first version data, so that whether each Flash0 passes data verification is judged; reading the second writing data in each Flash1, and comparing the second writing data with the second version data to judge whether each Flash1 passes the data verification;

data loading unit 5: if a certain Flash0 passes the data verification, loading first writing data from the Flash0 by a corresponding first FPGA to finish online upgrading; if a certain Flash1 passes the data verification, the corresponding second FPGA loads second writing data from the Flash1 to finish online upgrading.

The data parsing unit 2 specifically includes:

analyzing a service board address and a main board address corresponding to each FPGA to be upgraded from the FPGA addresses to be upgraded;

according to the service board address, a virtual service board address which can cover the service board addresses of all FPGAs to be upgraded is summarized, and according to the main board address, a virtual main board address which can cover the main board addresses of all FPGAs to be upgraded is summarized;

on the basis of the virtual service board address and the virtual main board address, a first address which can cover all Flash0 addresses of the first FPGA is built by combining the Flash0 address, and a second address which can cover all Flash1 addresses of the second FPGA is built by combining the Flash1 address.

In this embodiment, the first address and the second address are each 4Byte in size. The Flash0 address is 1Byte, the Flash1 address is 1Byte, the virtual service board address is 2Byte, and the virtual main board address is 1Byte.

The data verification unit 4 specifically includes:

The embodiment discloses an upgrade system for improving the online upgrade efficiency of an FPGA in ATE equipment, and the acceleration method of the embodiment 1 is systemized, so that the upgrade system has higher practicability.

The invention provides an upgrading method and system for improving the online upgrading efficiency of an FPGA in ATE equipment, which writes version data of the FPGA into Flash in a parallel mode, and compared with the traditional writing of Flash one by one, the method and system can realize the simultaneous writing of a plurality of Flash, greatly shorten the time for downloading the version data to the Flash and greatly improve the online upgrading efficiency of the ATE equipment on the FPGA. Meanwhile, the data verification method is optimized, the traditional verification of all data is changed into random verification of partial data, the data of data reading and data comparison are greatly reduced, the data transmission quantity is reduced, and meanwhile, the data verification efficiency is improved.

Those skilled in the art will appreciate that the drawing is merely a schematic illustration of a preferred implementation scenario and that the modules or flows in the drawing are not necessarily required to practice the invention. Those skilled in the art will appreciate that modules in an apparatus in an implementation scenario may be distributed in an apparatus in an implementation scenario according to an implementation scenario description, or that corresponding changes may be located in one or more apparatuses different from the implementation scenario. The modules of the implementation scenario may be combined into one module, or may be further split into a plurality of sub-modules. The above-mentioned inventive sequence numbers are merely for description and do not represent advantages or disadvantages of the implementation scenario. The foregoing disclosure is merely illustrative of some embodiments of the invention, and the invention is not limited thereto, as modifications may be made by those skilled in the art without departing from the scope of the invention.

Claims

1. The upgrading method for improving the online upgrading efficiency of the FPGA in the ATE equipment is characterized by being suitable for the ATE equipment comprising a main control board, a back board and service boards, wherein each service board comprises a first FPGA provided with Flash0 and a second FPGA provided with Flash 1;

the upgrading method comprises the following steps:

if a certain Flash0 passes the data verification, loading first writing data from the Flash0 by a corresponding first FPGA to finish online upgrading; if a certain Flash1 passes the data verification, loading second writing data from the Flash 1by a corresponding second FPGA to finish online upgrading;

the "resolving the first addresses corresponding to all Flash0 and the second addresses corresponding to all Flash1 from the FPGA address to be upgraded" specifically includes:

2. The upgrade method of claim 1, wherein the first address and the second address are each 4 bytes in size;

3. The upgrade method according to claim 1, wherein the data verification specifically comprises:

4. The upgrade method according to claim 3, wherein the first preset position and the second preset position are both randomly set;

5. The upgrade method according to claim 1, wherein the first FPGA and the second FPGA are different in functional mode, and the first version data and the second version data are different;

6. The upgrading system for improving the online upgrading efficiency of the FPGA in the ATE equipment is characterized by being suitable for the ATE equipment comprising a main control board, a back board and service boards, wherein each service board comprises a first FPGA provided with Flash0 and a second FPGA provided with Flash 1;

the upgrade system includes a system that,

a data loading unit: if a certain Flash0 passes the data verification, loading first writing data from the Flash0 by a corresponding first FPGA to finish online upgrading; if a certain Flash1 passes the data verification, loading second writing data from the Flash 1by a corresponding second FPGA to finish online upgrading;

the data analysis unit specifically comprises:

7. The upgrade system of claim 6, wherein the first address and the second address are each 4 bytes in size;

8. The upgrade system of claim 6, wherein the data verification unit specifically comprises: