CN116148654A - Device for detecting relay for chip test board card - Google Patents

Abstract

The present disclosure discloses an apparatus for detecting a relay for a chip test board, comprising: the testing machine is used for outputting an excitation control signal; the relay is used for controlling a chip test channel on the tester to switch and test a chip pin to be tested on the chip based on the excitation control signal; the detection unit is used for reading the excitation control signal and the response signal output by the relay when the control chip test channel switches and tests the chip pins to be tested on the chip, and detecting the relay by comparing the excitation control signal with the response signal.

Description

Device for detecting relay for chip test board card

Technical Field

The disclosure belongs to the technical field of semiconductor testing, and in particular relates to a device for detecting a relay for a chip test board.

Background

With the rapid development of the chip design and manufacturing industry, the manufacturing scale of semiconductors is larger and larger, the number of chip pins is obviously increased on some types of chips, and the use cost of a tester platform is often increased along with the increase of the number of resources of a tester test channel. Especially, in the face of increasing chip pin number, resources required by chip testing need to be evaluated before testing, and a tester meeting the chip testing requirements needs to be selected.

Currently, under some special products and test requirements, taking 3380D platform as an example, there are 256 IO channels of the tester. For example, if the chips packaged by QFN56, QFN64 and the like, or even more pins packaged chips are tested, if the channels of the tester are connected with the pins of the chips in a one-to-one correspondence manner, the maximum number of chips which can be tested by one tester at the same time is limited by the number of channels of the tester. For example, 3380D is generally only capable of simultaneously testing 4 chips for QFN64 packaged chips. In addition, in a general test scheme, most IO pins only perform OPEN/SHORT (OS) tests, and most IO pins are not used except for the OS tests, so that resources of IO channels of a tester are idle. At present, in order to fully utilize IO tester resources and realize the increase of the parallel test quantity, the controller and the relay can be used for realizing the switching of tester channels between two chip PINs, as shown in fig. 1, the controller is used for controlling the relay, under the condition of using G6KU-2Y, the tester channels ATE CH1 and ATE CH2 (the tester channel type comprises IO, DPS, PMU) can be controlled simultaneously, the tester channels ATE CH1 can be switched between the chip PINs IC PIN1 and IC PIN2, and the tester channels ATE CH2 can be switched between the chip PINs IC PIN3 and IC PIN4, so that one test channel of the tester can be used for measuring or supplying power to two chip PINs, the test efficiency can be improved, the tester with fewer resources can be used for satisfying the chip test with higher requirements, and the production cost is remarkably reduced.

In some chip tests, it is required to switch the chip pins to the peripheral circuit after an OPEN/SHORT (OS) test is performed on the chip pins. As shown in fig. 2, the relay is controlled by the controller, and under the condition of using G6KU-2Y, the chip PIN IC PIN1 and the IC PIN2 can be controlled simultaneously by the control signal RL0, so that the chip PIN IC PIN1 can be switched between the tester channel ATE CH1 and the peripheral circuit OUT PIN 1; the chip PIN IC PIN2 can be switched between the channel ATE CH2 of the tester and the peripheral circuit OUT PIN2, so that the chip PIN connection requirements of different test items of the chip are met.

When the relay is actually used for carrying out expansion switching on the IO channel, the relay is only controlled by the control signal RL0 of the testing machine, and the working state of the relay cannot be fed back to the testing machine, so that the testing machine cannot obtain the state information of the relay, namely, the testing machine does not know whether the relay is successfully switched, and therefore, when the relay fails, the testing channel of the testing machine cannot be switched, the testing channel is always connected with a certain pin, and the pin of the testing data is not corresponding to the pin to be tested controlled by the program.

For example, when the IO test channel is extended, as in fig. 1, the chip PINs IC PIN1 and IC PIN2 are measured by the tester channel ATE CH1, the OS tests the voltages on the chip PINs IC PIN1 and IC PIN 2. When the tester finishes testing the chip PIN IC PIN1 with the ATE CH1, if the relay cannot correctly connect the tester channel ATE CH1 to the chip PIN IC PIN2, the data measured by the tester will still be the data of the chip PIN IC PIN1, but the data will be saved as the data of the chip PIN IC PIN2 by the tester, resulting in data errors. If the chip PIN IC PIN1 measurement data meets the test requirement, namely the PASS, but the chip PIN IC PIN2 is actually FAIL, so when the relay FAILs or is in error in switching, the OS test cannot detect all PINs to be tested, so that part of the chip PINs (such as the IC PIN 1) are measured twice, part of the chip PINs (such as the IC PIN 2) are not detected, and the upper and lower limits set by different PINs PASS in the OS test are the same, the tester can judge that the OS tests of the chip PINs IC PIN1 and the IC PIN2 PASS, but the whole chip is a defective product, and the missing test condition cannot be detected through the data. In the production process, a large number of defective products are missed to be detected, and the circuits are required to be checked and retested is carried out on the whole batch of products, so that the test reliability and the production efficiency are reduced. Especially when facing to the chip which can not be retested, the chip which is tested once can not be retested, and can only be discarded in whole batch, so that economic loss is generated.

Disclosure of Invention

Aiming at the defects in the prior art, the object of the present disclosure is to provide a device for detecting a relay for a chip test board card, which can detect the working state of the relay itself when the relay switches and tests the chip pins to be tested, so as to avoid that the relay is damaged to cause the chip pins to be missed to be detected, thereby causing defective products to be undetected.

In order to achieve the above object, the present disclosure provides the following technical solutions:

an apparatus for testing a relay for a chip test board, comprising:

the testing machine is used for outputting an excitation control signal;

the relay is used for controlling a chip test channel on the tester to switch and test a chip pin to be tested on the chip based on the excitation control signal;

the detection unit is used for reading the excitation control signal and the response signal output by the relay when the control chip test channel switches and tests the chip pins to be tested on the chip, and detecting the relay by comparing the excitation control signal with the response signal.

Preferably, the relay includes a switching section and an output section, wherein,

the switching part is used for controlling a chip test channel on the tester to perform switching test on the chip pins to be tested based on the excitation control signal;

the output part is used for the switching part to output a response signal when the chip test channel is controlled to perform switching test on the chip pins to be tested based on the excitation control signal.

Preferably, the detection unit comprises a micro control unit MCU.

Preferably, the device further comprises a voltage stabilizing unit for performing voltage stabilizing control on the relay.

The present disclosure also provides a method of detecting a relay for a chip test board, comprising the steps of:

s100: outputting an excitation control signal by the testing machine;

s200: the relay controls a chip test channel on the tester to switch and test pins of a chip to be tested on the chip based on the excitation control signal;

s300: the detection unit reads the excitation control signal and the response signal output by the reading relay when the chip test channel is controlled to switch and test the chip pins to be tested on the chip based on the excitation control signal in real time, and detects the relay by comparing the excitation control signal and the response signal.

Preferably, in step S300, if the excitation control signal and the response signal are the same level signals, the relay is normal; if the excitation control signal and the response signal are different level signals, the relay is abnormal.

The present disclosure also provides an apparatus for detecting a plurality of relay arrays for a chip test board, comprising:

the testing machine is used for outputting an excitation control signal;

and the detection unit is used for reading a plurality of response signal sequences output by the relay arrays under the excitation of the excitation control signal, and detecting abnormal relays in the relay arrays by comparing the plurality of response signal sequences.

Preferably, the detection unit comprises a micro control unit MCU.

The present disclosure also provides a method of detecting a plurality of relay arrays for a chip test board, comprising the steps of:

s1000: outputting an excitation control signal by the testing machine;

s2000: the detection unit reads a plurality of response signal sequences output by the plurality of relay arrays under the excitation of the excitation control signal;

s3000: comparing the plurality of response signal sequences to detect an abnormal relay in the relay array.

Compared with the prior art, the beneficial effects that this disclosure brought are:

1. the relay is used for outputting the state of the relay, so that adverse effects on test data caused by the fact that an additional circuit and an original chip test circuit form a passage can be avoided;

2. the existing relay structure is improved, and the state of the relay can be detected while the switching test of the chip pins is realized;

3. the abnormal relay can be directly positioned, manual investigation is reduced, and the working efficiency is improved.

Drawings

FIG. 1 is a schematic diagram of a control of a tester channel switching between two chip pins using a relay;

FIG. 2 is a schematic diagram of switching between tester channels and peripheral circuits using relay control chip pins;

fig. 3 is a schematic diagram of an apparatus for testing a relay for a chip test board provided by the present disclosure.

Detailed Description

Specific embodiments of the present disclosure will be described in detail below with reference to fig. 1 to 3. While specific embodiments of the disclosure are shown in the drawings, it should be understood that the disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

It should be noted that certain terms are used throughout the description and claims to refer to particular components. Those of skill in the art will understand that a person may refer to the same component by different names. The specification and claims do not identify differences in terms of components, but rather differences in terms of the functionality of the components. As used throughout the specification and claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. The description hereinafter sets forth the preferred embodiments for carrying out the present disclosure, but is not intended to limit the scope of the disclosure in general, as the description proceeds. The scope of the present disclosure is defined by the appended claims.

For the purposes of promoting an understanding of the embodiments of the disclosure, reference will now be made to the embodiments illustrated in the drawings and specific examples, without the intention of being limiting the embodiments of the disclosure.

In one embodiment, the present disclosure provides an apparatus for inspecting a relay for a chip test board, comprising:

the testing machine is used for outputting an excitation control signal;

the relay is used for controlling a chip test channel on the tester to switch and test a chip pin to be tested on the chip based on the excitation control signal;

the detection unit is used for reading the excitation control signal and the response signal output by the relay when the control chip test channel switches and tests the chip pins to be tested on the chip, and detecting the relay by comparing the excitation control signal with the response signal.

In a specific embodiment, the relay comprises a switching part and an output part, wherein the switching part is used for controlling a chip tester channel on the tester to perform switching test on 2 chip pins to be tested in a single chip or two chips based on an excitation control signal output by a relay control channel on the tester; illustratively, as shown in fig. 3, the relay switching section includes pin1, pin2, pin3, pin4, and pin 8, and the output section includes pin 5 and pin 6. The PIN1 is connected to a zener diode (cathode connection PIN1 and anode connection PIN 8 of the zener diode, when RL0 is low level, a potential difference is formed between the PINs 1 and 8 of the relay, if no zener diode exists, the current between the PINs 1 and 8 of the relay may be excessively large, so that the relay is burnt out, so that the voltage of the relay is stabilized by using the zener diode to prevent the relay from being burnt out due to excessively large potential difference), the PIN2 is connected to the PIN IC PIN1 of the chip, the PIN3 is connected to the test channel ATE CH1 of the chip, the PIN4 is connected to the PIN IC PIN2 of the chip, and the PIN 8 is connected to a control channel of the relay on the tester to receive the excitation control signal RL0. Under the condition that the relay is in normal stateWhen the PIN 8 receives the excitation control signal RL0 output by the relay control channel on the tester to be at high level, no current is generated between the PIN1 and the PIN 8, the relay is disconnected and keeps the default state, the PIN2 is connected with the PIN3, the PIN 6 is connected with the PIN 7, namely the chip PIN IC PIN1 is communicated with the chip test channel ATE CH1, and at the moment, the PIN 5 is grounded and the response signal S output by the PIN 6 is output ₀ Is high. When the excitation control signal RL0 received by the PIN 8 is at a low level, a current is supplied between the PIN1 and the PIN 8, the relay is attracted, the PIN3 is connected with the PIN4, the PIN 5 is connected with the PIN 6, i.e. the chip PIN IC PIN2 is communicated with the chip test channel ATE CH1, and at the moment, the PIN 6 outputs a response signal S ₀ Is low. At the same time, the MCU as the detection unit reads the control signal RL0 and the response signal S in real time ₀ When the read excitation control signal RL0 is high, the response signal S is simultaneously ₀ Also at a high level, and while the read excitation control signal RL0 is at a low level, a response signal S ₀ And if the signal is at a low level, the chip test channel ATE CH1 is successfully switched between the chip PIN IC PIN1 and the chip PIN IC PIN2, and the relay can be judged to be in a normal state at the moment. When the relay is damaged or the circuit is broken, the relay cannot normally control the channel ATE CH1 of the chip tester to perform switching test on the chip PIN IC PIN1 and the chip PIN IC PIN2, namely, when the read excitation control signal RL0 is at a high level, the response signal S ₀ At a low level, and while the read excitation control signal RL0 is at a low level, a response signal S ₀ Is high.

It should be noted that, by detecting whether the response signal is consistent with the excitation control signal, whether the state of the relay is abnormal is merely determined based on the existing pin arrangement mode of fig. 3, if the pin 5 and the pin 7 in fig. 3 are exchanged, the input and the output of the normal relay are inconsistent, i.e. when the input and the output are detected to be different, the relay is normal; when the input and the output are detected to be the same, the relay is abnormal, and therefore, the specific judgment logic depends on the actual connection mode of the pins on the relay.

In addition, it should be noted that the reasons for the relay abnormality include many, such as the power supply abnormality of the relay pin1 (the effective path cannot be formed between the pin1 and the pin 8, resulting in the failure of the electromagnet), the aging and burning of the relay, etc., but the present disclosure is limited to the study of comparing the input and output signals to determine whether the relay is abnormal or not, and no deep investigation is made for the specific abnormality type.

The above embodiments describe the technical solutions of the present disclosure in detail. In the chip test, if the additional circuit and the original chip test circuit form a channel, various tiny signals can affect the data of the chip test, so that the additional circuit needs to be completely isolated from the chip test circuit. The relay state reading and data processing are realized by the MCU, and the relay detection can be realized on the test board card. The detection device can be used independently and completely separated from the tester, and can realize detection only by supplying power to the tester, so that extra tester resources are not required to be consumed, and precious test time is not occupied. In addition, compared with the existing relay test circuit, the relay test circuit has the advantages that the switching test of the chip pins is realized only by using one side of the relay, and the other side of the relay is used for outputting response signals generated by the relay under the excitation of the excitation control signals, so that the working states of the relay can be detected while the switching test of different chip pins to be tested is realized.

In addition to detecting the status of a single relay above, the present disclosure may also detect the operational status of a plurality of relays, i.e., a relay array, to enable locating of abnormal relays in the relay array. In the actual test process, the chip test board card can test a plurality of chips in parallel at the same time, the number of the relays used by each chip can be several to tens, more can reach tens, and excitation control signals input into each relay are mutually independent, namely one signal controls one relay. There is no absolute correlation between the excitation control signals input to any two relays, i.e. there are different situations in which the excitation control signals input to each relay, e.g. input to a plurality of corresponding chipsThe excitation control signals of the relays are L respectively ₀ 、L ₁ 、L ₂ 、L ₃ 、L ₄ … where L0 and L1 may be high and low, L ₂ And L is equal to ₃ And may also be different. Because the excitation control signals of all the relays corresponding to each chip are mutually independent, the response signals output by all the relays can be read by the MCU and arranged and combined to form a response signal sequence, and the state combination of the relays corresponding to the first chip is expressed as R ₁ ＝S _n ···S ₄ S ₃ S ₂ S ₁ S ₀ The relay array state of the rest chips tested in parallel is represented as R ₂ 、R ₃ 、R ₄ 、R ₅ ···R _n . In the case of a circuit that is all operating normally and that the excitation control signals input to each chip are identical, the sequence R ₁ 、R ₂ 、R ₃ 、R ₄ 、R ₅ ···R _n If the sequence R2 is different from other sequences, it can be determined that the sequence R2 is wrong, and it can be positioned that the last relay in the sequence R2 is abnormal, then it can be determined that the relay of the chip is abnormal, and then it can alarm and suspend the test operation.

The foregoing description of specific embodiments has been presented only to aid in the understanding of the present disclosure and is not intended to limit the present disclosure. Any local modification or substitution by one of ordinary skill in the art within the scope of the present disclosure is intended to be encompassed within the scope of the present disclosure.

Claims (9)

1. An apparatus for testing a relay for a chip test board, comprising:

the testing machine is used for outputting an excitation control signal;

the relay is used for controlling a chip test channel on the tester to switch and test a chip pin to be tested on the chip based on the excitation control signal;

the detection unit is used for reading the excitation control signal and the response signal output by the relay when the control chip test channel switches and tests the chip pins to be tested on the chip, and detecting the relay by comparing the excitation control signal with the response signal.

2. The apparatus of claim 1, wherein preferably the relay comprises a switching section and an output section, wherein,

the switching part is used for controlling a chip test channel on the tester to perform switching test on the chip pins to be tested based on the excitation control signal;

the output part is used for the switching part to output a response signal when the chip test channel is controlled to perform switching test on the chip pins to be tested based on the excitation control signal.

3. The apparatus of claim 1, wherein the detection unit comprises a micro control unit MCU.

4. The apparatus of claim 1, wherein the apparatus further comprises a voltage stabilizing unit for performing voltage stabilizing control on the relay.

5. A method of testing a relay for a chip test board, comprising the steps of:

s100: outputting an excitation control signal by the testing machine;

s200: the relay controls a chip test channel on the tester to switch and test pins of a chip to be tested on the chip based on the excitation control signal;

s300: the detection unit reads the excitation control signal and the response signal output by the reading relay when the chip test channel is controlled to switch and test the chip pins to be tested on the chip based on the excitation control signal in real time, and detects the relay by comparing the excitation control signal and the response signal.

6. The method according to claim 5, wherein in step S300, if the excitation control signal and the response signal are the same level signals, the relay is normal; if the excitation control signal and the response signal are different level signals, the relay is abnormal.

7. An apparatus for inspecting a plurality of relay arrays for a chip test board, comprising:

the testing machine is used for outputting an excitation control signal;

and the detection unit is used for reading a plurality of response signal sequences output by the relay arrays under the excitation of the excitation control signal, and detecting abnormal relays in the relay arrays by comparing the plurality of response signal sequences.

8. The apparatus of claim 7, wherein the detection unit comprises a micro control unit MCU.

9. A method of inspecting a plurality of relay arrays for a chip test board, comprising the steps of:

s1000: outputting an excitation control signal by the testing machine;

s2000: the detection unit reads a plurality of response signal sequences output by the plurality of relay arrays under the excitation of the excitation control signal;

s3000: comparing the plurality of response signal sequences to detect an abnormal relay in the relay array.

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