CN115877182A - Chip aging test device and method - Google Patents
Chip aging test device and method Download PDFInfo
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- CN115877182A CN115877182A CN202211682941.9A CN202211682941A CN115877182A CN 115877182 A CN115877182 A CN 115877182A CN 202211682941 A CN202211682941 A CN 202211682941A CN 115877182 A CN115877182 A CN 115877182A
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Abstract
The application provides a chip aging test device and a method, the device comprises a connection state detection module, a test control module and an aging control module, wherein the connection state detection module is electrically connected with a chip and is used for detecting whether the connection state between the chip and an aging plate is normal or not when the chip is placed on a test seat of the aging plate, and generating a trigger signal when the detection is normal; the test control module is used for generating an aging confirmation signal according to the trigger signal; and the aging control module is used for allowing the chip aging test device to carry out aging test on the chip according to the aging confirmation signal. This application increases the connection state between chip aging testing device detection chip and the ageing board, can effectively avoid ageing board and chip to carry out aging testing under the condition of connection failure, optimizes chip aging testing effect, improves ageing coverage.
Description
Technical Field
The application relates to the technical field of chip test production, in particular to a chip aging test device and a chip aging test method.
Background
Burn-in testing is often required in order to reject products that may fail early before the chip is delivered for use. The aging test is an accelerated life test performed after packaging, and mainly comprises a voltage test, a current test, a time sequence characteristic test, a function test and the like performed under a high-temperature and high-pressure condition, and the aging test can ensure high aging coverage rate.
With the increase of the scale of the chip, the connection problem between the chip and the test socket of the burn-in board in the burn-in test process is also increased, but the connectivity problem of the chip burn-in test is generally ignored in the chip burn-in test process at present, so that the burn-in board and the chip still carry out the burn-in test under the condition of connection failure, thereby causing the poor burn-in test effect of the chip and influencing the burn-in coverage rate.
Disclosure of Invention
The application provides a chip aging test device and a chip aging test method, which are used for at least solving the problems that the chip aging test effect is poor, the aging coverage rate is influenced and the like caused by aging test under the condition that the connection between an aging board and a chip is failed at present.
According to an aspect of the present application, there is provided a chip burn-in test apparatus including a connection state detection module, a test control module, and a burn-in control module, wherein,
the connection state detection module is electrically connected with the chip and used for detecting whether the connection state between the chip and the aging board is normal or not when the chip is placed on the test seat of the aging board and generating a trigger signal when the connection state is detected to be normal;
the test control module is used for generating an aging confirmation signal according to the trigger signal; and the number of the first and second groups,
and the aging control module is used for allowing the chip aging test device to perform the aging test on the chip according to the aging confirmation signal.
In an embodiment, the connection status detecting module is specifically configured to, when the chip is placed on the test socket of the burn-in board, obtain decoding information of the chip based on the received test instruction sequence, and detect whether the connection status between the chip and the burn-in board is normal based on the decoding information.
In one embodiment, the connection state detection module comprises a controller, a finite state machine and a control generator, wherein the controller is electrically connected with the chip, the finite state machine and the control generator respectively;
the controller is used for testing an instruction sequence when the chip is placed on a test seat of the aging board, checking whether the test instruction sequence is the same as a preset test instruction sequence for starting the aging test, acquiring decoding information of the chip when the checking result is the same, detecting whether the connection states between each pin of the chip and the aging board are normal according to the decoding information, and generating a control signal when the connection states are normal, wherein the control signal is used for driving the finite-state machine to work;
the control generator is used for generating a trigger signal when the finite-state machine reaches a preset working state and sending the trigger signal to the test control module.
In one embodiment, the test control module comprises a clock gate, an AND gate and a flip-flop, and has a signal terminal for receiving the trigger signal and an enable signal terminal for receiving the aging signal, the signal terminal and the enable signal terminal being connected to the flip-flop through the AND gate; the enable signal end is also connected with a clock gate, and when the enable signal end receives an aging signal, the clock gate is conducted; the trigger is used for generating an aging confirmation signal according to the trigger signal and the aging signal after the clock gating is conducted.
In one embodiment, the device further comprises a shielding module,
and the shielding module is used for sending out a shielding signal to shield other signals except the signal generated by the aging test.
According to another aspect of the present application, there is provided a chip burn-in test method, including a connection state detection module, a test control module, and a burn-in control module, wherein the connection state detection module is electrically connected to a chip, the method including:
the connection state detection module detects whether the connection state between the chip and the aging board is normal when the chip is placed on the test seat of the aging board, and generates a trigger signal when the connection state is detected to be normal;
the test control module generates an aging confirmation signal according to the trigger signal; and the number of the first and second groups,
and the aging control module generates an aging test signal according to the aging confirmation signal and allows the chip aging test device to perform the aging test on the chip based on the aging test signal.
In one embodiment, the connection state detection module detects whether a connection state between the chip and the burn-in board is normal when the chip is placed on the test socket of the burn-in board, and includes:
the connection detection module acquires decoding information of the chip based on a received test instruction sequence when the chip is placed on a test seat of the burn-in board, and detects whether the connection state between the chip and the burn-in board is normal or not based on the decoding information.
In one embodiment, the connection status detecting module includes a controller, a finite state machine, and a control generator, the controller is electrically connected to the chip, the finite state machine, and the control generator, respectively, detects whether a connection status between the chip and the burn-in board is normal based on the decoding information, and generates a trigger signal when the connection status is detected to be normal, including:
the controller tests an instruction sequence when the chip is placed on a test seat of an aging board, checks whether the test instruction sequence is the same as a preset test instruction sequence for starting an aging test, acquires decoding information of the chip when the check result is the same, detects whether connection states between pins of the chip and the aging board are normal according to the decoding information, and generates a control signal when the connection states are normal, wherein the control signal is used for driving the finite-state machine to work; and (c) a second step of,
and the control generator judges whether the finite state machine reaches a preset working state, if so, generates a trigger signal and sends the trigger signal to the test control module.
In one embodiment, the test control module comprises a clock gate, an and gate and a flip-flop, and has a signal terminal for receiving the trigger signal and an enable signal terminal for receiving an aging signal, the signal terminal and the enable signal terminal are connected to the flip-flop through the and gate, the enable signal terminal is further connected to the clock gate, and the clock gate is turned on when the enable signal terminal receives the aging signal;
wherein, the test control module generates an aging confirmation signal according to the trigger signal, including: the signal end receives the trigger signal;
the enable signal end receives an aging signal;
and the trigger generates an aging confirmation signal according to the trigger signal and the aging signal after the clock gating is conducted.
In one embodiment, the method further comprises a shielding module, and after the connection state detection module generates the trigger signal, the method further comprises:
the shielding module sends out a shielding signal to shield signals except signals generated by the aging test.
The chip aging test device and method provided by the application are electrically connected with the chip through the connection state detection module, whether the connection state between the chip and the aging board is normal or not is detected when the chip is placed on the test seat of the aging board, the trigger signal is generated when the detection is normal, and then the test control module generates an aging confirmation signal according to the trigger signal, and then the aging confirmation signal is controlled to start through the aging control module, the aging test between the chip and the aging board can be realized, the detection of the connection state between the chip and the aging board in the chip aging test process can be realized, the aging test of the aging board and the chip under the condition of connection failure can be effectively avoided, the chip aging test effect is optimized, and the aging coverage rate is improved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and, together with the description, serve to explain the principles of the application.
Fig. 1 is a schematic view of an application scenario of a chip aging testing apparatus according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a chip aging test apparatus according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of the connection status detecting module 131 in fig. 2;
FIG. 4 is a schematic diagram of the test control module 132 of FIG. 2;
FIG. 5 (a) is a schematic diagram of a chip burn-in test in the related art;
FIG. 5 (b) is a diagram illustrating a chip burn-in test including a test mode for detecting a chip connection state and a test mode for detecting a chip connection state in the embodiment of the present application;
fig. 6 is a second schematic structural diagram of a chip burn-in testing apparatus according to an embodiment of the present application;
fig. 7 is a schematic flowchart of a chip aging test method according to an embodiment of the present disclosure;
fig. 8 is a second flowchart illustrating a chip burn-in testing method according to an embodiment of the present disclosure.
With the above figures, there are shown specific embodiments of the present application, which will be described in more detail below. These drawings and written description are not intended to limit the scope of the inventive concepts in any manner, but rather to illustrate the inventive concepts to those skilled in the art by reference to specific embodiments.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
With the increase of the scale of the chip, the number of pins of the chip is more and more, and the connection problem between the chip and the test socket in the aging test process is also increased gradually. The aging test problem of the chip can be mainly embodied in two aspects, namely that the number of first control pins is large, the frequency of a second non-test core is large, and the two characteristics can cause the connection failure of an aging board and the chip. In order to avoid the problems that the aging test effect of the chip is poor, the aging coverage rate is influenced and the like because the aging test is still carried out under the condition that the connection between the aging board and the chip fails, the connection detection of the aging board and the chip is particularly important.
In the related art, a chip burn-in test is completed by performing or cyclically performing a logic flip test and a memory (RAM) flip test simultaneously in a burn-in test mode. The aged state is observed only by TDO (Test Data Output), and the shift Output result of the scan chain is observed by TDO by configuring core-configuration-chain selection, or the memory Test MBIST operation result is tested. And the connection state of the IO and the aging board except the scanning test control port can not be detected in the logic inversion test and memory (RAM) inversion test mode, and the connection state of the IO and the aging board used in the burn-in test mode can only be detected through TDO, namely, the connection state of part of the IO and the aging board can only be detected through the observation result of TDO in the burn-in test mode. Under the condition, the aging test can not be flexibly started and suspended according to the connection state of the aging board and the chip, and the technical effect of preventing the aging test from being carried out when the connection of the aging board and the chip fails is difficult to achieve.
In another related art, for other Test modes of a chip, although a connection detection manner between the chip and a Test board is proposed, a method for detecting a connection state between the chip and the Test board on an ATE (Automatic Test Equipment) generally needs to configure a Test protocol, and the ATE generates and outputs a stimulus signal, so that the Test cost and the stimulus application amount are difficult to implement on a burn-in board. That is, the connection detection method between the chip and the testing board in the normal chip testing mode cannot be applied to the burn-in test.
In view of this, an embodiment of the present invention provides a chip aging test apparatus added between a chip and an aging board, and with reference to fig. 1, fig. 1 is a schematic view of an application scenario of a possible chip aging test apparatus in an embodiment of the present invention, where the chip aging test apparatus includes an aging board 110, a chip 120, and a chip aging test apparatus 130, where the aging board 110 may include a plurality of test sockets 111, and the chip 120 is placed on the test sockets 111 to be electrically connected to the aging board.
The following describes the technical solution of the present application and how to solve the above technical problems in detail by specific embodiments. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.
Referring to fig. 2, fig. 2 is a diagram of a chip burn-in test apparatus 130 according to an embodiment of the present disclosure, which includes a connection state detection module 131, a test control module 132, and a burn-in control module 133, wherein,
the connection state detection module 131 is electrically connected to the chip, and is configured to detect whether the connection state between the chip and the burn-in board is normal when the chip is placed on the test socket of the burn-in board, and generate a trigger signal when the connection state is detected to be normal.
In this embodiment, when the chip is placed on the test socket of the burn-in board, the decoding information of the chip may be obtained and processed according to the received test instruction sequence, and the connection state between the chip and the burn-in board may be detected according to the decoding information of the chip.
It can be understood that the decoding information of the chip is the decoding information obtained by the decoder, and whether the connection state information of the voltage, the current and the like of each pin of the chip is normal can be detected according to the decoding information; in view of the fact that the chip may perform multiple tests simultaneously in addition to the burn-in test, in this embodiment, decoding information of the chip is obtained according to a received test instruction sequence, where the test instruction sequence may be sequence information input by a tester, in one implementation, by checking the received test instruction sequence, if the received test instruction sequence is preset test instruction sequence information, decoding information of the chip is obtained, and the preset instruction sequence information is function instruction sequence information preset by a system to start a burn-in test process. Illustratively, a worker inputs the preset instruction sequence information in a connection detection mode to enter the detection of the chip connection state, and if the instruction sequence information input by the worker is not the preset instruction sequence information, the worker does not enter the detection of the chip connection state, and starts other test processes according to the corresponding function instruction sequence information input by the worker. The design mode can facilitate the chip to synchronously carry out various tests besides the aging test, and different tests are not influenced mutually.
It should be noted that, those skilled in the art can adaptively set the preset instruction sequence information in combination with the actual application; in addition, the chip is placed on the test seat, and the chip can be directly placed on the test seat or connected to the test seat through a circuit.
In one embodiment, as shown in fig. 3, the connection status detection module 131 comprises a controller 1311, a finite state machine 1312, and a control generator 1313, and the controller 1311 is electrically connected to the chip, the finite state machine 1312, and the control generator 1313, respectively.
It is understood that a Finite State Machine (FSM) is a computing model abstracted for studying the computing process of a Finite memory and some language classes. Finite state automata have a finite number of states, each of which can be migrated to zero or more, input strings determine which state migration is to be performed, and finite state automata can be represented as a directed graph. The controller 1311 is configured to receive a test instruction sequence when the chip is placed on the test socket of the burn-in board, check whether the test instruction sequence is the same as a preset test instruction sequence for starting the burn-in test, acquire decoding information of the chip when the check result is the same, detect whether connection states between pins of the chip and the burn-in board are normal according to the decoding information, and generate a control signal when the connection states are normal, where the control signal is used to drive the finite state machine 1312 to operate.
The control generator 1313 is configured to generate a trigger signal when the finite state machine reaches a preset working state, and send the trigger signal to the test control module.
In this embodiment, whether a received test instruction sequence is the same as a preset test instruction sequence for starting an aging test is checked, it is determined whether a user initiates an aging test process, whether the states of the pins of each chip are all normal is detected according to information such as voltage of the pins of the chip in the obtained decoding information, and a control signal is generated to drive the finite-state machine 1312 to work when the states are all normal, where the finite-state machine 1312 and the control generator 1313 constitute a state analysis module, and the state analysis module analyzes that a trigger signal is generated when the finite-state machine reaches a preset state and sends the trigger signal to the test control module 132.
The finite state machine starts to operate after receiving the control signal, and the control generator generates the trigger signal when the finite state machine is shifted to the preset operating state. Illustratively, a finite state machine includes two states: and the current state and the secondary state execute corresponding actions when the conditions (receiving control signals) are met, and the current state is transferred to the secondary state, wherein the secondary state is the preset working state. In some examples, the finite state machine may also transition to the secondary state directly without performing any action upon receiving the control signal.
The test control module 132 is configured to generate an aging confirmation signal according to the trigger signal.
Compared with the related art, the chip burn-in test is directly carried out through an enabling switch or a functional instruction form, and the connection problem between the chip and the burn-in board is ignored. Only when the trigger signal of the connection state detection module 131 is received, the aging confirmation signal is generated to further control the start of the aging test between the chip and the aging board, so that the aging test of the aging board and the chip under the condition of connection failure is effectively avoided.
In one embodiment, as shown in FIG. 4, the test control module 132 includes
The clock gating CG, the AND gate AND AND the flip-flop D are provided with a signal end a for receiving the trigger signal AND an enable signal end b for receiving the aging signal, AND the signal end a AND the enable signal end b are connected to the flip-flop D through the AND gate; the enable signal end b is also connected with a clock gating CG, and when the enable signal end b receives an aging signal, the clock gating is conducted;
and the trigger D is used for generating an aging confirmation signal according to the trigger signal and the aging signal after the clock gating CG is conducted.
In this example, the test control module 132 comprises a flip-flop D with reset, a clock gating CG, AND an AND gate AND, where the clock of the flip-flop D is controlled by the clock gating CG, AND the enable terminal b of the CG is directly controlled by the aging signal BURNIN _ EN. In other modes, the CG enable is disabled, the output value of the D flip-flop is reset to 0, and the burn-in _ connect signal is 1. The aging signal BURNIN _ EN AND the Trigger signal Trigger jointly control the output of the AND gate AND, AND the AND output end is connected with the D end of the Trigger. That is, in the burn-in test mode, the clock of the flip-flop is active, and the burn-in _ connect signal is determined by the Trigger signal Trigger and the burn-in signal BURNIN _ EN.
The burn-in control module 133 is configured to allow the chip burn-in test apparatus to perform a burn-in test on the chip according to the burn-in confirmation signal.
In this embodiment, after receiving the aging confirmation signal, the aging control module 133 controls to start the aging test between the chip and the aging board, that is, generates a test signal to enter a scan chain/memory to start an aging (test) mode, and the value of the flip-flop or the MBIST operation result in the chip can be shifted out through the scan chain for detection, and outputs an observation signal result. Correspondingly, if the link state verification of the chip pin and the aging board fails, the chip enters a non-aging test mode, and the aging observation result is set to other specified states.
In a specific example, the burn-in test mode may be divided into a test mode for detecting a chip connection state and a test mode for non-detecting a chip connection state, as shown in fig. 5 (a) and 5 (b), and after the technology of the present application is adopted, the Trigger signal Trigger and the burn-in signal BURNIN _ EN jointly control the burn-in mode of the circuit. When BURNIN _ EN jumps from 0 to 1, the chip enters an aging test mode, at the moment, if the Trigger signal is 1, the chip connection state test mode is entered, and if the Trigger signal is 0, the chip connection state test mode is entered. When the BURNIN _ EN signal changes from 1 to 0, the chip exits the burn-in (test) mode.
Referring to fig. 6 and fig. 6 are second schematic structural diagrams of a chip burn-in test apparatus provided in an embodiment of the present application, and based on the second embodiment, in this example, in consideration of problems such as signal interference in a chip burn-in test process, by setting a shielding module to shield other signals except signals generated by the burn-in test, processed signals are clearer and more accurate. As shown in fig. 6, the chip burn-in test apparatus includes a connection state detection module 131, a test control module 132, a burn-in control module 133, a shielding module 134, and a scan chain/memory, wherein the scan chain/memory is used for performing a burn-in test and generating an observation signal.
It should be noted that, the scan chain/memory is a common means for chip testing in the art, and is connected in series to form a long chain consisting of multiple flip-flops by adding a selector before a common flip-flop. The two inputs of the selector are from the scanning input, the other one is from the combinational logic, the data input source of the trigger is selected by the selector controlled by the scanning enabling signal, and in the aging test mode, when the scanning enabling is 1, the chip is in the shift mode. In shift mode, the scan-in value can be shifted into the on-chain flip-flop or the value in the on-chain flip-flop is shifted out of the observation after multiple beats of clock.
In addition, the test design of the chip includes multiple test modes, such as JTAG test, IOMAP test, nand-Tree test, etc., for IO (Input/Output) electrical parameter characteristics, and the control of these test modes can be implemented by using JTAG design, and for each test mode, different JTAG instructions need to be configured and initialization of data registers of corresponding instructions needs to be completed, which is not described in detail in this embodiment.
The shielding module 134 is used for sending out a shielding signal to shield signals except signals generated by the burn-in test.
In an example, after the test control module generates the aging confirmation signal, the aging confirmation signal is synchronously transmitted to the shielding module 134, the shielding module 134 may determine whether to send the shielding signal to the aging control module 133 according to the condition of the aging confirmation signal, and the aging control module 133 may send out a test signal according to the signals sent by the test control module and the shielding module to control the aging test process of starting the scan chain/memory.
Based on the same technical concept, the embodiment of the present application further provides one of chip aging test methods, which includes a connection state detection module, a test control module, and an aging control module, where the connection state detection module is electrically connected to a chip, as shown in fig. 7, and the method includes steps S701 to S704.
Step S701, a connection state detection module detects whether the connection state between the chip and the aging board is normal when the chip is placed on a test seat of the aging board; if so, step S702 is executed, otherwise, the process is ended, and in some embodiments, a non-detection chip connection state detection mode is entered, which is already described in the device embodiments and is not described herein again.
Step S702, the connection state detection module generates a trigger signal;
step S703, the test control module generates an aging confirmation signal according to the trigger signal; and the number of the first and second groups,
and step S704, the aging control module generates an aging test signal according to the aging confirmation signal, and allows the chip aging test device to perform aging test on the chip based on the aging test signal.
In one embodiment, the connection state detection module in step S701 detects whether the connection state between the chip and the burn-in board is normal when the chip is placed on the test socket of the burn-in board, and includes the following steps:
and the connection detection module acquires the decoding information of the chip based on the received test instruction sequence when the chip is placed on the test seat of the aging board, and detects whether the connection state between the chip and the aging board is normal or not based on the decoding information.
In one embodiment, the connection status detection module includes a controller, a finite state machine, and a control generator, the controller is electrically connected to the chip, the finite state machine, and the control generator, respectively, detects whether a connection status between the chip and the burn-in board is normal based on the decoding information, and generates a trigger signal when the connection status is detected to be normal (step S701), including the following steps:
the controller receives a test instruction sequence when the chip is placed on a test seat of the aging board, checks whether the test instruction sequence is the same as a preset test instruction sequence for starting the aging test, acquires decoding information of the chip when the check result is the same, detects whether connection states between pins of the chip and the aging board are normal according to the decoding information, and generates a control signal when the connection states are normal, wherein the control signal is used for driving the finite-state machine to work; and the number of the first and second groups,
and the control generator judges whether the finite-state machine reaches a preset working state, if so, generates a trigger signal and sends the trigger signal to the test control module.
In one embodiment, the test control module includes
The test control module comprises a clock gate, an AND gate and a trigger, and is provided with a signal end for receiving the trigger signal and an enable signal end for receiving an aging signal, wherein the signal end and the enable signal end are connected to the trigger through the AND gate, the enable signal end is also connected with the clock gate, and when the enable signal end receives the aging signal, the clock gate is conducted;
wherein, the test control module generates an aging confirmation signal according to the trigger signal (step S702), including the following steps:
the signal end receives the trigger signal;
the enable signal end receives an aging signal;
and the trigger generates an aging confirmation signal according to the trigger signal and the aging signal after clock gating is conducted.
In one embodiment, the method further comprises a shielding module, and after the connection state detection module generates the trigger signal, the method further comprises the following steps:
the shielding module sends out a shielding signal to shield signals except signals generated by the aging test.
It should be noted that the principle of each step of the method provided in the embodiments of the present application has been described in detail in the embodiments of the apparatus described above, and is not described herein again.
With reference to fig. 8 and fig. 8, a second flow chart of the chip burn-in test method provided in the embodiment of the present application is shown, in which a chip is powered on, a user selects a mode, an burn-in (test) mode is selected if an output signal is BURNIN _ EN =1, other modes are selected if the output signal is BURNIN _ EN =0, in the burn-in mode, pin state verification (i.e., connection state detection) is performed first, if the verification passes, a detection chip connection state burn-in mode is entered, and if the verification fails, a non-detection chip connection state burn-in mode is entered. In particular, the method comprises the steps of,
after the chip is powered on and enters a working mode, the BURNIN _ EN signal is set to be 0, and the chip enters a non-aging mode. The operation in the non-aging mode is irrelevant to the pin state verification, and no matter whether a user carries out the pin state verification or passes the verification, the trigger signal generated by the pin state verification module cannot influence the current operation.
After the chip is powered on, if the chip connection state detection aging mode is required to be entered, the BURNIN _ EN signal is set to be 1 to enter the aging mode, a user performs pin state verification in the aging mode, and after the pin state verification is passed, the chip is switched to the aging mode for detecting the chip connection state.
In the process of entering the aging mode for detecting the connection state of the chip, the trigger signal generated by the connection state detection module is sent to the test control module, the test control module generates a corresponding aging confirmation signal, and the shielding module can further judge whether the aging output result needs to be processed. It can be seen that the test output result in the aging mode of the connection state of the detection chip is the original result after signal shielding, and the test output result in the aging mode of the connection state of the non-detection chip is the result to be processed.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.
Claims (10)
1. A chip aging test device is characterized by comprising a connection state detection module, a test control module and an aging control module, wherein,
the connection state detection module is electrically connected with the chip and used for detecting whether the connection state between the chip and the aging board is normal or not when the chip is placed on the test seat of the aging board and generating a trigger signal when the connection state is detected to be normal;
the test control module is used for generating an aging confirmation signal according to the trigger signal; and the number of the first and second groups,
and the aging control module is used for allowing the chip aging test device to carry out aging test on the chip according to the aging confirmation signal.
2. The apparatus of claim 1, wherein the connection status detecting module is specifically configured to obtain decoding information of the chip when the chip is placed on the test socket of the burn-in board based on the received test command sequence, and detect whether the connection status between the chip and the burn-in board is normal based on the decoding information.
3. The apparatus of claim 2, wherein the connection status detection module comprises a controller, a finite state machine, and a control generator, the controller being electrically connected to the chip, the finite state machine, and the control generator, respectively;
the controller is used for receiving a test instruction sequence when the chip is placed on a test seat of the aging board, verifying whether the test instruction sequence is the same as a preset test instruction sequence for starting the aging test, acquiring decoding information of the chip when the verification result is the same, detecting whether the connection states between the pins of the chip and the aging board are normal according to the decoding information, and generating a control signal when the connection states are normal, wherein the control signal is used for driving the finite-state machine to work;
the control generator is used for generating a trigger signal when the finite-state machine reaches a preset working state and sending the trigger signal to the test control module.
4. The apparatus of claim 1, wherein the test control module comprises a clock gate, an AND gate, and a flip-flop, and has a signal terminal for receiving the trigger signal and an enable signal terminal for receiving an aging signal, the signal terminal and the enable signal terminal being connected to the flip-flop through the AND gate; the enable signal end is also connected with a clock gate, and when the enable signal end receives an aging signal, the clock gate is conducted;
the trigger is used for generating an aging confirmation signal according to the trigger signal and the aging signal after the clock gating is conducted.
5. The apparatus of claim 1, further comprising a shielding module,
and the shielding module is used for sending out a shielding signal to shield other signals except the signal generated by the aging test.
6. The chip aging test method is characterized by comprising a connection state detection module, a test control module and an aging control module, wherein the connection state detection module is electrically connected with a chip, and the method comprises the following steps:
the connection state detection module detects whether the connection state between the chip and the aging board is normal or not when the chip is placed on the test seat of the aging board, and generates a trigger signal when the connection state is detected to be normal;
the test control module generates an aging confirmation signal according to the trigger signal; and the number of the first and second groups,
and the aging control module generates an aging test signal according to the aging confirmation signal and allows the chip aging test device to perform aging test on the chip according to the aging test signal.
7. The method of claim 6, wherein the connection state detection module detects whether the connection state between the chip and the burn-in board is normal when the chip is placed on the test socket of the burn-in board, and comprises:
the connection detection module acquires decoding information of the chip based on a received test instruction sequence when the chip is placed on a test seat of the burn-in board, and detects whether the connection state between the chip and the burn-in board is normal or not based on the decoding information.
8. The method of claim 7, wherein the connection status detection module comprises a controller, a finite state machine and a control generator, the controller is electrically connected to the chip, the finite state machine and the control generator, respectively, detects whether a connection status between the chip and the burn-in board is normal based on the decoded information, and generates a trigger signal when the detection is normal, comprising:
the controller receives a test instruction sequence when the chip is placed on a test seat of an aging board, checks whether the test instruction sequence is the same as a preset test instruction sequence for starting an aging test, acquires decoding information of the chip when the check result is the same, detects whether connection states between pins of the chip and the aging board are normal according to the decoding information, and generates a control signal when the connection states are normal, wherein the control signal is used for driving the finite-state machine to work; and the number of the first and second groups,
and the control generator judges whether the finite-state machine reaches a preset working state, if so, generates a trigger signal and sends the trigger signal to the test control module.
9. The method of claim 6, wherein the test control module comprises a clock gate, an AND gate and a flip-flop, and has a signal terminal for receiving the trigger signal and an enable signal terminal for receiving an aging signal, the signal terminal and the enable signal terminal being connected to the flip-flop through the AND gate, the enable signal terminal being further connected to a clock gate, the clock gate being turned on when the enable signal terminal receives the aging signal;
wherein, the test control module generates an aging confirmation signal according to the trigger signal, and comprises:
the signal end receives the trigger signal;
the enable signal end receives an aging signal;
and the trigger generates an aging confirmation signal according to the trigger signal and the aging signal after clock gating is conducted.
10. The method of claim 6, further comprising a shielding module, after the connection status detection module generates a trigger signal, the method further comprising:
the shielding module sends out shielding signals to shield signals except signals generated by the aging test.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116699372A (en) * | 2023-08-08 | 2023-09-05 | 北京燧原智能科技有限公司 | Chip burn-in test circuit |
| CN117521588A (en) * | 2024-01-08 | 2024-02-06 | 深圳中安辰鸿技术有限公司 | Control method and device for preventing non-uniform aging of integrated circuit and processing chip |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116699372A (en) * | 2023-08-08 | 2023-09-05 | 北京燧原智能科技有限公司 | Chip burn-in test circuit |
| CN116699372B (en) * | 2023-08-08 | 2023-11-07 | 北京燧原智能科技有限公司 | Chip burn-in test circuit |
| CN117521588A (en) * | 2024-01-08 | 2024-02-06 | 深圳中安辰鸿技术有限公司 | Control method and device for preventing non-uniform aging of integrated circuit and processing chip |
| CN117521588B (en) * | 2024-01-08 | 2024-05-10 | 深圳中安辰鸿技术有限公司 | Control method and device for preventing non-uniform aging of integrated circuit and processing chip |
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