CN116137521A - Cascade integral comb filter circuit, filtering method and analog-to-digital conversion system - Google Patents

Cascade integral comb filter circuit, filtering method and analog-to-digital conversion system Download PDF

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Publication number
CN116137521A
CN116137521A CN202111356084.9A CN202111356084A CN116137521A CN 116137521 A CN116137521 A CN 116137521A CN 202111356084 A CN202111356084 A CN 202111356084A CN 116137521 A CN116137521 A CN 116137521A
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integrator
comb
filter circuit
path
output
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祝天市
沈天平
刘玉芳
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CRM ICBG Wuxi Co Ltd
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CRM ICBG Wuxi Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/06—Non-recursive filters
    • H03H17/0621—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing
    • H03H17/0635—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies
    • H03H17/0671—Cascaded integrator-comb [CIC] filters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0223—Computation saving measures; Accelerating measures
    • H03H2017/0245—Measures to reduce power consumption
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
    • Y02E40/40—Arrangements for reducing harmonics

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

The invention provides a cascade integral comb filter circuit, a filter method and an analog-to-digital conversion system, which comprise the following steps: n-path integrators, each integrator receives an input signal and performs integration processing on the corresponding input signal; the multiplexer is connected with the output end of each integrator, and sequentially selects and outputs the output signals of each integrator; the comb is connected with the output end of the multiplexer and sequentially carries out differential processing on each path of signals output by the multiplexer; the demultiplexer is connected with the output end of the comb and sequentially transmits each path of signal subjected to differential processing to a corresponding output port; wherein N is a natural number greater than 1. The invention combines a plurality of CIC filters, and a plurality of integrators share one comb device, so that the area can be greatly saved; and the time sequence control for extracting the output data of the three groups of integrators is realized by using only one counter, so that the power consumption is reduced to a certain extent.

Description

Cascade integral comb filter circuit, filtering method and analog-to-digital conversion system
Technical Field
The present invention relates to the field of integrated circuit design, and in particular, to a cascaded integrator-comb filter circuit, a filtering method, and an analog-to-digital conversion system.
Background
CIC (Cascaded Integrator Comb), i.e. an integrating comb filter, is often used as a high-efficiency filter for engineering applications to process a large amount of data collected by a high-speed a/D converter, and the number of CIC filters affects the stop band attenuation, so that three-stage CIC filters are often used for engineering applications to process the data. As shown IN fig. 1, the input signal adc_in of the CIC filter is a signal generated by superimposing a sine wave with a lower frequency and a high frequency signal, when the oversampling rate is far greater than the frequency of the input signal, the input signal is first modulated and converted into a dense wave, and the dense wave passes through the filter to obtain the output signal cic_out, as can be seen from fig. 1, wherein the high frequency component is filtered, and meanwhile, the information contained IN the low frequency component of the input signal is also more completely saved.
Typically a CIC filter can only work with one modulator, processing a set of data. However, when multiple groups of ADCs with the same configuration are required to work simultaneously, multiple groups of CIC filters are required to be used for processing data respectively, as shown in fig. 2, three CIC filters are arranged in parallel, an input signal is received and processed respectively to obtain corresponding output signals, and a configurator configures each CIC filter through multiple counters; the filter includes a large number of calculation processes, which are reflected to a complex circuit, and thus occupies a large area, and a plurality of counters are needed to control the extraction process of the integrator output data, so that the power consumption is high.
Therefore, how to solve the problems of large occupied area and high power consumption when a plurality of groups of filters are matched for use has become one of the problems to be solved in the urgent need of the technicians in the field.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention is directed to providing a cascaded integrator-comb filter circuit, a filtering method and an analog-to-digital conversion system, which are used for solving the problems of large occupied area, high power consumption and the like when a plurality of groups of filter circuits are matched in the prior art.
To achieve the above and other related objects, the present invention provides a cascaded integrator-comb filter circuit, comprising:
n-path integrators, each integrator receives an input signal and performs integration processing on the corresponding input signal;
the multiplexer is connected with the output end of each integrator, and sequentially selects and outputs the output signals of each integrator;
the comb is connected with the output end of the multiplexer and sequentially carries out differential processing on each path of signals output by the multiplexer;
the demultiplexer is connected with the output end of the comb and sequentially transmits each path of signal subjected to differential processing to a corresponding output port;
wherein N is a natural number greater than 1.
Optionally, the integrator comprises M stages of integration modules connected in series, wherein M is a natural number greater than or equal to 1.
More optionally, the comb comprises M stages of differential modules connected in series.
More optionally, the cascaded integrator-comb filter circuit further includes a first counter, where the first counter is connected to each integrator, and counts the number of integration times of each integrator to determine a timing sequence of output signals of each integrator.
More optionally, the cascaded integrator-comb filter circuit further includes a second counter, where the second counter is connected to the comb, and counts the differential times of the comb to control the working state transition of the cascaded integrator-comb filter circuit.
To achieve the above and other related objects, the present invention provides a filtering method, based on the above cascaded integrator-comb filter circuit, the filtering method at least includes:
1) Initializing the cascade integration comb filter circuit;
2) The N-path integrator starts working at the same time, signals of one-path integrator are transmitted to the comb, differential processing is carried out on output signals of the integrator based on the comb, and signals are output to corresponding output ports after the differential processing is finished;
3) Selecting the signal of the next integrator, repeating the step 2) until the signals in each integrator are differentiated to obtain N paths of output signals, and returning to the step 1);
wherein the time of the primary differentiation processing is longer than the time of the primary integration processing.
Optionally, the filtering method further includes: and respectively counting the integration times of each path of integrator, and outputting signals of the corresponding integrator when the integration times of each path of integrator reach the corresponding over-sampling value.
Optionally, the filtering method further includes: and counting the differential times of the comb, and filtering N paths of data once when the differential times of the comb reach a preset value and the differential processing of the current path of signals is completed.
To achieve the above and other related objects, the present invention provides an analog-to-digital conversion system, including at least:
the N sigma-delta modulation circuits and the cascade integral comb filter circuit are connected to the output ends of the sigma-delta modulation circuits.
As described above, the cascade integral comb filter circuit, the filtering method and the analog-to-digital conversion system have the following beneficial effects:
1. the cascade integration comb filter circuit, the filtering method and the analog-to-digital conversion system combine a plurality of groups of CIC filters, and a plurality of integrators share one comb, so that the area can be greatly saved.
2. The cascade integral comb filter circuit, the filtering method and the analog-to-digital conversion system of the invention realize the time sequence control of extracting the output data of three groups of integrators only by using one counter, and reduce the power consumption to a certain extent.
Drawings
Fig. 1 shows waveforms of input and output signals of a CIC filter according to the prior art.
Fig. 2 is a schematic diagram of a structure of a plurality of CIC filters in the prior art when they are used simultaneously.
Fig. 3 shows a schematic diagram of a cascaded integrator-comb filter circuit according to the present invention.
Fig. 4 shows a schematic structure of the integrator of the present invention.
Fig. 5 is a schematic diagram of a comb of the present invention.
Fig. 6 is a schematic diagram showing the operation state transition of the filtering method of the present invention.
Fig. 7 shows a timing diagram of the filtering method of the present invention.
Fig. 8 is a schematic structural diagram of an analog-to-digital conversion system according to the present invention.
Description of element reference numerals
1. Cascade integral comb filter circuit
11a first integrator
11b second integrator
11c third integrator
12. Multiplexer for multiplexing
13. Comb device
14. Demultiplexer
2. Sigma-delta modulation circuit
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 3-8. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Example 1
As shown in fig. 3, the present embodiment provides a cascaded integrator-comb filter circuit 1, the cascaded integrator-comb filter circuit 1 comprising: an N-way integrator, a multiplexer 12, a comb 13 and a demultiplexer 14.
As shown in fig. 3, the integrators are arranged in parallel, and each integrator receives an input signal and performs integration processing on the corresponding input signal.
Specifically, in the present embodiment, N is set to 3; in actual use, the value of N can be set according to actual needs, and N is a natural number greater than 1.
Specifically, in the present embodiment, each integrator is denoted as a first integrator 11a, a second integrator 11b, and a third integrator 11c, respectively; the first integrator 11a receives a first input signal IN1 and integrates the first input signal IN 1; the second integrator 11b receives a second input signal IN2 and integrates the second input signal IN 2; the third integrator 11c receives a third input signal IN3 and integrates the third input signal IN 3.
More specifically, each integrator includes M stages of integration modules 111 connected in series, where M is a natural number equal to or greater than 1. In the present embodiment, M is set to 3, and as shown in fig. 4, the integration modules 111 operate simultaneously.
As shown in fig. 3, the multiplexer 12 is connected to the output terminals of the respective integrators, and sequentially selects and outputs the output signals of the respective integrators.
Specifically, the multiplexer 12 alternatively outputs the output signal of the first integrator 11a, the second integrator 11b, or the third integrator 11 c. The multiplexer 12 decimates the time nodes of the output signals of the preceding integrator to ensure that the preceding input signals do not overlap the data processed in the succeeding combiners.
As an implementation manner of the present invention, the cascaded integrator-comb filter circuit 1 further includes a first counter (not shown in the figure), where the first counter is connected to each integrator, and counts the number of times of integration of each integrator to determine the timing of the output signal of each integrator. Specifically, each integrator corresponds to an over-sampling value, and when the integration times of each integrator reach the corresponding over-sampling value, the integration signals of the corresponding channels are output.
As shown in fig. 3, the comb 13 is connected to the output end of the multiplexer 12, and sequentially performs differential processing on each path of signals output from the multiplexer 12.
Specifically, the comb 13 includes M-stage serial differential modules 131, and the number of stages of the differential modules 131 is consistent with the number of stages of the integrating modules 111 in the integrator. In this embodiment, a 3-stage differentiation module 131 is included, as shown in fig. 5.
As shown in fig. 3, the demultiplexer 14 is connected to the output of the comb 13, and sequentially transmits the signals subjected to the differentiation processing to the corresponding output ports.
Specifically, the demultiplexer 14 receives the output signal of the comb 13, and outputs each signal in a time-sharing manner to obtain a first output signal Out1, a second output signal Out2, and a third output signal Out3 corresponding to the input signal. The time node of the output signal of the demultiplexer 14 ensures that the differentiation of the current signal is completed.
As another implementation manner of the present invention, the cascaded integrator-comb filter circuit 1 further includes a second counter (not shown in the figure), where the second counter is connected to the comb 13, and counts the differential times of the comb 13, so as to control the switching of the operating state of the cascaded integrator-comb filter circuit. Specifically, it can be determined whether the differentiation of the current signal is completed or not by the number of differentiation times of the comb 13. Specifically, it may also be determined whether the filtering of the N-way data is completed once by the number of differentiation times of the comb 13 (i.e., the output data of each integrator is differentiated via the comb 13).
Example two
As shown in fig. 3 and fig. 6 to fig. 7, the present embodiment provides a filtering method, based on the cascaded integrator-comb filter circuit 1 of the first embodiment, the cic filter processing data is divided into three steps, namely, integrating delay processing, extracting and differentiating delay processing. The filtering method comprises the following steps:
1) Initializing the cascaded integrator-comb filter circuit.
2) The N-path integrator starts working at the same time, signals of one-path integrator are transmitted to the comb, differential processing is carried out on output signals of the integrator based on the comb, and signals are output to corresponding output ports after the differential processing is finished; wherein the time of the primary differentiation processing is longer than the time of the primary integration processing.
As an example, the number of times of integration of each path integrator is counted separately, and when the number of times of integration of each path integrator reaches the corresponding over-sampling value, the signal of the corresponding integrator is output.
3) And (3) selecting the signal of the next integrator, repeating the step (2) until the signals in the integrators are differentiated to obtain N paths of output signals, and returning to the step (1).
As an example, the number of differentiation times of the comb is counted, and filtering of N-way data is achieved once when the number of differentiation times of the comb reaches a preset value and the differentiation process of the current-way signal is completed.
Specifically, as shown in fig. 6 and 7, the filtering method of the present invention is described based on a working state transition diagram and a timing diagram;
(a) The cascaded integrator-comb filter circuit 1 is in an IDLE state (IDLE) after reset, where the combiners 13 of each integrator stage are in a reset state, and enter an initial state when the enable signal cic _en is active.
(b) In the initial state, the demultiplexer 14 completes the initialization based on an operation clock cic _clk, and after the initialization is completed, the cascaded integrator-comb filter circuit 1 enters the integrator state.
(c) When the cascade integrating comb filter circuit 1 is in an integrating state, the three-way integrator starts to work, the first counter cnt1 starts to work, each working clock cic _clk three-way integrator can perform integration once, the count value cnt1 of the first counter can be increased by one, and output results acc0, acc1 and acc2 of the three-way integrator are respectively stored in the registers. When the count value cnt1 does not reach the configured first oversampling value osr1, the state machine is not changed; when the count value of the first counter cnt1 reaches the first oversampling value, the multiplexer 12 transmits the stored value data1 in the register storing the data of the first integrator 11a to the comb 13 while entering the differential state.
(d) In the differential state, the comb 13 performs three differential processes on the input first path data at the high level of cnt00, cnt01 and cnt02, the first-stage differential module output signal comb0 outputs data7 after the high level of cnt00, the second-stage differential module output signal comb1 outputs data10 after the high level of cnt01, the third-stage differential module output signal comb2 outputs data13 after the high level of cnt02, the demultiplexer 14 outputs the processed result data13, a process completion flag comb_flag is generated, and the state machine returns to the integral state.
(e) After returning to the integrating state, repeating the step (c), when the count value cnt1 of the first counter reaches the second oversampling value osr2, the multiplexer 12 will transmit the stored value data3 in the register storing the data of the second integrator 11b to the comb 13, and then execute the step (d) to differentiate the output signal of the second integrator 11b, where the first stage differentiating module output signal comb0 outputs data8 after cnt04 is high level, the second stage differentiating module output signal comb1 outputs data11 after cnt05 is high level, the third stage differentiating module output signal comb2 outputs data14 after cnt06 is high level, and after the end, a processing completion flag comb_flag is generated, and the state machine returns to the integrating state again.
(f) After returning to the integrating state, repeating the step (c), when the count value cnt1 of the first counter reaches the third oversampling value osr3, the multiplexer 12 will transmit the stored value data5 in the register storing the data of the third integrator 11c to the comb 13, and then execute the step (d) to perform differential processing on the output signal of the third integrator 11c, where the first stage differential module output signal comb0 outputs data9 after cnt08 high level, the second stage differential module output signal comb1 outputs data12 after cnt09 high level, the third stage differential module output signal comb2 outputs data15 after cnt0a high level, and generate a processing completion flag comb_flag after finishing; meanwhile, the second counter counts the differential times of the comb 13, and in this embodiment, a third-order filter is used, so the maximum count value cnt2 is 2' b10 (preset value), the specific count value can be adjusted according to practical application, and the third signal finishes differentiating the count value cnt2 of the second counter to reach the preset value; at this time, the demultiplexer 14 outputs three output signals, the state machine enters a complete state, and once data processing is completed, and data13, data14 and data15 are the once conversion results of the three groups of ADCs.
(g) After entering a completion state, generating an A/D conversion completion mark, and returning the cascade integration comb filter circuit 1 to an initial state to continue integration, wherein output results acc0, acc1 and acc2 of the three-way integrator correspond to data2, data4 and data6 respectively; if the enable signal cic _en is not active at this time, the idle state is returned.
It should be noted that, as long as the enable signal cic _en of the cascaded integrator-comb filter circuit 1 is valid, all the integrators continuously operate, and each time the signal transmitted by any integrator is processed by the integrator, a completion flag is generated, which indicates that the corresponding ADC conversion is completed. Typically the integration is a continuous process and the comb section is differentiated from the decimated signal, typically at a higher oversampling rate in engineering applications, so that the time per differentiation is much longer than the time per integration, and so the comb section can be shared.
Example III
As shown in fig. 8, the present embodiment provides an analog-to-digital conversion system including: n sigma-delta modulation circuits 2 and the cascaded integrator-comb filter circuit 1 of the first embodiment.
Specifically, the number of sigma-delta modulation circuits 2 corresponds to the number of data input ports of the cascaded integrator-comb filter circuit 1, and in this embodiment, N is set to 3. The cascaded integrator-comb filter circuit 1 is connected to the output terminal of each of the sigma-delta modulation circuits 2, and filters the output signals of each of the sigma-delta modulation circuits 2. The signal is subjected to oversampling and noise shaping processing by a sigma-delta modulation circuit 2 to obtain a dense wave, and then is subjected to digital filtering and decimation by a cascade integral comb filter circuit 1 to be converted into useful data.
The cascade integration comb filter circuit, the filtering method and the analog-to-digital conversion system combine a plurality of groups of CIC filters, and a plurality of integrators share one comb, so that the area can be greatly saved; and only one counter is used (based on the first counter count up to osr, osr2 and osr3, and three counters count up to osr1, osr2 and osr3 respectively) so as to realize the time sequence control for extracting the output data of the three groups of integrators, and reduce the power consumption to a certain extent.
In summary, the present invention provides a cascaded integrator-comb filter circuit, a filtering method and an analog-to-digital conversion system, which includes: n-path integrators, each integrator receives an input signal and performs integration processing on the corresponding input signal; the multiplexer is connected with the output end of each integrator, and sequentially selects and outputs the output signals of each integrator; the comb is connected with the output end of the multiplexer and sequentially carries out differential processing on each path of signals output by the multiplexer; the demultiplexer is connected with the output end of the comb and sequentially transmits each path of signal subjected to differential processing to a corresponding output port; wherein N is a natural number greater than 1. The invention includes three integrators, three groups of data flows generated by the modulators are processed by three-stage integration delay in the three integrators respectively, in engineering application, a higher oversampling rate is needed, corresponding to the higher sampling rate, so each group of data has a larger sampling time relative to each integration time, in the period, one comb is enough to do three-stage differential delay processing to the three groups of data respectively, and a specific path of data enters the comb and is selected by a multiplexer, after the comb processes one group of data, the data is supplied to the multiplexer before the next group of data arrives, so that the data is prevented from being covered, the multiplexer module outputs the data as a group of A/D conversion values (each group of output corresponds to an input signal) and simultaneously generates an A/D conversion completion mark, and then the multiplexer selects the next group of data to the comb for processing, so that the purposes of reducing the area and the power consumption of the filter can be achieved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (9)

1. A cascaded integrator-comb filter circuit, said cascaded integrator-comb filter circuit comprising at least:
n-path integrators, each integrator receives an input signal and performs integration processing on the corresponding input signal;
the multiplexer is connected with the output end of each integrator, and sequentially selects and outputs the output signals of each integrator;
the comb is connected with the output end of the multiplexer and sequentially carries out differential processing on each path of signals output by the multiplexer;
the demultiplexer is connected with the output end of the comb and sequentially transmits each path of signal subjected to differential processing to a corresponding output port;
wherein N is a natural number greater than 1.
2. The cascaded integrator-comb filter circuit of claim 1 wherein: the integrator comprises M stages of integration modules connected in series, wherein M is a natural number greater than or equal to 1.
3. The cascaded integrator-comb filter circuit of claim 2 wherein: the comb includes M stages of differential modules connected in series.
4. A cascaded integrator-comb filter circuit as claimed in any one of claims 1 to 3, wherein: the cascade integration comb filter circuit further comprises a first counter, wherein the first counter is connected with each path of integrator, and counts the integration times of each path of integrator to determine the time sequence of output signals of each path of integrator.
5. The cascaded integrator-comb filter circuit of claim 4 wherein: the cascade integral comb filter circuit further comprises a second counter, wherein the second counter is connected with the comb and counts the differential times of the comb so as to control the working state conversion of the cascade integral comb filter circuit.
6. A filtering method using a cascaded integrator-comb filter circuit according to any one of claims 1-5, characterized in that the filtering method comprises at least:
1) Initializing the cascade integration comb filter circuit;
2) The N-path integrator starts working at the same time, signals of one-path integrator are transmitted to the comb, differential processing is carried out on output signals of the integrator based on the comb, and signals are output to corresponding output ports after the differential processing is finished;
3) Selecting the signal of the next integrator, repeating the step 2) until the signals in each integrator are differentiated to obtain N paths of output signals, and returning to the step 1);
wherein the time of the primary differentiation processing is longer than the time of the primary integration processing.
7. The filtering method of claim 6, wherein: the filtering method further comprises the following steps: and respectively counting the integration times of each path of integrator, and outputting signals of the corresponding integrator when the integration times of each path of integrator reach the corresponding over-sampling value.
8. The filtering method of claim 6, wherein: the filtering method further comprises the following steps: and counting the differential times of the comb, and filtering N paths of data once when the differential times of the comb reach a preset value and the differential processing of the current path of signals is completed.
9. An analog to digital conversion system, comprising at least:
n sigma-delta modulation circuits and a cascaded integrator-comb filter circuit according to any of claims 1-5, said cascaded integrator-comb filter circuits being connected to the output of each sigma-delta modulation circuit.
CN202111356084.9A 2021-11-16 2021-11-16 Cascade integral comb filter circuit, filtering method and analog-to-digital conversion system Pending CN116137521A (en)

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