CN201854251U - High-speed real-time band rejection filter based on CPLD (complex programmable logic device) - Google Patents
High-speed real-time band rejection filter based on CPLD (complex programmable logic device) Download PDFInfo
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- CN201854251U CN201854251U CN200920048865XU CN200920048865U CN201854251U CN 201854251 U CN201854251 U CN 201854251U CN 200920048865X U CN200920048865X U CN 200920048865XU CN 200920048865 U CN200920048865 U CN 200920048865U CN 201854251 U CN201854251 U CN 201854251U
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Abstract
The utility model provides an implementation method for a signal processing system based on a CPLD (complex programmable logic device), which is capable of completing high-speed real-time filtering tasks. A serial A/D (analog to digital) module (I) is used for acquiring analog quantity, the analog quantity is converted and then transmitted to a digital filtering module (II) for digital signal processing, finally the analog quantity is outputted by a serial D/A (digital to analog) module (III) instruction, and the implementation method can be seen on an attached map of an instruction book abstract. The digital filter algorithm in the implementation method is capable of helping in suppression of special band signals rapidly and effectively, and can be realized based on the CPLD. In addition, the A/D module and the D/A module adopt a high-speed conversion mode, so that the system can be applied to high-speed and even ultrahigh-speed signal processing occasions for high-speed real-time filtering.
Description
Technical field
The utility model relates to digital information processing system in the industrial circle, especially at a high speed or the technology of ultrahigh speed Real-Time Filtering, and specifically a kind of high-speed real-time band stop filter based on CPLD.
Background technology
At present, common digital information processing system is generally by the A/D modular converter, and digital filtering module and D/A modular converter are formed.Analog signal, is exported through the D/A modular converter after the digital filtering module processing by the input of A/D modular converter.Digital filtering module is the core here, and the general at present microprocessor that adopts is realized filtering algorithm with software.But in some occasion, such as the occasion that need handle in real time high speed signal, said system is unable to do what one wishes with regard to some, and the speed of service of software can't satisfy the requirement of real-time.Adopt programmable logic device (CPLD), realize filtering algorithm, can improve the processing speed of filtration module effectively, can carry out real time signal processing in high speed even ultrahigh speed occasion with hardware mode.
Summary of the invention
The purpose of this utility model is to satisfy the problem of mission requirements under high speed or ultrahigh speed occasion at the existing digital information processing system of major part, the digital signal processing system of design one cover, make at a high speed in addition the ultrahigh speed occasion under signal processing more stable more accurate.
The technical solution of the utility model is:
A kind of real-time band stop filter based on CPLD, it gathers analog quantity by serial a/d module (I), send digital filtering module (II) to carry out Digital Signal Processing through conversion, is exported with analog quantity by serial D/A module (III) at last.
Wherein the feature of digital filtering module (II) be it mainly by A/D interface circuit (1), several parts compositions such as number tape resistance filtering operation circuit (2) and D/A output circuit (3) are seen accompanying drawing 1.The input of A/D interface circuit (1) output corresponding with A/D converter (I) links to each other, the input of number tape resistance filtering operation circuit (2) output corresponding with A/D interface circuit (1) links to each other, the input of D/A output circuit (3) output corresponding with number tape resistance filtering operation (2) links to each other, and the output of D/A output circuit (3) links to each other with D/A converter (III) corresponding input end.
The utlity model has following advantage:
The utility model can be realized real-time " trap " of special frequency band scope handled by the digital signal that is converted to through high-speed a/d is carried out Real-Time Filtering at the real-time band stop filter based on CPLD of the System Signal Processing under high speed even the ultrahigh speed occasion.
In digital processing field, CPLD is the processing speed of its superelevation compared to the advantage of special dsp chip or FPGA, and time predictability preferably.Thereby be particularly suitable for being used for carrying out real time signal processing, widened the application of signal processing system.
Description of drawings
Fig. 1 is the signal processing system structural representation that is made of the utility model.
Fig. 2 is a composition structured flowchart schematic diagram of the present utility model.
Fig. 3 is A/D converter and the utility model connection diagram.
Fig. 4 is the utility model and D/A converter connection diagram.
Specific embodiments
Following structure accompanying drawing and embodiment are further described the utility model:
As shown in Figures 1 and 2.
A kind of real-time band stop filter of single-chip control, it is mainly by A/D interface circuit (1), and number tape resistance filtering operation circuit (2) and D/A output circuit (3) are formed.
The input of A/D interface circuit (1) output corresponding with A/D converter (I) links to each other, the input of number tape resistance filtering operation circuit (2) output corresponding with A/D interface circuit (1) links to each other, the input of D/A output circuit (3) output corresponding with number tape resistance filtering operation (2) links to each other, and the output of D/A output circuit (3) links to each other with D/A converter (III) corresponding input end.
The utility model adopts CPLD to realize the function of digital real-time band stop filter, can carry out high speed even ultrahigh speed Real-Time Filtering, fast and effeciently filters out the signal of special frequency band.By serial communication mode A/D converter, D/A converter and chip body are coupled together, constitute system for real-time signal processing.The annexation of the utility model in whole signal processing system as shown in Figure 1.
Based on the actual demand in the industrial production, type of the present utility model adopts band stop filter, and its effective trap scope is that 9900Hz is to 11100Hz.
Based on the requirement of high-speed real-time filtering, adopt iir filter in the realization of the utility model algorithm, than the FIR filter, its amplitude-frequency characteristic precision is higher, has guaranteed the accuracy of system effectively.The iir filter type of specifically selecting for use is an elliptic filter, though the passband of elliptic filter is not the most smooth, but the narrowest transition band is arranged, under equal index, elliptic filter is balance passband and stopband more reasonably, both guaranteed accurate inhibition, the excessive attenuation that has prevented passband had been arranged stopband.
Consider that higher order filter can make algorithm complicated, the utility model adopts quadravalence in the selection of filter order, and the complexity that makes algorithm is in suitable scope.
Calculates among the CPLD and be generally fixed-point number, and digital filter coefficient is a floating number that the utility model has carried out quantification treatment to these floating numbers.The method that adopts is the quantization method of the n power of convergent-divergent 2, and coefficient with multiply by suitable zoom factor, is turned to integer, difference equation at last again divided by this zoom factor.Zoom factor is selected suitably can be the ERROR CONTROL that is caused by coefficient quantization in very little scope, though can lose very little a part of precision, coefficient quantization has reduced hardware resource greatly, thereby has greatly improved arithmetic speed.
The A/D modular converter that the utility model adopts is the tlc1543 of Texas Instruments company, is controlled by the A/D control module.This chip has 11 tunnel analog input channels, and integrated sampling-maintenance functional module adopts the CMOS technology, and noise is low, Heat stability is good.The frequency of chip selection signal/CS is consistent by A/D control module and systematic sampling frequency, considers the requirement of real-time, and A/D translative mode preference pattern 1 is changed fast, has guaranteed real-time.Tlc1543 is output as serial data, and A/D interface circuit of the present utility model will realize that the string of data changes and function.A/D interface circuit and tlc1543 interface schema are seen Fig. 3.
The D/A converter that the utility model adopts is the tlc5615 of Texas Instruments company, is controlled by the D/A control module.This chip power-consumption is low, and Heat stability is good, refresh rate have effectively guaranteed the rapidity of data transaction up to 1.21MHz.Realize the clock synchronization of clock signal and CPLD by the D/A output circuit.Tlc5615 is input as serial data, and is that D/A output circuit of the present utility model will be realized data and change the string function.D/A output circuit and tlc6515 interface schema are seen Fig. 4.
Consider that the increase of filter figure place has improved the precision of computing on the one hand, also increased hardware spending on the other hand, lowered speed.In addition, for matching with A/D control module and D/A control module, the utility model is selected 10 on the processing figure place, the parallel digital filter of sending into of 10 bit data, output 10 parallel-by-bit data after " trap " handled.
The course of work of the present utility model is as follows:
Behind system's electrifying startup, because the algorithm core of digital filter is a difference equation, so system is since second sampling period operate as normal.The A/D interface circuit of CPLD requires the work schedule of control tlc1543 according to control, make analog signal convert 10 bit-serial digital signals to behind the tlc1543 sample quantization and send into CPLD, the A/D interface circuit utilizes shift function that 10 Bits Serial data are converted to 10 parallel-by-bit data.Next these 10 parallel-by-bit data become one group of 10 new parallel-by-bit data through the treatment conversion of band stop filter, it will and change string manipulation by the D/A output circuit and become 10 Bits Serial data, and convert the output of target simulation amount to by tlc5615 under this circuit control control.9900Hz will farthest be suppressed to the frequency component in the 11100Hz scope in the analog signal of output, thereby realizes accurate filtering.Because the high arithmetic speed of CPLD cooperates the quick conversion of A/D, D/A, adds the rapidity of algorithm filter itself, conversion speed of the present utility model is guaranteed.As seen the utility model can be used for carrying out high speed even ultrahigh speed Real-Time Filtering fully.
Claims (4)
1. the real-time band stop filter of single-chip control, it is characterized in that it is mainly by A/D control module (1), digital band-reject filter (2) and D/A control module (3) are formed, the input of A/D control module (1) output corresponding with A/D converter (I) links to each other, the input of digital band-reject filter (2) output corresponding with A/D control module (1) links to each other, the input of D/A control module (3) output corresponding with digital band-reject filter (2) links to each other, and the output of D/A control module (3) links to each other with D/A converter (III) corresponding input end.
2. the real-time band stop filter of single-chip according to claim 1 control is characterized in that described digital filter (2) adopts the quadravalence elliptic filter to realize, the trap scope be 9900Hz to 11100Hz, the processing figure place of band stop filter is 10.
3. the real-time band stop filter of single-chip according to claim 1 control is characterized in that the work schedule of A/D control module (1) control A/D converter wherein, and the string of the line data of going forward side by side changes also to be handled.
4. the real-time band stop filter of single-chip according to claim 1 control is characterized in that the work schedule of D/A control module (3) control D/A converter wherein, the line data of going forward side by side and change string manipulation.
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| Application Number | Priority Date | Filing Date | Title |
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| CN200920048865XU CN201854251U (en) | 2009-10-30 | 2009-10-30 | High-speed real-time band rejection filter based on CPLD (complex programmable logic device) |
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| CN200920048865XU CN201854251U (en) | 2009-10-30 | 2009-10-30 | High-speed real-time band rejection filter based on CPLD (complex programmable logic device) |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103078606A (en) * | 2012-12-28 | 2013-05-01 | 京信通信系统（中国）有限公司 | Multichannel CIC (Cascaded Integrator Comb) interpolation-filter system and implementation method thereof |
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2009
- 2009-10-30 CN CN200920048865XU patent/CN201854251U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103078606A (en) * | 2012-12-28 | 2013-05-01 | 京信通信系统（中国）有限公司 | Multichannel CIC (Cascaded Integrator Comb) interpolation-filter system and implementation method thereof |
| CN103078606B (en) * | 2012-12-28 | 2016-03-16 | 京信通信系统（中国）有限公司 | Multichannel CIC interpolation filter system and its implementation |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110601 Termination date: 20121030 |