CN116131818A - Double frequency reference clock circuit, chip and electronic equipment - Google Patents
Double frequency reference clock circuit, chip and electronic equipment Download PDFInfo
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- CN116131818A CN116131818A CN202310412315.6A CN202310412315A CN116131818A CN 116131818 A CN116131818 A CN 116131818A CN 202310412315 A CN202310412315 A CN 202310412315A CN 116131818 A CN116131818 A CN 116131818A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
- H03K5/05—Shaping pulses by increasing duration; by decreasing duration by the use of clock signals or other time reference signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/00006—Changing the frequency
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/131—Digitally controlled
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
Abstract
The embodiment of the application relates to the field of integrated circuits and discloses a frequency doubling reference clock circuit, a chip and electronic equipment. The digital control module in the frequency doubling reference clock circuit is used for transmitting a first calibration signal to the first calibration loop according to a first delay clock and a reference clock generated by the first calibration loop through the delay reference clock, and calibrating the first calibration loop so that the first calibration loop generates a first calibration clock transmitted to the frequency doubling module; and transmitting a second calibration signal to the second calibration loop according to a second delay clock and the first calibration clock generated by the second calibration loop through the delay reference clock, and calibrating the second calibration loop so that the second calibration loop generates a second calibration clock transmitted to the frequency doubling module; the frequency doubling module is used for generating a frequency doubling reference clock according to the first calibration clock and the second calibration clock, realizing the duty ratio calibration of the reference clock with low power consumption, and simultaneously enabling the generated frequency doubling reference clock to reduce noise in a loop.
Description
Technical Field
The embodiment of the application relates to the technical field of integrated circuits, in particular to a frequency doubling reference clock circuit, a chip and electronic equipment.
Background
The frequency synthesizer is a core module for generating a local oscillation signal in a wireless communication chip, the performance of the frequency synthesizer basically depends on the cleanliness of an input reference clock, and a crystal oscillator (crystal oscillator) is generally adopted to generate the reference clock, but the crystal oscillator has lower crystal oscillation frequency and larger frequency division coefficient, so that the gain multiple of in-band noise is increased, and excellent phase noise performance is difficult to realize. The above problem can be solved by multiplying the reference clock, for example, the input reference clock is xored with the delayed reference clock to generate a double frequency clock, and the double frequency clock requires the duty ratio of the reference clock to be accurate to 50%, so that the double frequency reference clock is prevented from generating periodic fast and slow frequencies, and periodic spurious signals are generated in the double frequency circuit. Therefore, how to implement the duty cycle calibration of the input reference clock is particularly important.
In order to realize an accurate 50% duty ratio calibration loop, one method is to perform RC low-frequency filtering on a reference clock to obtain a direct current level, and then adjust the delay time of a delay chain or delay buffer threshold voltage according to a comparison result of the direct current level and 1/2 of the working voltage of a circuit so as to realize duty ratio adjustment of the reference clock, wherein the RC circuit adopted by the method has larger occupied area and high power consumption; the other method is to adjust the duty ratio of the reference clock by using a digital delay chain calibration loop, and the rising edge and the falling edge of the reference clock are needed to participate simultaneously, so that the calibration loop needs to ensure that the duty ratio of the input and output reference clocks is kept unchanged, and the requirements on each parameter of the circuit are higher and are difficult to realize.
Disclosure of Invention
An object of the embodiment of the present application is to provide a frequency doubling reference clock circuit, a chip and an electronic device, which can realize duty cycle calibration of a reference clock with low power consumption, so that the generated frequency doubling reference clock can reduce noise in a loop, and the occupied area of the circuit is small.
To solve the above technical problem, an embodiment of the present application provides a frequency doubling reference clock circuit, including: the device comprises a first calibration loop, a second calibration loop, a digital control module and a frequency doubling module, wherein the first calibration loop and the second calibration loop are both connected with the digital control module, and the first calibration loop and the second calibration loop are both connected with the frequency doubling module; the first calibration loop is used for delaying an input reference clock to generate a first delay clock and inputting the first delay clock to the digital control module, and the second calibration loop is used for delaying the reference clock to generate a second delay clock and inputting the second delay clock to the digital control module; the digital control module is used for sending a first calibration signal to the first calibration loop according to the first delay clock and the reference clock, wherein the first calibration signal is used for calibrating the first calibration loop so that the first calibration loop generates a first calibration clock and sends the first calibration clock to the frequency doubling module; the digital control module is further configured to send a second calibration signal to the second calibration loop according to the second delay clock and the first calibration clock, where the second calibration signal is used to calibrate the second calibration loop, so that the second calibration loop generates a second calibration clock, and send the second calibration clock to the frequency doubling module; the frequency doubling module is used for generating a frequency doubling reference clock according to the first calibration clock and the second calibration clock.
The embodiment of the application also provides a chip which comprises the frequency doubling reference clock circuit.
The embodiment of the application also provides electronic equipment comprising the chip.
The frequency doubling reference clock circuit comprises a first calibration loop, a second calibration loop, a digital control module and a frequency doubling module, wherein the first calibration loop is used for delaying an input reference clock to generate a first delay clock, inputting the first delay clock to a connected digital control module, the second calibration loop is used for delaying the input reference clock to generate a second delay clock, inputting the second delay clock to the connected digital control module, the digital control module is used for sending a first calibration signal to the first calibration loop according to the first delay clock and the reference clock so as to calibrate the first calibration loop, enabling the first calibration loop to generate a first calibration clock sent to the frequency doubling module, the digital control module is further used for sending a second calibration signal to the second calibration loop according to the second delay clock and the first calibration clock so as to calibrate the second calibration loop, enabling the second calibration loop to generate a second calibration clock sent to the frequency doubling module, and the frequency doubling module is used for generating a frequency doubling reference clock according to the first calibration clock and the second calibration clock. The delayed reference clocks are calibrated through the two calibration loops respectively, namely the duty ratio of the delayed reference clocks is calibrated, the calibration clocks meeting the requirement of the required duty ratio can be obtained, the frequency doubling clocks are generated based on the generated two paths of calibration clocks, the periodic spurious signals generated in the frequency doubling circuits due to the fact that the frequency doubling reference clocks generate periodic fast and slow frequencies due to the fact that the duty ratio is not met can be avoided, in addition, the generated frequency doubling reference clocks can reduce noise in the loops, and compared with the RC circuit, the frequency doubling reference clocks are small in occupied area and low in power consumption.
In addition, the first calibration loop includes a first digitally controlled delay cell and a second digitally controlled delay cell; the first calibration signal is specifically used for calibrating the first numerical control delay unit and the second numerical control delay unit, so that the first numerical control delay unit generates a first-stage calibration clock delayed by 1/2 period of the reference clock, and the second numerical control delay unit generates a second-stage calibration clock delayed by 1 period of the reference clock; the digital control module is specifically configured to output the second calibration signal according to the second delay clock and the primary calibration clock.
In addition, the first calibration loop comprises a first numerical control delay unit, a second numerical control delay unit, a third numerical control delay unit and a fourth numerical control delay unit; the first calibration signal is further used for calibrating the first numerical control delay unit, the second numerical control delay unit, the third numerical control delay unit and the fourth numerical control delay unit, so that the first numerical control delay unit generates a first-stage calibration clock delayed by 1/4 period of the reference clock, the second numerical control delay unit generates a second-stage calibration clock delayed by 1/2 period of the reference clock, the third numerical control delay unit generates a third-stage calibration clock delayed by 3/4 period of the reference clock, and the fourth numerical control delay unit generates a fourth-stage calibration clock delayed by 1 period of the reference clock; the digital control module is further configured to output the second calibration signal according to the second delay clock and the second calibration clock.
In addition, the second calibration loop comprises a fine-tuning numerical control delay unit and an OR gate circuit; the second calibration signal is specifically used for calibrating the fine-tuning numerical control delay unit, so that the fine-tuning numerical control delay unit generates a five-stage calibration clock delayed by a period of a preset length of the reference clock; the OR gate circuit is used for outputting the second calibration clock according to the five-stage calibration clock and the reference clock, and the falling edge of the second calibration clock is delayed by 1/2 period from the rising edge of the reference clock.
In addition, the frequency doubling module is specifically configured to generate the frequency doubling reference clock according to a first calibration clock delayed by 1/4 period from the reference clock and a second calibration clock delayed by 1/2 period from a rising edge of the reference clock.
In addition, the frequency doubling reference clock circuit further comprises a data selector which is respectively connected with the first calibration loop and the second calibration loop; the data selector is used for detecting the duty ratio of the reference clock, inputting the reference clock into the first calibration loop and the second calibration loop for the reference clock with the duty ratio smaller than the preset standard duty ratio, inverting the reference clock with the duty ratio larger than the standard duty ratio, inputting the inverted reference clock into the first calibration loop and the second calibration loop, so that the first calibration loop generates the first delay clock, and the second calibration loop generates the second delay clock, thereby realizing calibration of different duty ratios of the reference clock, and realizing a more comprehensive calibration range.
In addition, the frequency doubling reference clock circuit further comprises a crystal oscillator buffer circuit, and the crystal oscillator buffer circuit is connected with the data selector; the crystal oscillator buffer circuit is used for detecting the duty ratio of the reference clock, adjusting the duty ratio of the reference clock under the condition that the difference value between the duty ratio of the reference clock and the standard duty ratio is larger than a first preset threshold value, and inputting the adjusted reference clock to the data selector; the difference value between the duty ratio of the adjusted reference clock and the standard duty ratio is smaller than the first preset threshold value, so that the calibration range of the duty ratio of the reference clock is further enlarged, and the generated frequency doubling reference clock circuit can reduce noise in a loop.
In addition, the crystal oscillator buffer circuit comprises a PMOS tube and an NMOS tube; the crystal oscillator buffer circuit is specifically configured to adjust the duty ratio of the reference clock by adjusting the channel width or the channel length of the PMOS tube or adjusting the channel width or the channel length of the NMOS tube when detecting that the difference between the duty ratio of the reference clock and the standard duty ratio is greater than a first preset threshold, so as to adjust the duty ratio of the reference clock to be within a calibration range required by the first calibration loop and the second calibration loop.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which the figures of the drawings are not to be taken in a limiting sense, unless otherwise indicated.
FIG. 1 is a specific block diagram I of a double frequency reference clock circuit provided in accordance with one embodiment of the present application;
FIG. 2 is a second specific block diagram of a double frequency reference clock circuit provided according to one embodiment of the present application;
FIG. 3 is a third specific block diagram of a double frequency reference clock circuit provided in accordance with one embodiment of the present application;
fig. 4 is a block diagram of a first calibration loop and a second calibration loop provided in accordance with one embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, as will be appreciated by those of ordinary skill in the art, in the various embodiments of the present application, numerous technical details have been set forth in order to provide a better understanding of the present application. However, the technical solutions claimed in the present application can be implemented without these technical details and with various changes and modifications based on the following embodiments. The following embodiments are divided for convenience of description, and should not be construed as limiting the specific implementation of the present application, and the embodiments may be mutually combined and referred to without contradiction.
The embodiment of the application provides a frequency doubling reference clock circuit, which is characterized in that two calibration loops are used for calibrating delayed reference clocks respectively, namely, the duty ratio of the delayed reference clocks is calibrated, the calibration clocks meeting the requirement of the required duty ratio can be obtained, the frequency doubling clocks are generated based on the generated two paths of calibration clocks, the periodic frequency increase and the periodic frequency decrease of the frequency doubling reference clocks due to the fact that the duty ratio is not met can be avoided, periodic stray signals are generated in the frequency doubling circuits, namely, the frequency doubling reference clocks with low phase noise are realized, and compared with the RC circuit, the frequency doubling reference clock circuit is small in occupied area and low in power consumption.
Implementation details of the frequency doubling reference clock circuit in the embodiment of the present application are specifically described below, and the following details are provided for understanding only, and are not necessary to implement the present embodiment.
In some embodiments, the specific structure of the frequency doubling reference clock circuit is shown in fig. 1, and includes: the first calibration loop 11, the second calibration loop 12, the digital control module 13 and the frequency doubling module 14, wherein the first calibration loop 11 and the second calibration loop 12 are connected with the digital control module 13, and the first calibration loop 11 and the second calibration loop 12 are also connected with the frequency doubling module 14.
Specifically, the first calibration loop 11 is configured to receive an input reference clock X, the reference clock may be a reference clock generated by a crystal oscillator, the first calibration loop 11 delays the reference clock to generate a first delayed clock, then inputs the first delayed clock to the digital control module 13, and the reference clock is simultaneously input to the digital control module 13, so that the digital control module 13 sends a first calibration signal to the first calibration loop 11 according to the first delayed clock and the reference clock, and the first calibration signal is used for calibrating the first calibration loop 11, so that the first calibration loop 11 generates the first calibration clock, and sends the first calibration clock to the frequency doubling module 14. It will be appreciated that the first calibration signal is generated based on the delay time of the first delay clock relative to the reference clock, and the delay time of the first calibration clock output by the calibrated first calibration loop 11 is determined by the first calibration signal sent by the digital control module 13.
The second calibration loop 12 is also configured to receive the input reference clock, delay the reference clock to generate a second delayed clock, and then input the second delayed clock to the digital control module 13, where the digital control module 13 is configured to send a second calibration signal to the second calibration loop 12 according to the second delayed clock input by the second calibration loop 12 and the first calibration clock input by the first calibration loop, where the second calibration signal is configured to calibrate the second calibration loop 12, so that the second calibration loop 12 generates the second calibration clock, and send the second calibration clock to the frequency doubling module 14. It will be appreciated that the second calibration signal is generated based on the delay time of the second delay clock relative to the first calibration clock, and the delay time of the second calibration clock output by the calibrated second calibration loop 12 is determined by the second calibration signal sent by the digital control module 13.
The frequency doubling module 14 is configured to receive the first calibration clock sent by the first calibration loop 11 and the second calibration clock sent by the second calibration loop 12, and generate a frequency doubling reference clock according to the first calibration clock and the second calibration clock.
In some embodiments, the specific structure of the frequency doubling reference clock circuit may be as shown in fig. 2, including: the device comprises a first calibration loop 11, a second calibration loop 12, a digital control module 13, a frequency doubling module 14, a data selector 15 and a crystal oscillator buffer circuit 16. The data selector 15 is connected to the first calibration loop 11 and the second calibration loop 12, and the crystal oscillator buffer circuit 16 is connected to the data selector 15.
The data selector 15 is configured to detect a duty cycle of an input reference clock, for a reference clock with a duty cycle smaller than a preset standard duty cycle, input the reference clock to the first calibration loop 11 and the second calibration loop 12, invert the reference clock with a duty cycle larger than the standard duty cycle, and input the inverted reference clock to the first calibration loop 11 and the second calibration loop 12, so that the first calibration loop 11 generates a first delay clock, and the second calibration loop 12 generates a second delay clock. The reference clock inverting is to delay the phase of the input reference clock by 180 degrees, the standard duty cycle is to take 50%, namely, the reference clock with the duty cycle smaller than 50% is directly input to the first calibration loop 11 and the second calibration loop 12, the reference clock with the duty cycle larger than 50% is inverted, so that the duty cycle of the reference clock is smaller than 50%, and then the reference clock is input to the first calibration loop 11 and the second calibration loop 12. Therefore, the embodiment not only can carry out duty cycle calibration on the reference clock with the duty cycle smaller than the standard duty cycle, but also can carry out duty cycle calibration on the reference clock with the duty cycle larger than the standard duty cycle, so that the calibration on different duty cycles of the reference clock is realized, and the calibration range is more comprehensive.
The crystal oscillator buffer circuit 16 is configured to detect a duty cycle of an input reference clock, adjust the duty cycle of the reference clock when detecting that a difference between the duty cycle of the reference clock and a standard duty cycle is greater than a first preset threshold, and input the adjusted reference clock to the data selector 15; the difference value between the duty ratio of the adjusted reference clock and the standard duty ratio is smaller than a first preset threshold value. Wherein the first preset threshold is set by a person skilled in the art according to actual needs. In this embodiment, before the reference clock is input into the data selector 15, the duty cycle of the reference clock is adjusted by the crystal oscillator buffer circuit 16 to a reference clock with a duty cycle that deviates from the standard duty cycle by a relatively large amount, so that the duty cycle of the reference clock can be adjusted to a value close to the standard duty cycle, the calibration range of the duty cycle of the reference clock is further enlarged, and the influence on the calibration performance of the first calibration loop 11 and the second calibration loop 12 when the duty cycle of the reference clock deviates from the standard duty cycle by a relatively large amount is avoided, thereby ensuring the low phase noise performance of the finally generated double frequency reference clock.
In one example, the crystal oscillator buffer circuit 16 includes a PMOS transistor and an NMOS transistor, and the crystal oscillator buffer circuit 16 is specifically configured to adjust the duty cycle of the reference clock to be within a calibration range required by the first calibration loop and the second calibration loop by adjusting the channel width or the channel length of the PMOS transistor or adjusting the channel width or the channel length of the NMOS transistor when detecting that the difference between the duty cycle of the reference clock and the standard duty cycle is greater than the first preset threshold. The channel width and the channel length of the PMOS tube and the NMOS tube have a certain corresponding relation with the duty ratio of the reference clock, and the proportion change of the channel width of the PMOS tube and the channel width of the NMOS tube or the proportion change of the channel length of the PMOS tube and the NMOS tube can be realized by adjusting the channel width or the channel length of the PMOS tube or the channel width or the channel length of the NMOS tube, so that the duty ratio of the reference clock is adjusted. For example, the channel length of the PMOS tube includes N gears, the ratio of the channel length of each gear to the channel length of the current NMOS tube corresponds to the duty ratio of a reference clock, and then the duty ratio of the reference clock can be adjusted by adjusting the gears of the channel length of the PMOS tube, or the channel length of the NMOS tube includes N gears, the ratio of the channel length of each gear to the channel length of the current PMOS tube corresponds to the duty ratio of a reference clock, and then the duty ratio of the reference clock can be adjusted by adjusting the gears of the channel length of the NMOS tube. The manner of adjusting the duty ratio of the reference clock based on the channel widths of the PMOS and NMOS transistors is similar and will not be described in detail herein.
It will be appreciated that the input reference clock is first subjected to a first duty cycle adjustment by the crystal oscillator buffer circuit 16, then input to the data selector 15 to determine whether a second duty cycle adjustment is required, and finally input to the first calibration loop 11 and the second calibration loop 12 for subsequent operations.
In some embodiments, the specific structure of the frequency doubling reference clock circuit is shown in fig. 3, and the first calibration loop 11 specifically includes a first digitally controlled delay unit 111, a second digitally controlled delay unit 112, a third digitally controlled delay unit 113, and a fourth digitally controlled delay unit 114. The first calibration signal is specifically used for calibrating the first digital control delay unit 111, the second digital control delay unit 112, the third digital control delay unit 113 and the fourth digital control delay unit 114, so that the first digital control delay unit 111 generates a first-stage calibration clock delayed by 1/4 period of the reference clock, the second digital control delay unit 112 generates a second-stage calibration clock delayed by 1/2 period of the reference clock, the third digital control delay unit 113 generates a third-stage calibration clock delayed by 3/4 period of the reference clock, and the fourth digital control delay unit 114 generates a fourth-stage calibration clock delayed by 1 period of the reference clock.
In one example, the first calibration loop 11 further includes a first comparator 115 as shown in fig. 2, where a first input end of the first comparator 115 is connected to the first calibration loop 11, a second input end is used for accessing a reference clock, and an output end is connected to the digital control module 13, that is, the input of the first comparator 115 is a first delay clock and a reference clock, and output is a first comparison clock, and the digital control module 13 specifically outputs a first calibration signal for calibrating the first calibration loop 11 according to the first comparison clock. It can be seen that the first comparator 115 here corresponds to a trigger for triggering the digital control module 13 to output the first calibration signal.
In a specific implementation, the first calibration signal sequentially calibrates the first nc delay unit 111, the second nc delay unit 112, the third nc delay unit 113, and the fourth nc delay unit 114, and calibration contents of the first nc delay unit 111, the second nc delay unit 112, the third nc delay unit 113, and the fourth nc delay unit 114 include: the first calibration signal sequentially performs the high-gear clock calibration, the medium-gear clock calibration, and the low-gear clock calibration of the first digital control delay unit 111 first, then sequentially performs the high-gear clock calibration, the medium-gear clock calibration, and the low-gear clock calibration of the second digital control delay unit 112, then sequentially performs the high-gear clock calibration, the medium-gear clock calibration, and the low-gear clock calibration of the third digital control delay unit 113, and finally sequentially performs the high-gear clock calibration, the medium-gear clock calibration, and the low-gear clock calibration of the fourth digital control delay unit 114. The first calibration clock of the first digitally controlled delay unit 111, the second calibration clock of the second digitally controlled delay unit 112, the third calibration clock of the third digitally controlled delay unit 113, and the fourth calibration clock of the fourth digitally controlled delay unit 114 may be obtained. At this time, the output first comparison clock of the first comparator 115 is turned over between 1 and 0, which marks that the first calibration clock generated by the first digital control delay unit 111 is delayed by 1/4 period from the reference clock, the second calibration clock generated by the second digital control delay unit 112 is delayed by 1/2 period from the reference clock, the third calibration clock generated by the third digital control delay unit 113 is delayed by 3/4 period from the reference clock, and the fourth calibration clock generated by the fourth digital control delay unit 114 is delayed by 1 period from the reference clock.
The second calibration loop 12 specifically includes a fine-tuning digital control delay unit 121 and an or circuit 122, where the second calibration signal is specifically used to calibrate the fine-tuning digital control delay unit 121, so that the fine-tuning digital control delay unit 121 generates a five-stage calibration clock delayed by a period of a preset length from the reference clock; the or circuit 122 is configured to output a second calibration clock according to the five-stage calibration clock and the reference clock, and a falling edge of the second calibration clock is delayed by 1/2 period from a rising edge of the reference clock.
In one example, the second calibration loop further includes an adjusting unit (not shown in the figure), which is connected to the second digital delay unit 112 of the first calibration loop 11, and is configured to adjust the second calibration clock output by the second digital delay unit 112, and send the adjusted second calibration clock to the digital control module 13, so that the digital control module 13 outputs a second calibration signal, and based on this, the second calibration loop is calibrated to generate a second calibration clock with an accurate falling edge delayed by 1/2 period from the rising edge of the reference clock.
In one example, the second calibration loop 12 further includes a second comparator 123 as shown in fig. 2, where a first input end of the second comparator 123 is connected to the second calibration loop 12, a second input end is connected to the first calibration loop 11, and an output end is connected to the digital control module 13, that is, an input of the second comparator 123 is a second delay clock and a first calibration clock, and output is a second comparison clock, and the digital control module 13 specifically outputs a second calibration signal for calibrating the second calibration loop 12 according to the second comparison clock. It can be seen that the second comparator 123 here corresponds to a trigger for triggering the digital control module 13 to output the second calibration signal.
In a specific implementation, the second calibration clock (i.e. the calibration clock delayed by 1/2 period from the reference clock) generated by the second digital delay unit 112 of the first calibration loop 11 and the reference clock are input to the second comparator 123, so that the second comparator 123 outputs the second comparison clock, and the digital control module 13 is triggered to output the second calibration signal for calibrating the fine-tuning digital delay unit 121 of the second calibration loop 12. The fine-tuning digital control delay unit 121 is calibrated to generate a five-stage calibration clock delayed by a period of a preset length from the reference clock, and then inputs the five-stage calibration clock to the or circuit 122, and simultaneously inputs the reference clock to the or circuit 122, so that the or circuit 122 outputs a second calibration clock according to the five-stage calibration clock and the reference clock. At this time, the output of the second comparator 123 will flip between 1 and 0, indicating that the falling edge of the second calibration clock is precisely delayed 1/2 period from the rising edge of the reference clock. The period length of the five-stage calibration clock delayed from the reference clock may be set by those skilled in the art according to needs, and it is only necessary to ensure that the or circuit 122 precisely delays the rising edge of the reference clock by 1/2 period according to the falling edge of the second calibration clock output by the five-stage calibration clock and the reference clock.
It can be seen that the falling edge of the second calibration clock is precisely delayed by 1/2 period from the rising edge of the reference clock, and the duty cycle of the second calibration clock is the duty cycle of the reference clock after calibration is completed. The second calibration clock and the first calibration clock of the first digital control delay unit 111 are input to the frequency doubling module 14 to generate a frequency doubling reference clock circuit, i.e. the first calibration clock of the embodiment is the first calibration clock of the first digital control delay unit 111. In addition, the first calibration loop 11 and the second calibration loop 12 in this embodiment can complete the duty ratio calibration of the reference clock within 20us, without affecting the normal start of the phase-locked loop control circuit (Phase Locked Loop, PLL).
That is, the frequency doubling module 14 is specifically configured to generate a frequency-doubled reference clock according to a first calibration clock delayed by 1/4 period from the reference clock and a second calibration clock delayed by 1/2 period from the rising edge of the reference clock. In one example, the frequency doubling module 14 is an exclusive nor circuit as shown in fig. 2, that is, the frequency doubling module 14 performs exclusive nor calculation on the second calibration clock and the first calibration clock to obtain a frequency doubling reference clock circuit, and in this embodiment, the duty ratio of the second calibration clock is the duty ratio of the calibrated reference clock, so that the generated frequency doubling reference clock circuit does not introduce large noise, and a frequency doubling reference clock circuit with low phase noise is realized, and the circuit occupies a small area and has low cost.
In some embodiments, the first calibration loop 11 may only include the first digital control delay unit 411 and the second digital control delay unit 412 as shown in fig. 4, where the first calibration signal is specifically used to calibrate the first digital control delay unit 311 and the second digital control delay unit 412, so that the first digital control delay unit 411 generates a first-stage calibration clock delayed by 1/2 period from the reference clock, and the second digital control delay unit 412 generates a second-stage calibration clock delayed by 1 period from the reference clock. The structure of the second calibration loop 12 is similar to the above-described embodiments and will not be described again here.
In a specific implementation, the primary calibration clock (i.e. the calibration clock delayed by 1/2 period from the reference clock) generated by the first nc delay unit 411 of the first calibration loop 11 and the reference clock are input to the second comparator 123, so that the second comparator 123 outputs a second comparison clock, and triggers the digital control module 13 to output a second calibration signal for calibrating the fine tuning nc delay unit 121 of the second calibration loop 12. The subsequent operation performed by the second calibration loop 12 generates the second calibration clock, and the specific implementation process of the second calibration loop 12 is not described herein.
It can be seen that this embodiment is another implementation manner for implementing the duty cycle calibration of the reference clock, and the duty cycle of the second calibration clock output based on this embodiment is also the duty cycle of the reference clock after the calibration is completed.
In some embodiments, on the basis of the frequency-doubled reference clock circuit described in any one of the above embodiments, the frequency-doubled reference clock circuit further includes a temperature tracking module, where the temperature tracking module is connected to the first calibration loop 11 and the second calibration loop 12 respectively; the temperature tracking module is configured to, when detecting that a change value of an operating temperature of the frequency doubling reference clock circuit is greater than a second preset threshold, adjust a first calibration clock output by the first calibration loop 11 and a second calibration clock output by the second calibration loop 12, respectively, and send the adjusted first calibration clock and second calibration clock to the frequency doubling module 14. Wherein the second preset threshold may be set by a person skilled in the art according to actual needs. In some embodiments, the temperature tracking module may also be a software module, which is configured to monitor the current temperature in real time, and adjust the first calibration clock output by the first calibration loop 11 and the second calibration clock output by the second calibration loop 12.
It should be noted that, the foregoing examples in the present embodiment are all examples for understanding and are not limited to the technical solution of the present invention.
Another embodiment of the present application relates to a chip comprising a frequency doubling reference clock circuit according to any one of the above embodiments.
It is to be noted that this embodiment is a chip embodiment corresponding to the above-described method embodiment, and this embodiment may be implemented in cooperation with the above-described circuit embodiment. The related technical details and technical effects mentioned in the above embodiments are still valid in this embodiment, and in order to reduce repetition, they are not described here again. Accordingly, the related technical details mentioned in the present embodiment can also be applied to the above-described embodiments.
In addition, in order to highlight the innovative part of the present application, elements that are not so close to solving the technical problem presented in the present application are not introduced in the present embodiment, but it does not indicate that other elements are not present in the present embodiment.
Another embodiment of the present application relates to an electronic device, including the chip described in the foregoing embodiment.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the present application and that various changes in form and details may be made therein without departing from the spirit and scope of the embodiments herein. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the embodiments herein, and the scope of the embodiments herein should be assessed accordingly.
Claims (10)
1. A double frequency reference clock circuit, comprising: the device comprises a first calibration loop, a second calibration loop, a digital control module and a frequency doubling module, wherein the first calibration loop and the second calibration loop are both connected with the digital control module, and the first calibration loop and the second calibration loop are both connected with the frequency doubling module;
the first calibration loop is used for delaying an input reference clock to generate a first delay clock and inputting the first delay clock to the digital control module, and the second calibration loop is used for delaying the reference clock to generate a second delay clock and inputting the second delay clock to the digital control module;
the digital control module is used for sending a first calibration signal to the first calibration loop according to the first delay clock and the reference clock, wherein the first calibration signal is used for calibrating the first calibration loop so that the first calibration loop generates a first calibration clock and sends the first calibration clock to the frequency doubling module;
the digital control module is further configured to send a second calibration signal to the second calibration loop according to the second delay clock and the first calibration clock, where the second calibration signal is used to calibrate the second calibration loop, so that the second calibration loop generates a second calibration clock, and send the second calibration clock to the frequency doubling module;
the frequency doubling module is used for generating a frequency doubling reference clock according to the first calibration clock and the second calibration clock.
2. The doubled reference clock circuit of claim 1, wherein the first calibration loop comprises a first digitally controlled delay cell and a second digitally controlled delay cell;
the first calibration signal is specifically used for calibrating the first numerical control delay unit and the second numerical control delay unit, so that the first numerical control delay unit generates a first-stage calibration clock delayed by 1/2 period of the reference clock, and the second numerical control delay unit generates a second-stage calibration clock delayed by 1 period of the reference clock;
the digital control module is specifically configured to output the second calibration signal according to the second delay clock and the primary calibration clock.
3. The double frequency reference clock circuit of claim 1, wherein the first calibration loop comprises a first digitally controlled delay cell, a second digitally controlled delay cell, a third digitally controlled delay cell, and a fourth digitally controlled delay cell;
the first calibration signal is further used for calibrating the first numerical control delay unit, the second numerical control delay unit, the third numerical control delay unit and the fourth numerical control delay unit, so that the first numerical control delay unit generates a first-stage calibration clock delayed by 1/4 period of the reference clock, the second numerical control delay unit generates a second-stage calibration clock delayed by 1/2 period of the reference clock, the third numerical control delay unit generates a third-stage calibration clock delayed by 3/4 period of the reference clock, and the fourth numerical control delay unit generates a fourth-stage calibration clock delayed by 1 period of the reference clock;
the digital control module is further configured to output the second calibration signal according to the second delay clock and the second calibration clock.
4. The doubled reference clock circuit of claim 3, wherein the second calibration loop comprises a fine digitally controlled delay cell and an or gate circuit;
the second calibration signal is specifically used for calibrating the fine-tuning numerical control delay unit, so that the fine-tuning numerical control delay unit generates a five-stage calibration clock delayed by a period of a preset length of the reference clock;
the OR gate circuit is used for outputting the second calibration clock according to the five-stage calibration clock and the reference clock, and the falling edge of the second calibration clock is delayed by 1/2 period from the rising edge of the reference clock.
5. The frequency doubling reference clock circuit according to claim 4, wherein the frequency doubling module is specifically configured to generate the frequency doubling reference clock according to a first calibration clock delayed by 1/4 period from the reference clock and a second calibration clock delayed by 1/2 period from a rising edge of the reference clock.
6. The doubled reference clock circuit of any one of claims 1 to 5, further comprising a data selector connected to the first calibration loop and the second calibration loop, respectively;
the data selector is used for detecting the duty ratio of the reference clock, inputting the reference clock into the first calibration loop and the second calibration loop for the reference clock with the duty ratio smaller than the preset standard duty ratio, inverting the reference clock with the duty ratio larger than the standard duty ratio, inputting the inverted reference clock into the first calibration loop and the second calibration loop, so that the first calibration loop generates the first delay clock, and the second calibration loop generates the second delay clock.
7. The double frequency reference clock circuit of claim 6, further comprising a crystal buffer circuit, the crystal buffer circuit being coupled to the data selector;
the crystal oscillator buffer circuit is used for detecting the duty ratio of the reference clock, adjusting the duty ratio of the reference clock under the condition that the difference value between the duty ratio of the reference clock and the standard duty ratio is larger than a first preset threshold value, and inputting the adjusted reference clock to the data selector; wherein the difference between the duty cycle of the adjusted reference clock and the standard duty cycle is less than the first preset threshold.
8. The double frequency reference clock circuit of claim 7, wherein the crystal oscillator buffer circuit comprises a PMOS tube and an NMOS tube;
the crystal oscillator buffer circuit is specifically configured to adjust the duty ratio of the reference clock by adjusting the channel width or the channel length of the PMOS tube or adjusting the channel width or the channel length of the NMOS tube when it is detected that the difference between the duty ratio of the reference clock and the standard duty ratio is greater than a first preset threshold.
9. A chip comprising a doubled reference clock circuit according to any one of claims 1 to 8.
10. An electronic device comprising the chip of claim 9.
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