CN116130440A

CN116130440A - Semiconductor flip-chip packaging structure and manufacturing method thereof

Info

Publication number: CN116130440A
Application number: CN202211642731.7A
Authority: CN
Inventors: 万亮
Original assignee: Jingyi Semiconductor Co ltd
Current assignee: Jingyi Semiconductor Co ltd
Priority date: 2022-09-27
Filing date: 2022-12-20
Publication date: 2023-05-16
Also published as: CN116435276A

Abstract

A flip-chip package structure of semiconductor and its fabrication method are disclosed. The semiconductor flip-chip package structure has a conductive rewiring layer and a corrosion barrier layer. The corrosion barrier layer is used for completely covering the top surface and the side surface of the conductive rewiring layer, and extends outwards from the root of the side surface of the conductive rewiring layer to cover part of the top surface of the passivation layer, so that leakage and even short circuit between rewiring layers are prevented. The etch stop layer may be formed using a sputtering process. The semiconductor flip-chip packaging structure has high reliability, and meanwhile, the process consistency is good and the yield is high when the semiconductor flip-chip packaging structure is manufactured.

Description

Semiconductor flip-chip packaging structure and manufacturing method thereof

Technical Field

Embodiments of the present invention relate to semiconductor devices, and more particularly, to a semiconductor flip-chip package structure and a method of fabricating the same that improve reliability of the semiconductor devices.

Background

Flip chip packaging has become a major packaging technology in the field of power chips, and particularly, as chip current increases, power loss caused by parasitic parameters decreases, and heat dissipation capability increases, which has higher requirements. In the bump process at the front end of the flip-chip process, the use of copper as a rewiring layer can greatly improve chip performance to meet the above-mentioned needs.

At the same time, chip technology is advancing, with the accompanying smaller and smaller silicon grain size, and the power density is doubled, resulting in the pitch of the rewiring layer being compressed. The probability of electric leakage and even short circuit between rewiring layers caused by electrochemical corrosion of the product in a high-temperature and high-humidity environment is continuously amplified, and serious reliability risks exist.

Disclosure of Invention

The present invention is directed to one or more of the problems of the prior art, and provides a semiconductor flip-chip package structure and a method for fabricating the same.

A first aspect of the present invention proposes a flip-chip semiconductor package structure, comprising: a semiconductor substrate including at least one conductive pad formed thereon; a passivation layer covering the semiconductor substrate; a plurality of through holes, each through hole penetrating through the passivation layer until the conductive pad is exposed; a conductive rewiring layer filling the plurality of vias and covering at least a portion of the passivation layer; a corrosion barrier layer entirely covering the top surface and the side surfaces of the conductive rewiring layer and the top surface of a part of the passivation layer adjacent to the root of the side surface of the conductive rewiring layer; and at least one conductive bump fabricated on a selected portion of the top surface of the etch stop layer and coupled to the at least one conductive pad through the plurality of vias.

A second aspect of the present application proposes a method for fabricating a flip-chip semiconductor device, including: manufacturing a passivation layer on a semiconductor substrate; manufacturing a plurality of through holes in the passivation layer; forming a conductive rewiring layer filling the plurality of through holes and covering at least a portion of the passivation layer; forming a corrosion barrier layer on a top surface, a side surface, and a passivation layer top surface adjacent to a side root portion of the conductive rewiring layer; and fabricating at least one conductive bump on a selected portion of the conductive rewiring layer.

The semiconductor flip package structure provided by the invention has high reliability, and meanwhile, the process consistency is good and the yield is high when the semiconductor flip package structure is manufactured.

Drawings

Fig. 1 illustrates a semiconductor flip-chip package structure 100 according to one embodiment of the invention.

Fig. 2 illustrates a semiconductor flip-chip package structure 200 according to one embodiment of the invention.

Fig. 3 illustrates a semiconductor flip-chip package structure 300 according to one embodiment of the invention.

Fig. 4 illustrates a semiconductor flip-chip package structure 400 according to yet another embodiment of the invention.

Fig. 4A-4P are flow diagrams illustrating a packaging method for fabricating a flip-chip packaged semiconductor device 100 according to one embodiment of the present disclosure.

As shown in the drawings, like reference numerals refer to like parts throughout the different views. The drawings are provided for the purpose of illustrating embodiments, concepts, etc. and are not drawn to scale.

Icon: 100-a semiconductor flip-chip package structure; 200-a semiconductor flip-chip packaging structure; 300-semiconductor flip-chip packaging structure; 400-semiconductor flip-chip packaging structure; 101-comprising a semiconductor substrate; 102-conductive pads; 103-a passivation layer; 104-through holes; 105-an under bump metallization layer; 106-rewiring layer; 107-a corrosion barrier; 108-an insulating layer; 109-a support layer; 110-an alloy inhibition layer; 111-solder.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. In the description of the present invention, it should be noted that, if the terms "upper", "lower", "inner", "outer", and the like indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, or the azimuth or the positional relationship in which the inventive product is conventionally put in use, it is merely for convenience of describing the present invention and simplifying the description, and it is not indicated or implied that the apparatus or element referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus it should not be construed as limiting the present invention. The terms "first," "second," and the like, if any, are used solely for distinguishing between descriptions and should not be construed as indicating or implying a relative importance.

Furthermore, references to "one embodiment," "an embodiment," "one example," or "an example" throughout this specification mean: a particular feature, structure, or characteristic described in connection with the embodiment or example is included within at least one embodiment of the invention. Thus, the appearances of the phrases "in one embodiment," "in an embodiment," "one example," or "an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combination and/or sub-combination in one or more embodiments or examples.

Fig. 1 provides a semiconductor flip-chip package structure 100 according to one embodiment of the present invention. Fig. 1 is a schematic cross-sectional view of a semiconductor flip-chip package structure 100, wherein the semiconductor flip-chip package structure 100 includes a semiconductor substrate 101, a plurality of conductive pads (top metal) 102, a passivation layer 103, a via 104, an under bump metallization (Under Bump Metallization, UBM) 105, a conductive rewiring layer (Redistribution Layer, RDL) 106, a corrosion barrier layer 107, an insulating layer 108, and conductive bumps.

Included in the semiconductor substrate 101 is an integrated circuit chip that contains active and passive circuit elements that may include transistors, resistors, diodes, capacitors, inductors, current sources, voltage sources, and other suitable circuit elements. The transistors may include, for example, metal Oxide Semiconductor Field Effect Transistors (MOSFETs), bipolar Junction Transistors (BJTs), junction Field Effect Transistors (JFETs), insulated Gate Bipolar Transistors (IGBTs), double diffused metal oxide semiconductor transistors (DMOS), and the like. These circuit elements are coupled to each other to form integrated circuit chips having different functions, such as logic circuits, power conversion circuits, memory circuits (e.g., random access memory circuits, static random access memory circuits, etc.), input/output circuits, integrated systems on chip, and other suitable circuits.

The semiconductor substrate 101 may be referred to as a substrate comprising a semiconductor material including, but not limited to, bulk silicon, doped silicon, silicon germanium (SiGe), silicon-on-insulator (SOI), and other suitable semiconductor materials.

Isolation structures may also be fabricated in the semiconductor substrate 101 for isolating different circuit elements or integrated circuits of different functions in the semiconductor substrate 101.

The semiconductor substrate 101 also includes a top metal layer overlying the integrated circuit chip formed in the semiconductor substrate 101. The top metal layer may be patterned to form a plurality of conductive pads 102. The conductive pads 102 are for coupling to different circuit elements and/or different circuit nodes in the integrated circuit chip in the semiconductor substrate 101 so that these different circuit elements and/or different circuit nodes can receive or transmit signals or be coupled to a supply node or ground, etc. The material used to make the top layer metal may include one or a combination of metals such as aluminum, copper, silver, gold, nickel, tungsten, and the like. Each conductive pad 102 may have an exposed surface that may be subjected to a planarization process (e.g., a mechanochemical polishing process), if necessary.

Those skilled in the art will appreciate that hundreds or thousands or even more conductive pads 102 may be fabricated on the semiconductor substrate 101. Conductive pads 102 may be grouped by function. For example, those conductive pads 102 having similar or identical functions may be grouped together. Meanwhile, it is not necessary to divide all the conductive pads 102 having the similar or identical function into only one group, but they may be divided into plural groups, for example, those conductive pads 102 having the similar or identical function that are relatively adjacent in arrangement position may be divided into one group, and others conductive pads 102 having the similar or identical function that are relatively adjacent in arrangement position may be divided into another group. By adopting the technical scheme of the embodiment of the disclosure, the position arrangement of the plurality of conductive pads 102 in the semiconductor package structure 100 can be more flexible, and the communication resistance of the conductive path formed from the conductive pads 102 to the conductive bumps is lower, so that the current processing capability is improved.

The top of the semiconductor substrate 101 is covered with a passivation layer 103 for insulation protection. The passivation layer 103 covers the entire semiconductor substrate 101 and the conductive pad 102 on the upper surface thereof. A plurality of vias 104 may be made in the passivation layer. The plurality of vias corresponds to each conductive pad 102 such that the conductive pad is at least partially exposed so that the conductive pad 102 may be connected out in a later process step. In one embodiment, the via 104 may be fabricated by forming a patterned opening through a laser grooving process.

A UBM layer 105 is fabricated over the corresponding portions of passivation layer 103 for each set of conductive pads 102 and over the sidewalls and bottom of each via 104. UBM layer 105 is a metallization transition layer between conductive pad 102 and a conductive bump, and mainly functions as adhesion and diffusion barrier, and is typically composed of multiple metal films such as an adhesion layer, a diffusion barrier layer, and a wetting layer. The UBM layer 105 may be formed by sputtering, evaporation, electroless plating, electroplating a conductive material, and the like. UBM layer 105 needs to have a sufficiently good adhesion to conductive pad 102 and passivation layer 103 for protecting conductive pad 102 during subsequent processing steps and maintaining a low contact resistance between conductive pad 102 and the conductive bump, while acting as an effective diffusion barrier between conductive pad 102 and the bump, and also as a seed layer for solder bump or metal bump deposition for providing a conductive path for subsequent fabrication of RDL layer 106.

Over UBM layer 105 is RDL layer 106.RDL layer 106 fills vias 104 on conductive pads 102 and covers UBM layer 105 over conductive pads 102. In one embodiment, RDL layer 106 may comprise copper (Cu) and have a thickness. The thickness can be selected according to practical application requirements. RDL layer 106 is used to change the original contact locations (conductive pads 102) of the chip through a wafer level metal routing process, enabling the chip to be adapted for different package styles.

In a semiconductor device, as the spacing between different RDL layers 106 continues to decrease, there is a high likelihood that adjacent RDL layers 106 corresponding to different sets of conductive pads 102 will short during thermal reflow causing an electrical short. Such shorting is typically caused by migration of RDL layers 106 or conductive bumps during thermal reflow, or by migration caused by differences in the strength of the electric field that the semiconductor device is subjected to between adjacent RDL layers 106 during operation. Furthermore, when the semiconductor device is operated in some extreme operating environment, such as, in particular, in an environment of high temperature or high humidity, the molding material used to encapsulate and mold the semiconductor device is likely to peel or delaminate from the surface of the passivation layer 103 to scale, which may lead to failure or damage of the semiconductor device. Thus, to further ensure device reliability and long life requirements, in embodiments of the present disclosure, a corrosion barrier layer 107 will be formed on the surface of RDL layer 106. The etch stop layer 107 completely encapsulates the top and sides of the RDL layer 106 and extends outwardly from the side root of the RDL layer 106 to cover the top surface of the partial passivation 103 such that the etch stop layer 107 and the RDL layer 106 form a dense contact. Dense contact means that no gaps at all exist between the etch stop layer 107 and the RDL layer 106. Because the corrosion barrier layer 107 extends from the root of the side surface of the RDL layer 106 to the top surface of the part of the passivation layer 103, the RDL layer 106 cannot diffuse out through any gaps to form whiskers even at the root of the side surface, thereby avoiding the corroded channel of the RDL layer 106, meeting the requirements of high reliability and long service life, and especially realizing zero risk of devices in high-humidity environment.

In one embodiment, a corrosion barrier layer 107 may be formed by sputtering an inert metal on the top and sides of RDL layer 106 and portions of passivation layer 103 adjacent to the root of the sides of RDL layer 106 to form a dense protection for RDL layer 106. The corrosion barrier layer 107 is formed by a sputtering process, no additional process equipment is required, only a conventional sputtering step in a bump manufacturing process is required, and no special process control and risk are caused. In addition, the thickness of the corrosion barrier layer 107 is easy to control by adopting a sputtering process, and a thinner corrosion barrier layer 107 can be formed, so that the influence on the size and the spacing of the RDL layer 106 is very small, and the process consistency is good and the yield is high. For example, in one embodiment, the thickness of the corrosion barrier layer 107 is 0.1 micrometers (μm) to 0.5 μm. And other processes, such as chemical plating, are adopted, so that the thickness uniformity of the plating layer of the positive wafer is ensured, and the thickness of the plating layer is generally more than 1-2 mu m.

In one embodiment, the corrosion barrier layer 107 may be made of an electrochemical corrosion resistant metal, such as titanium (Ti), cr chromium, nickel (Ni), or gold (Au).

After the formation of the etch stop layer 107, a conductive bump will be fabricated on the etch stop layer 107. In one embodiment, one or more conductive bumps will be fabricated on selected portions of the etch stop layer 107 corresponding to over each set of conductive pads 102 such that each conductive bump is coupled to the set of conductive pads 102 through the etch stop layer 107, RDL layer 106, and via 104. As in the semiconductor package 100 of the embodiment shown in fig. 1, a conductive bump is formed on a conductive pad 102; in the semiconductor package 200 of the embodiment shown in fig. 2, two conductive bumps are to be formed on one conductive pad 102.

In the embodiment shown in fig. 1, the conductive bump includes a support layer 109, an alloy-suppression layer 110, and solder 111. The longitudinal height of the conductive bump may be the sum of the thickness of the support layer 109, the thickness of the alloy-inhibit layer 110, and the thickness of the solder 111. In one embodiment, the conductive bumps have a longitudinal height of between 25 μm and 115 μm. Those skilled in the art will appreciate that the thickness and height values given herein are exemplary only and are not intended to be limiting of the present disclosure.

In one embodiment, the conductive bumps may also include solder balls.

In other embodiments, a wire bond structure may be used in place of the conductive bumps in the semiconductor flip-chip package 100. In embodiments of the wire bond structure, if the etch stop layer 107 and the solder balls being wire bonded are not of a material selected, a solder layer may be formed on selected portions of the etch stop layer 107 to enhance the solder properties of the solder balls during wire bonding. If the etch stop layer 107 and the solder balls made by wire bonding are selected to be bonded, the solder layer may be omitted and the solder balls may be directly made by wire bonding to the etch stop layer 107.

According to one exemplary embodiment of the present disclosure, after the conductive bumps corresponding to all of the grouped conductive pads 102 are completely fabricated, a thermal reflow process may be employed such that each conductive bump is at least partially melted and then reflowed to enable physical and electrical connection between the semiconductor package structure 100 and the package lead frame, package substrate, or circuit motherboard to be established through the conductive bumps.

The conductive pads 102 on the semiconductor substrate 101 are coupled to corresponding contact areas or pins on the package lead frame, package base or circuit motherboard, respectively, by conductive bumps, such that the completed semiconductor substrate 101 is mounted or bonded to the package lead frame, package base or circuit motherboard, etc. by a bump flip-chip packaging process.

In one embodiment, the semiconductor package structure 100 may further include an insulating layer 108 formed on the etch stop layer 107, the insulating layer 108 wrapping the etch stop layer 107 formed on the side of the RDL layer 106 and formed on the top edge portion of the RDL layer 106. The insulating layer separates the corresponding etch stop layer 107 under each bump from other adjacent etch stop layers 107. The insulating layer 108 helps to isolate adjacent corrosion barrier layers 107, thereby further improving the operational reliability of the semiconductor package 100. The insulating layer 108 comprises spin-on glass (SOG), a flowable oxide, an organic material, or other suitable material having a low dopant diffusivity.

Fig. 3 provides a semiconductor flip-chip package structure 300 according to yet another embodiment of the present invention. The embodiment shown in fig. 3 illustrates a wiring schematic where RDL layers 106 having different electrical potentials are routed through the middle of two bumps. Similarly, for the intermediate lines, the etch stop layer 107 is also used to complete the capping of the RDL layer 106 of the intermediate lines to form a dense contact. The insulating layer 108 covers the etch stop layer 107.

Fig. 4 provides a semiconductor flip-chip package structure 400 according to yet another embodiment of the present invention. In the semiconductor flip-chip package structure 400, a wire bond structure is used in place of the conductive bumps in the semiconductor flip-chip package structure 100.

Fig. 4A through 4P illustrate a flow diagram of a middle-stage packaging method for flip-chip packaged semiconductor devices (e.g., the semiconductor package structure 100 referred to in the above embodiments) according to one embodiment of the present disclosure. It should be understood by those skilled in the art that the cross-sectional views of fig. 4A through 4P only illustrate a portion of the flow stages of the semiconductor package 100.

Referring to the illustration of fig. 4A, a via 104 is fabricated in a passivation layer 103 in a prepared semiconductor substrate 101. The vias 104 extend longitudinally from the upper surface of the passivation layer 103 to the conductive pads 102, each via 104 passing through an underlying portion of the passivation layer 103 until at least a portion of the underlying conductive pad 102 is exposed. The plurality of vias 104 may expose portions of the conductive pad 102.

Referring next to fig. 4B, UBM layer 105 is fabricated on the upper surface of passivation layer 103 and the sidewalls and bottom of each via 104. UBM layer 105 is typically copper, titanium, or a copper-titanium alloy, such as titanium Tungsten (TiW), titanium copper (TiCu), nickel titanium (TiNi), or the like, having a thickness of 0.3 micrometers (μm) to 0.5 μm.

With continued reference to fig. 4C, a first photoresist layer PR1 is coated on the upper surface of the prepared UBM layer 105.

With continued reference to fig. 4D, the first photoresist layer PR1 is exposed and development patterned to expose the UBM layer 105 under the conductive bumps.

With continued reference to fig. 4E, an RDL layer 106 is fabricated on the exposed UBM metal layer 105, the RDL layer 106 filling each via 104 and up to a certain thickness on the UBM layer 105. In one embodiment, the thickness may be 1 μm to 20 μm. For example, in one embodiment, the thickness of RDL layer 106 may be 5 μm to 20 μm. In another embodiment, the thickness may be 1 μm to 30 μm.

With continued reference to fig. 4F, the first photoresist layer PR1 is stripped to remove the UBM layer 105 exposed on the passivation layer 103.

With continued reference to fig. 4G, UBM layer 105 is etched away, exposing passivation layer 103.

Referring next to fig. 4H, an etch stop layer 107 is formed over the semiconductor structure prepared in fig. 4G, the etch stop layer 107 completely covering the top surface of the semiconductor structure formed in fig. 4G, i.e.: completely encapsulating the top and side surfaces of RDL layer 106 and the surface of passivation layer 103. In this step, the etch stop layer 107 may be formed using a sputtering process. In this step, the corrosion barrier layer 107 is made of a material resistant to electrochemical corrosion, such as titanium (Ti), chromium (Cr), nickel (Ni), or gold (Au). In one embodiment, the thickness of the corrosion barrier layer 107 is 0.1 μm to 0.5 μm, for example 0.4 μm.

Referring then to fig. 4I, an insulating layer 108 is coated on the corrosion barrier layer 107.

Referring then to fig. 4J, the insulating layer 108 is exposed and developed. Such that insulating layer 108 encapsulates etch stop layer 107 formed on the sides of RDL layer 106 and on the top edge portions of RDL layer 106. In one embodiment, the thickness of the insulating layer 108 coating is the length of the corrosion barrier layer 107 extending outward from the root of the sides of the RDL layer 106.

Referring to fig. 4K, a second photoresist layer PR2 is then coated on the upper surface of the semiconductor device formed in fig. 4J.

Referring next to fig. 4L, the second photoresist layer PR2 is exposed and development patterned to expose the under-bump etch stop layer 107 and a portion of the insulating layer 108.

Referring then to fig. 4M, conductive bumps are electroplated on the exposed etch stop layer 107. In the step shown in fig. 4M, the supporting layer 109, the alloy-inhibiting layer 110, and the solder 111 will be plated, respectively. In one embodiment, the support layer 109 may include copper pillars, the alloy-suppression layer 110 includes a nickel layer, and the solder 111 includes a tin (Sn) layer or a tin silver (SnAg) layer. In one embodiment, the thickness of the support layer 109 may be 15 μm to 65 μm. In another embodiment, the thickness of the support layer 109 may be 40 μm to 65 μm. In one embodiment, the solder 111 may be 10 μm to 50 μm thick. In another embodiment, the solder 111 may be 25 μm to 50 μm thick.

Referring to fig. 4N, the second photoresist layer PR2 is then removed by stripping.

Referring then to fig. 4O, the exposed etch stop layer 107 on the passivation layer 103 is etched away.

Finally, referring to fig. 4P, the solder 111 is reflowed to form a hemispherical shape.

The present disclosure provides semiconductor devices including conductive bumps formed on a rewiring layer and related methods of fabricating semiconductor devices, although some embodiments of the invention are described in detail, it should be understood that these embodiments are for illustration only and are not intended to limit the scope of the invention. Other possible alternative embodiments will be apparent to those of ordinary skill in the art from reading this disclosure.

Claims

1. A semiconductor flip-chip package structure, the package structure comprising:

a semiconductor substrate including at least one conductive pad formed thereon;

a passivation layer covering the semiconductor substrate;

a plurality of vias, each via passing through the passivation layer until a portion of the conductive pad is exposed;

a conductive rewiring layer filling the plurality of through holes and covering a portion of the passivation layer;

a corrosion barrier layer entirely covering the top surface and the side surfaces of the conductive rewiring layer and the top surface of a part of the passivation layer adjacent to the root of the side surface of the conductive rewiring layer; and

and at least one conductive bump fabricated on a selected portion of the top surface of the corrosion barrier layer, wherein the at least one conductive bump is coupled to the at least one conductive pad through the plurality of vias.

2. The package structure of claim 1, wherein the corrosion barrier layer has a thickness of 0.1 microns to 0.5 microns.

3. The package structure of claim 1, wherein the corrosion barrier layer comprises an electrochemical corrosion resistant metal.

4. The package structure of claim 1, wherein the package structure further comprises:

and the under bump metal layer is covered on the passivation layer right below the conductive rewiring layer and the side walls and the bottoms of the through holes.

5. The package structure of claim 1, wherein the package structure further comprises:

and the insulating layer is formed on the corrosion barrier layer and wraps the corrosion barrier layer formed on the side surface of the conductive rewiring layer and the edge part of the top surface of the conductive rewiring layer.

6. The package structure of claim 1, wherein the at least one conductive bump comprises:

a support layer formed on selected portions of the conductive rewiring layer;

the alloy inhibition layer is manufactured on the supporting layer; and

and solder material is manufactured on the alloy inhibiting layer.

7. A method of fabricating a flip-chip semiconductor device, the method comprising:

manufacturing a passivation layer on a semiconductor substrate;

manufacturing a plurality of through holes in the passivation layer;

forming a conductive rewiring layer, wherein the conductive rewiring layer fills the plurality of through holes and covers part of the passivation layer;

forming a corrosion barrier layer on a top surface, a side surface, and a passivation layer top surface adjacent to a side root portion of the conductive rewiring layer; and

at least one conductive bump is formed on selected portions of the top surface of the etch stop layer.

8. The method of manufacturing of claim 7, wherein forming a corrosion barrier layer on the top surface, the side surfaces of the conductive rewiring layer, and the top surface of the passivation layer adjacent the root of the side surfaces of the conductive rewiring layer comprises:

forming a corrosion barrier layer on the top surface, the side surfaces and the top surface of the passivation layer of the conductive rewiring layer;

coating an insulating layer on the corrosion barrier layer;

exposing and developing the insulating layer to enable the insulating layer to wrap the corrosion barrier layer formed on the side surface and the root of the side surface of the conductive rewiring layer, and wrap the top surface part of the corrosion barrier layer outside the selected part of the top surface of the corrosion barrier layer; and

etching away the etch stop layer exposed on the passivation layer.

9. The method of manufacturing of claim 8, wherein forming a corrosion barrier layer on the top surface, the side surfaces, and the top surface of the passivation layer of the conductive rewiring layer comprises: and forming a corrosion barrier layer on the top surface and the side surfaces of the conductive rewiring layer and the top surface of the passivation layer through a sputtering mode.

10. The method of manufacturing of claim 7, wherein the corrosion barrier layer comprises an electrochemical corrosion resistant metal.