CN112466855A - Antenna chip packaging structure and preparation method thereof - Google Patents

Antenna chip packaging structure and preparation method thereof Download PDF

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Publication number
CN112466855A
CN112466855A CN202011453915.XA CN202011453915A CN112466855A CN 112466855 A CN112466855 A CN 112466855A CN 202011453915 A CN202011453915 A CN 202011453915A CN 112466855 A CN112466855 A CN 112466855A
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China
Prior art keywords
layer
antenna
forming
connection structure
packaging
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CN202011453915.XA
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Chinese (zh)
Inventor
薛亚媛
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SJ Semiconductor Jiangyin Corp
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SJ Semiconductor Jiangyin Corp
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Priority to CN202011453915.XA priority Critical patent/CN112466855A/en
Publication of CN112466855A publication Critical patent/CN112466855A/en
Priority to US17/546,473 priority patent/US20220181278A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/12—Supports; Mounting means
    • H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/36—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
    • H01Q1/38—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith formed by a conductive layer on an insulating support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate

Abstract

The invention provides an antenna chip packaging structure and a preparation method thereof, wherein the preparation method comprises the following steps: providing a first support substrate and forming a rewiring layer; sequentially forming a first antenna layer, a first connection structure and a first packaging layer on the rewiring layer; forming a second antenna layer, a second connection structure and a second packaging layer in sequence above the first packaging layer; forming a third antenna layer over the second encapsulation layer; bonding a second support substrate over the second encapsulation layer and the third antenna layer; removing the first supporting substrate, and forming a lower metal layer of a salient point below the rewiring layer; and forming solder balls on the under bump metal layer and connecting the chip. According to the invention, by introducing a multi-layer antenna layer structure, the size of the packaging structure is reduced; the laser drilling is adopted to ensure that the through hole forming process has high precision and low cost; the lower metal layer of the salient point is introduced to be connected with the welding ball and the chip, so that the welding effect is good, and the reliability is high; the warpage of the package structure is improved by introducing the second support substrate.

Description

Antenna chip packaging structure and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to an antenna chip packaging structure and a preparation method thereof.
Background
The fifth generation mobile communication technology (abbreviated as 5G) is a latest generation cellular mobile communication technology, which employs millimeter or centimeter band communication, and has significant advantages of high data transmission rate, low delay, and capability of supporting large-scale device connection.
Currently, in the packaging process of 5G chip, the antenna structure and other components such as chip are integrated into the same packaging structure by means of the aip (antenna in package) technology. By integrating the antenna in the package structure, the device design can be effectively simplified, thereby realizing the design requirements of miniaturization and low cost.
However, the conventional antenna chip packaging structure has poor electric heating performance and large packaging size, and is difficult to optimize aiming at the characteristics of the 5G chip, which leads to the performance reduction of the 5G antenna chip. In addition, warpage is easily generated in the packaging process, and warpage exceeding the process specification can cause deformation of the packaging structure under the action of stress, thereby affecting the reliability and yield of products.
Therefore, it is necessary to provide a new antenna chip package structure and a method for manufacturing the same to solve the above problems.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an antenna chip package structure and a method for manufacturing the same, which are used to solve the problems of poor electrical heating performance, large package size and easy warpage in the prior art.
In order to achieve the above and other related objects, the present invention provides a method for manufacturing an antenna chip package structure, including the steps of:
1) providing a first support substrate, and forming a rewiring layer on the first support substrate;
2) sequentially forming a first antenna layer connected with the rewiring layer, a first connection structure connected with the first antenna layer and a first packaging layer covering the rewiring layer, the first antenna layer and the first connection structure above the rewiring layer;
3) forming a second antenna layer connected with the first connection structure, a second connection structure connected with the second antenna layer and a second packaging layer covering the first packaging layer, the second antenna layer and the second connection structure in sequence above the first packaging layer;
4) forming a third antenna layer over the second encapsulation layer connecting the second connection structure;
5) bonding a second support substrate over the second encapsulation layer and the third antenna layer;
6) removing the first supporting substrate, and forming an under bump metal layer below the rewiring layer;
7) and forming a solder ball on the under bump metal layer and connecting a chip.
As an alternative of the present invention, in step 1), there is further included a step of coating a release layer on the first support substrate, the rewiring layer being adhered to the first support substrate through the release layer; in step 6), when the first support substrate is removed, the first support substrate is separated from the rewiring layer by peeling off the release layer.
As an alternative of the invention, the redistribution layer comprises at least one metal wiring layer and a dielectric layer encasing the metal wiring layer.
As an alternative of the present invention, before step 6), a step of forming a via hole in the rewiring layer to connect the metal wiring layer is further included.
As an alternative of the invention, the method of forming the through-hole comprises a laser drilling process.
As an alternative of the invention, before step 7), a step of removing the second support substrate is further included.
As an alternative of the present invention, a stacked structure of a plurality of the second antenna layers, the second connection structure, and the second encapsulation layer is formed in step 3); the second packaging layers are sequentially overlapped and cover the corresponding second antenna layers and the second connecting structures; a plurality of the second antenna layers are connected to each other by a plurality of the second connection structures; the second antenna layer at the bottommost layer is connected with the first connecting structure, and the second connecting structure at the topmost layer is connected with the third antenna layer.
As an alternative of the present invention, the step of forming the solder balls on the under bump metallurgy layer includes a ball-mounting and reflow process.
The invention also provides an antenna chip packaging structure, which is characterized by comprising:
rewiring layers;
a first antenna layer connecting the re-wiring layer, a first connection structure connecting the first antenna layer, and a first encapsulation layer covering the re-wiring layer, the first antenna layer, and the first connection structure, which are located above the re-wiring layer;
a second antenna layer connected to the first connection structure, a second connection structure connected to the second antenna layer, and a second encapsulation layer covering the first encapsulation layer, the second antenna layer, and the second connection structure, over the first encapsulation layer;
an under bump metallurgy layer located below the rewiring layer;
and the solder balls are connected with the under bump metal layer and the chip.
As an alternative of the invention, the redistribution layer comprises at least one metal wiring layer and a dielectric layer encasing the metal wiring layer.
As an alternative of the present invention, a via hole connecting the metal wiring layers is formed in the rewiring layer.
As an alternative of the present invention, a stacked structure of a plurality of the second antenna layers, the second connection structure, and the second encapsulation layer is formed above the first encapsulation layer; the second packaging layers are sequentially overlapped and cover the corresponding second antenna layers and the second connecting structures; a plurality of the second antenna layers are connected to each other by a plurality of the second connection structures; the second antenna layer at the bottommost layer is connected with the first connecting structure, and the second connecting structure at the topmost layer is connected with the third antenna layer.
As described above, the present invention provides an antenna chip package structure and a method for manufacturing the same, which reduces the size of the package structure by introducing a multi-layered antenna layer structure; the laser drilling is adopted to ensure that the through hole forming process has high precision and low cost; the lower metal layer of the salient point is introduced to be connected with the welding ball and the chip, so that the welding effect is good, and the reliability is high; the warpage of the package structure is improved by introducing the second support substrate.
Drawings
Fig. 1 is a flowchart illustrating a method for manufacturing an antenna chip package structure according to an embodiment of the invention.
Fig. 2 is a schematic cross-sectional view of a first support substrate and a redistribution layer provided in a first embodiment of the present invention.
Fig. 3 is a schematic cross-sectional view illustrating a first antenna layer formed according to a first embodiment of the invention.
Fig. 4 is a schematic cross-sectional view illustrating a first connection structure according to an embodiment of the invention.
Fig. 5 is a schematic cross-sectional view illustrating a first package layer formed according to a first embodiment of the invention.
Fig. 6 is a schematic cross-sectional view illustrating a first package layer after a polishing process according to an embodiment of the invention.
Fig. 7 is a schematic cross-sectional view illustrating a second antenna layer formed according to an embodiment of the invention.
Fig. 8 is a schematic cross-sectional view illustrating a second connection structure according to an embodiment of the invention.
Fig. 9 is a schematic cross-sectional view illustrating a second package layer formed according to a first embodiment of the invention.
Fig. 10 is a schematic cross-sectional view illustrating a second package layer after a polishing process according to an embodiment of the invention.
Fig. 11 is a schematic cross-sectional view illustrating a third antenna layer formed according to a first embodiment of the invention.
Fig. 12 is a schematic cross-sectional view illustrating a bonded second supporting substrate according to a first embodiment of the invention.
Fig. 13 is a schematic cross-sectional view illustrating a first supporting substrate after being removed according to a first embodiment of the invention.
Fig. 14 is a schematic cross-sectional view illustrating a bump under metal layer formed according to an embodiment of the invention.
Fig. 15 is a schematic cross-sectional view illustrating a process of removing the second supporting substrate according to a first embodiment of the invention.
Fig. 16 is a schematic cross-sectional view illustrating a solder ball formed according to an embodiment of the invention.
Fig. 17 is a schematic cross-sectional view illustrating a chip connected according to an embodiment of the invention.
Fig. 18 is a schematic cross-sectional view illustrating an antenna chip package structure according to a second embodiment of the invention.
Description of the element reference numerals
101 first support substrate
101a release layer
102 rewiring layer
102a metal wiring layer
102b dielectric layer
103 first antenna layer
104 first connecting structure
105 first encapsulation layer
106 second antenna layer
107 second connection structure
108 second encapsulation layer
108a buffer layer
109 third antenna layer
110 second support substrate
110a release layer
111 bump under metal layer
111a via hole
112 solder ball
113 chip
203 first antenna layer
204 first connecting structure
205 first encapsulation layer
206 second antenna layer
207 second connecting structure
208 second encapsulation layer
208a buffer layer
209 third antenna layer
S1-S7 Steps 1) -7)
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 18. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Example one
Referring to fig. 1 to 17, the present invention provides a method for manufacturing an antenna chip package structure, which includes the following steps:
1) providing a first support substrate 101, and forming a rewiring layer 102 on the first support substrate 101;
2) forming a first antenna layer 103 connecting the redistribution layer 102, a first connection structure 104 connecting the first antenna layer 103, and a first encapsulation layer 105 covering the redistribution layer 102, the first antenna layer 103, and the first connection structure 104 in this order above the redistribution layer 102;
3) forming a second antenna layer 106 connecting the first connection structure 104, a second connection structure 107 connecting the second antenna layer 106, and a second encapsulation layer 108 covering the first encapsulation layer 105, the second antenna layer 106, and the second connection structure 107 in this order over the first encapsulation layer 105;
4) forming a third antenna layer 109 connected to the second connection structure 107 over the second encapsulation layer 108;
5) bonding a second support substrate 110 over the second encapsulation layer 108 and the third antenna layer 109;
6) removing the first support substrate 101 and forming an under bump metallurgy layer 111 below the rewiring layer 102;
7) solder balls 112 and connection chips 113 are formed on the under bump metallurgy layer 111.
In step 1), referring to step S1 of fig. 1 and fig. 2, a first supporting substrate 101 is provided, and a rewiring layer 102 is formed on the first supporting substrate 101.
As an example, as shown in fig. 2, a release layer 101a is further coated on the first support substrate 101, and the rewiring layer 102 is adhered to the first support substrate 101 through the release layer 101 a. The release layer 101a includes a LTHC light-to-heat conversion material Layer (LTHC). The rewiring layer 102 and the first support substrate 101 may be separated from each other from the LTHC light-heat conversion material layer by heating the LTHC light-heat conversion material layer based on laser to lose adhesiveness of the LTHC light-heat conversion material layer.
By way of example, the re-routing layer 102 includes at least one metal routing layer 102a and a dielectric layer 102b encasing the metal routing layer 102 a. Optionally, the material forming the metal wiring layer 102a includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium; the material for forming the dielectric layer 102b includes one or a combination of two or more of epoxy resin, silica gel, polyimide, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass. The process for depositing the metal wiring layer 102a comprises a chemical vapor deposition process, an evaporation process, a sputtering process, an electroplating process or a chemical plating process, and after deposition, the patterned metal wiring layer 102a is formed through a photoetching and etching process; the process of forming the dielectric layer 102b includes a chemical vapor deposition process or a physical vapor deposition process. The re-wiring layer 102 of a multilayer structure can be obtained by repeatedly forming the metal wiring layer 102a and the dielectric layer 102 b. In the present embodiment, the metal wiring layer 102a has two layers in total.
In step 2), referring to step S2 of fig. 1 and fig. 3 to 6, a first antenna layer 103 connected to the redistribution layer 102, a first connection structure 104 connected to the first antenna layer 103, and a first encapsulation layer 105 covering the redistribution layer 102, the first antenna layer 103, and the first connection structure 104 are sequentially formed above the redistribution layer 102.
As shown in fig. 3, a first antenna layer 103 connecting metal wiring layers in the rewiring layer 102 is formed above the rewiring layer 102. The material for forming the antenna layer comprises one or the combination of more than two of copper, aluminum, nickel, gold, silver and titanium; the forming method comprises chemical vapor deposition and physical vapor deposition, and a patterned antenna layer is formed through photoetching and etching processes after deposition.
As shown in fig. 4, one end of the metal connection line is soldered on the first antenna layer 103 in the opening region by a wire bonding process, and the other end extends upward to form the first connection structure 104. Optionally, the bonding process includes one of a thermocompression bonding process, an ultrasonic bonding process, and a thermocompression ultrasonic bonding process; the material of the metal connecting wire comprises one of gold, silver, copper or aluminum; after one end of the metal connecting wire is soldered to the first antenna layer 103, the metal connecting wire is extended upward and cut at the other end, and the cut ends of the plurality of metal connecting wires are maintained at the same level.
As shown in fig. 5, a first encapsulation layer 105 is formed covering the rewiring layer 102, the first antenna layer 103, and the first connection structure 104. The material for forming the first encapsulation layer 105 includes one of polyimide, silicone, and epoxy resin; the forming method includes one of compression molding, transfer molding, liquid seal molding, vacuum lamination and spin coating.
As shown in fig. 6, the top excess of the first encapsulation layer 105 and the first connection structure 104 are removed by a grinding process, and the top of the first connection structure 104 is exposed.
In step 3), referring to step S3 of fig. 1 and fig. 7 to 10, a second antenna layer 106 connected to the first connection structure 104, a second connection structure 107 connected to the second antenna layer 106, and a second encapsulation layer 108 covering the first encapsulation layer 105, the second antenna layer 106, and the second connection structure 107 are sequentially formed over the first encapsulation layer 105.
As shown in fig. 7, a second antenna layer 106 connected to the first connection structure 104 is formed over the first encapsulation layer 105, and its constituent material and formation method may refer to the first antenna layer 103.
As shown in fig. 8, a second connection structure 107 connecting the second antenna layer 106 is formed on the second antenna layer 106, and the first connection structure 104 can be referred to for its constituent material and formation method.
As shown in fig. 9 to 10, a second encapsulation layer 108 is formed covering the first encapsulation layer 105, the second antenna layer 106, and the second connection structure 107, and its constituent material and forming method may refer to the first encapsulation layer 105. Optionally, a buffer layer 108a is further formed between the second encapsulation layer 108 and the first encapsulation layer 105, and the buffer layer 108a can relieve interlayer stress and protect the antenna layer structure from being deformed and damaged by the stress.
In step 4), referring to step S4 of fig. 1 and fig. 11, a third antenna layer 109 connected to the second connection structure 107 is formed above the second encapsulation layer 108.
As shown in fig. 11, a third antenna layer 109 connected to the second connection structure 107 is formed over the second encapsulation layer 108, and its constituent material and formation method can refer to the first antenna layer 103.
In step 5), referring to step S5 of fig. 1 and fig. 12, a second supporting substrate 110 is bonded over the second encapsulation layer 108 and the third antenna layer 109.
As an example, as shown in fig. 12, the second supporting substrate 110 also includes a release layer 110a, which also includes a LTHC light-to-heat conversion material Layer (LTHC) having the same function as the release layer 101 a. According to the invention, the second supporting substrate 110 is introduced as a temporary bonding substrate, so that an additional fixing supporting function is provided in the subsequent process, abnormal warping of the packaging structure in the subsequent process is prevented, and the performance of the packaging structure is not influenced by the abnormal warping.
In step 6), referring to step S6 of fig. 1 and fig. 12 to 15, the first support substrate 101 is removed, and an under bump metallurgy layer 111 is formed below the rewiring layer 102.
As shown in fig. 12 to 13, the release layer 101a is peeled off by laser irradiation, thereby removing the first support substrate 101.
As shown in fig. 13, after removing the first supporting substrate 101, a step of forming a via hole 111a connecting the metal wiring layer 102a in the rewiring layer 102 is further included. Optionally, the method of forming the through hole 111a includes a laser drilling process. The through hole structure formed by the laser drilling process has the remarkable advantages of high precision and low cost. The via hole 111a exposes the metal wiring layer 102a after formation.
As shown in fig. 14, an Under Bump Metallurgy (UBM) layer 111 is formed in a region where the via hole 111a is formed below the rewiring layer 102. The under bump metal layer 111 can be formed by multiple metal material layers, can provide good electrical connection for a solder ball and a chip, and has a good welding effect in a reflow soldering process, so that the reliability of a chip packaging product is improved.
As shown in fig. 15, after the under bump metallurgy layer 111 is formed, a step of removing the second supporting substrate 110 is further included. The removal process of the second support substrate 110 may refer to the first support substrate 101.
In step 7), referring to step S7 of fig. 1 and fig. 16 to 17, solder balls 112 and a connection chip 113 are formed on the under bump metallurgy layer 111.
As shown in fig. 16, solder balls 112 are formed on the under bump metallurgy layer 111. Optionally, the step of forming the solder balls 112 on the under bump metallurgy layer 111 includes ball mounting and reflow processes.
As shown in fig. 17, the chip 113 is connected to the under bump metallurgy layer 111. Optionally, the chip 113 is a 5G chip.
In the embodiment, the first support substrate and the second support substrate are introduced to ensure that the packaging structure is supported and fixed by the support substrate in the packaging process, so that abnormal warping is prevented. The size of the packaging structure is reduced by introducing a multi-layer antenna layer structure; the laser drilling is adopted to ensure that the through hole forming process has high precision and low cost; by introducing the under bump metal layer to connect with the solder ball and the chip, the welding effect is good and the reliability is high.
Example two
As shown in fig. 18, this embodiment provides a method for manufacturing an antenna chip package structure, which is different from the first embodiment in that a stacked structure of a plurality of second antenna layers, a second connection structure, and a second package layer is formed in step 3); the second packaging layers are sequentially overlapped and cover the corresponding second antenna layers and the second connecting structures; a plurality of the second antenna layers are connected to each other by a plurality of the second connection structures; the second antenna layer at the bottommost layer is connected with the first connecting structure, and the second connecting structure at the topmost layer is connected with the third antenna layer.
As an example, in fig. 18, a two-layer stacked structure of the second antenna layer 206, the second connection structure 207, and the second encapsulation layer 208 is formed between the first encapsulation layer 205 and the third antenna layer 209. A buffer layer 208a is also formed between adjacent encapsulation layers. The second antenna layer 206 at the bottom layer is connected with the first connection structure 204, and the first connection structure 204 is connected with the first antenna layer 203; the second connection structure 207 of the topmost layer connects to the third antenna layer 209. In the present embodiment, a case of a two-layer stacked structure is shown, but in other embodiments of the present invention, the stacked structure may be a three-layer or more structure.
Other embodiments of this embodiment are the same as the first embodiment, and are not described herein again.
EXAMPLE III
As shown in fig. 17, the present embodiment provides an antenna chip packaging structure, including:
a rewiring layer 102;
a first antenna layer 103 connecting the redistribution layer 102, a first connection structure 104 connecting the first antenna layer 103, and a first encapsulation layer 105 covering the redistribution layer 102, the first antenna layer 103, and the first connection structure 104, which are located above the redistribution layer 102;
a second antenna layer 106 connected to the first connection structure 104, a second connection structure 107 connected to the second antenna layer 106, and a second encapsulation layer 108 covering the first encapsulation layer 105, the second antenna layer 106, and the second connection structure 107, which are located above the first encapsulation layer 105;
an under bump metallurgy layer 111 located below the rewiring layer 102;
and connecting the solder balls 112 of the under bump metallurgy layer 111 and the chip 113.
As an example, as shown in fig. 17, the redistribution layer 102 includes at least one metal wiring layer 102a and a dielectric layer 102b wrapping the metal wiring layer 102 a. As shown in fig. 13, a via hole 111a connecting the metal wiring layer 102a is also formed in the redistribution layer 102.
As an example, as shown in fig. 18, a stacked structure of a plurality of the second antenna layers 206, the second connection structure 207, and the second encapsulation layer 208 is formed above the first encapsulation layer 205; a plurality of the second packaging layers 208 are sequentially stacked and cover the corresponding second antenna layers 206 and the second connection structures 207; a plurality of the second antenna layers 206 are connected to each other by a plurality of the second connection structures 207; the second antenna layer 206 at the bottom layer is connected to the first connection structure 204, and the second connection structure 207 at the top layer is connected to the third antenna layer 209.
In summary, the present invention provides an antenna chip package structure and a method for manufacturing the same, wherein the method for manufacturing the antenna chip package structure includes the following steps: 1) providing a first support substrate, and forming a rewiring layer on the first support substrate; 2) sequentially forming a first antenna layer connected with the rewiring layer, a first connection structure connected with the first antenna layer and a first packaging layer covering the rewiring layer, the first antenna layer and the first connection structure above the rewiring layer; 3) forming a second antenna layer connected with the first connection structure, a second connection structure connected with the second antenna layer and a second packaging layer covering the first packaging layer, the second antenna layer and the second connection structure in sequence above the first packaging layer; 4) forming a third antenna layer over the second encapsulation layer connecting the second connection structure; 5) bonding a second support substrate over the second encapsulation layer and the third antenna layer; 6) removing the first supporting substrate, and forming an under bump metal layer below the rewiring layer; 7) and forming a solder ball on the under bump metal layer and connecting a chip. According to the invention, by introducing a multi-layer antenna layer structure, the size of the packaging structure is reduced; the laser drilling is adopted to ensure that the through hole forming process has high precision and low cost; the lower metal layer of the salient point is introduced to be connected with the welding ball and the chip, so that the welding effect is good, and the reliability is high; the warpage of the package structure is improved by introducing the second support substrate.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (12)

1. A preparation method of an antenna chip packaging structure is characterized by comprising the following steps:
1) providing a first support substrate, and forming a rewiring layer on the first support substrate;
2) sequentially forming a first antenna layer connected with the rewiring layer, a first connection structure connected with the first antenna layer and a first packaging layer covering the rewiring layer, the first antenna layer and the first connection structure above the rewiring layer;
3) forming a second antenna layer connected with the first connection structure, a second connection structure connected with the second antenna layer and a second packaging layer covering the first packaging layer, the second antenna layer and the second connection structure in sequence above the first packaging layer;
4) forming a third antenna layer over the second encapsulation layer connecting the second connection structure;
5) bonding a second support substrate over the second encapsulation layer and the third antenna layer;
6) removing the first supporting substrate, and forming an under bump metal layer below the rewiring layer;
7) and forming a solder ball on the under bump metal layer and connecting a chip.
2. The method for manufacturing an antenna chip package structure according to claim 1, wherein: in step 1), a step of coating a release layer on the first support substrate, the rewiring layer being adhered to the first support substrate through the release layer; in step 6), when the first support substrate is removed, the first support substrate is separated from the rewiring layer by peeling off the release layer.
3. The method for manufacturing an antenna chip package structure according to claim 1, wherein: the rewiring layer comprises at least one metal wiring layer and a dielectric layer wrapping the metal wiring layer.
4. The method for manufacturing an antenna chip package structure according to claim 3, wherein: before step 6), a step of forming a via hole in the rewiring layer to connect the metal wiring layer is further included.
5. The method for manufacturing the antenna chip packaging structure according to claim 4, wherein: the method of forming the via hole includes a laser drilling process.
6. The method for manufacturing an antenna chip package structure according to claim 1, wherein: before step 7), a step of removing the second support substrate is also included.
7. The method for manufacturing an antenna chip package structure according to claim 1, wherein: a stacked structure of the second antenna layers, the second connection structure, and the second package layer is formed in step 3); the second packaging layers are sequentially overlapped and cover the corresponding second antenna layers and the second connecting structures; a plurality of the second antenna layers are connected to each other by a plurality of the second connection structures; the second antenna layer at the bottommost layer is connected with the first connecting structure, and the second connecting structure at the topmost layer is connected with the third antenna layer.
8. The method for manufacturing an antenna chip package structure according to claim 1, wherein: the step of forming the solder balls on the under bump metal layer comprises ball planting and reflow soldering processes.
9. An antenna chip package structure, comprising:
rewiring layers;
a first antenna layer connecting the re-wiring layer, a first connection structure connecting the first antenna layer, and a first encapsulation layer covering the re-wiring layer, the first antenna layer, and the first connection structure, which are located above the re-wiring layer;
a second antenna layer connected to the first connection structure, a second connection structure connected to the second antenna layer, and a second encapsulation layer covering the first encapsulation layer, the second antenna layer, and the second connection structure, over the first encapsulation layer;
an under bump metallurgy layer located below the rewiring layer;
and the solder balls are connected with the under bump metal layer and the chip.
10. The antenna chip package structure of claim 9, wherein: the rewiring layer comprises at least one metal wiring layer and a dielectric layer wrapping the metal wiring layer.
11. The antenna chip package structure of claim 10, wherein: and a through hole connected with the metal wiring layer is formed in the rewiring layer.
12. The antenna chip package structure of claim 9, wherein: a laminated structure formed by a plurality of second antenna layers, the second connection structure and the second packaging layer is formed above the first packaging layer; the second packaging layers are sequentially overlapped and cover the corresponding second antenna layers and the second connecting structures; a plurality of the second antenna layers are connected to each other by a plurality of the second connection structures; the second antenna layer at the bottommost layer is connected with the first connecting structure, and the second connecting structure at the topmost layer is connected with the third antenna layer.
CN202011453915.XA 2020-12-09 2020-12-09 Antenna chip packaging structure and preparation method thereof Pending CN112466855A (en)

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CN202011453915.XA CN112466855A (en) 2020-12-09 2020-12-09 Antenna chip packaging structure and preparation method thereof
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