CN116130413A - 基于改进硅通孔技术的多层芯片三维堆叠封装方法 - Google Patents
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Abstract
本发明公开了基于改进硅通孔技术的多层芯片三维堆叠封装方法。该方法是由如下步骤实现的:步骤一,采用深反应离子刻蚀技术进行通孔的加工,形成通孔;步骤二,采用等离子体增强化学气相沉积技术隔断填充金属与Si之间的电导通,沉积绝缘层;步骤三,在Cu和半导体本体之间沉积一层阻挡层,在阻挡层表面覆盖一层Cu种子层用以导电,沉积阻挡层和种子层;步骤四,采用电镀Cu工艺来填充硅通孔;步骤五,采用化学机械抛光技术将多余的Cu去除,平坦化晶圆表面;步骤六,将晶圆的磨削、抛光、保护膜去除和划片膜粘贴等工序集合在一台设备内,减薄晶圆。
Description
技术领域
本发明涉及芯片堆叠封装领域,尤其涉及基于改进硅通孔技术的多层芯片三维堆叠封装方法。
背景技术
进入二十一世纪后,集成电路按照尺寸微缩的技术路线遭遇了物理节点失效、经济学定律失效,以及性能、功耗、面积指标难以达到等各种困难,单纯依靠尺寸微缩的发展道路变得越来越窄,因此工业上开始逐渐意识到实现三维集成产业化的重要性。理想的技术方案是在Si片上生长多层不同功能的器件,但该方法技术难度较高,当前还处于基础研究和实验室开发阶段。目前已报道的三维芯片大多是芯片在垂直方向上的堆叠,该技术利用硅通孔将芯片打通,实现芯片之间和芯片内部的垂直互连。三维芯片具有以下优势:性能方面,多颗芯片垂直互连,从而提高互连速度、减少响应时间;功耗方面,缩短全局连线,减少长连线上中继器的数量,实现能耗降低;面积方面,多层堆叠的芯片集成度提升巨大,单位面积上的晶体管数量成倍地增长。另外,堆叠的芯片可以是异质异构的,可以使用不同的工艺,因此多层堆叠能够实现复杂的系统功能,能够很好地符合未来“新基建”对集成电路的要求。
发明内容
硅通孔是一种穿通Si晶圆或芯片的垂直互连结构,可以完成连通上下层晶圆或芯片的功能,是晶圆级多层堆叠技术中有效提高系统整合度与效能的关键工艺。硅通孔工艺依据制程的先后可以分为先通孔、中通孔和后通孔三种技术方案。先通孔是指在没有进行任何CMOS工艺前,先在空白Si片上制作通孔。中通孔是指在CMOS器件即将完成和晶圆减薄工艺前进行硅通孔的制作,一般是在器件结构基本完成而全局互连尚未实现的阶段进行。后通孔是指在晶圆减薄后再进行硅通孔的制作。
由于Cu作为填充材料可以使通孔的性能得到较大提升,因此目前的主流方案是中通孔与后通孔方案。在这两种方案中,通常有以下几个步骤:通孔的形成、绝缘层的沉积、阻挡层和种子层的沉积、硅通孔的填充、晶圆表面的平坦化和晶圆的减薄。
形成通孔:
晶圆上的硅通孔形成是硅通孔技术的核心,目前的通孔加工技术主要分为两种:一种是激光钻孔;另一种是深反应离子刻蚀。由于Cu的热膨胀系数远大于Si,因此通孔中填充过多的Cu容易导致可靠性问题。为了提高通孔可靠性,通孔的直径越小越好,所以生成小孔径高深宽比硅通孔的深反应离子刻蚀成为本发明硅通孔制作技术的选择。
沉积绝缘层:
在填充金属之前,必须先进行绝缘层的沉积,隔断填充金属与Si之间的电导通。通孔内壁绝缘层材料包括硅氧化物、硅氮化物和聚合物等。等离子体增强化学气相沉积技术的沉积速率高、工艺温度低、均匀性好且台阶覆盖率高,广泛应用于沉积SiO2等绝缘层材料。
沉积阻挡层和种子层:
由于Cu具有优秀的电性能和热性能,且成本低廉,目前硅通孔大多采用Cu来填充。Cu和半导体本体之间需要沉积一层阻挡层,既能阻挡Cu向SiO2中扩散,也能提高Cu在SiO2表面的黏附强度。通常的阻挡层材料包括Ta、TaN/Ta、TiN等金属或金属化合物。在阻挡层表面覆盖一层Cu种子层用以导电,通电后,电镀液中的Cu离子与电子结合形成镀在种子层表面的Cu。
填充硅通孔:
硅通孔的Cu填充技术主要有电镀、磁控溅射、化学气相沉积、原子层沉积等方法。由于电镀的成本更低且沉积速率更快,本发明采用电镀Cu工艺来填充硅通孔。
平坦化晶圆表面:
完成电镀Cu后,晶圆的表面沉积了一层较厚的不均匀Cu层,本发明采用化学机械抛光技术将多余的Cu去除并将晶圆表面平坦化。Cu的研磨工艺分为三步:第一步用较快的研磨速率去除晶圆表面大部分的Cu;第二步通过降低研磨速率研磨掉与阻挡层接触的Cu,使研磨停留在阻挡层上;第三步研磨掉阻挡层和少量的氧化硅。
减薄晶圆:
在先通孔和中通孔工艺中,晶圆表面平坦化后,还需要进行晶圆背面的减薄使硅通孔露出,而在后通孔工艺中,晶圆在进行Bosch刻蚀工艺前就会进行减薄。晶圆减薄使硅通孔露出,在晶圆级多层堆叠技术中,将多片晶圆进行堆叠键合,同时总厚度还必须满足封装设备的要求。本发明采用一体机的思路,将晶圆的磨削、抛光、保护膜去除和划片膜粘贴等工序集合在一台设备内,以解决晶圆经过减薄后通常容易产生变形或翘曲。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1是本发明中步骤一到步骤六的流程示意图。
具体实施方式
下面结合具体实施例对本发明作详细的说明。
基于改进硅通孔技术的多层芯片三维堆叠封装方法,该方法采用下述步骤实现:
步骤一,采用深反应离子刻蚀技术进行通孔的加工,形成通孔。步骤二,采用等离子体增强化学气相沉积技术隔断填充金属与Si之间的电导通,沉积绝缘层。步骤三,在Cu和半导体本体之间沉积一层阻挡层,在阻挡层表面覆盖一层Cu种子层用以导电,沉积阻挡层和种子层。步骤四,采用电镀Cu工艺来填充硅通孔。步骤五,采用化学机械抛光技术将多余的Cu去除,平坦化晶圆表面。步骤六,将晶圆的磨削、抛光、保护膜去除和划片膜粘贴等工序集合在一台设备内,减薄晶圆。
所述步骤一中,具体步骤包括:
采用深反应离子刻蚀技术将聚合物钝化层的沉积和对单晶硅的刻蚀这两种工艺过程组合到一起循环交替进行,进而形成侧壁陡直的高深宽比扇贝结构;深反应离子刻蚀技术的具体过程为:首先使用SF6刻蚀Si表面,然后在侧壁上沉积一层(CF2)n高分子钝化膜,再通入SF6刻蚀掉钝化膜,接着进行Si基材的刻蚀,如此反复,从而形成一个局部的各向异性刻蚀。
所述步骤二中,具体步骤包括:
采用等离子体增强化学气相沉积技术进行绝缘层的沉积,隔断填充金属与Si之间的电导通;通孔内壁绝缘层材料包括硅氧化物、硅氮化物和聚合物等。
所述步骤三中,具体步骤包括:
在Cu和半导体本体之间沉积一层阻挡层,阻挡Cu向SiO2中扩散,提高Cu在SiO2表面的黏附强度;采用电镀的方式来生长Cu,在阻挡层表面覆盖一层Cu种子层用以导电,电镀液中的Cu离子与电子结合形成镀在种子层表面的Cu。
所述步骤四中,具体步骤包括:
选用Cu作为硅通孔的填充材料,采用电镀Cu工艺来填充硅通孔;利用特殊的电镀促进剂和抑制剂来加速通孔内部的沉积速率和抑制通孔外表面的沉积速率,调整促进剂和抑制剂的比例而防止产生电镀空洞。
所述步骤五中,具体步骤包括:
采用化学机械抛光技术将多余的Cu去除并将晶圆表面平坦化;Cu的研磨工艺分三步进行:首先用较快的研磨速率去除晶圆表面大部分的Cu;其次通过降低研磨速率研磨掉与阻挡层接触的Cu,使研磨停留在阻挡层上;最后研磨掉阻挡层和少量的氧化硅。
所述步骤六中,具体步骤包括:
进行晶圆背面的减薄使硅通孔露出,在晶圆级多层堆叠技术中将多片晶圆进行堆叠键合;采用复合方法进行晶圆的减薄,首先利用机械磨削将晶圆减薄到一定程度后,然后利用化学机械抛光技术和湿法腐蚀等减薄工艺进一步减薄至目标厚度。
Claims (7)
1.基于改进硅通孔技术的多层芯片三维堆叠封装方法,其特征在于,包括步骤:
步骤一,采用深反应离子刻蚀技术进行通孔的加工,形成通孔;
步骤二,采用等离子体增强化学气相沉积技术隔断填充金属与Si之间的电导通,沉积绝缘层;
步骤三,在Cu和半导体本体之间沉积一层阻挡层,在阻挡层表面覆盖一层Cu种子层用以导电,沉积阻挡层和种子层;
步骤四,采用电镀Cu工艺来填充硅通孔;
步骤五,采用化学机械抛光技术将多余的Cu去除,平坦化晶圆表面;
步骤六,将晶圆的磨削、抛光、保护膜去除和划片膜粘贴等工序集合在一台设备内,减薄晶圆。
2.根据权利要求1所述基于改进硅通孔技术的多层芯片三维堆叠封装方法,其特征在于:所述步骤一中,具体步骤包括:
采用深反应离子刻蚀技术将聚合物钝化层的沉积和对单晶硅的刻蚀这两种工艺过程组合到一起循环交替进行,进而形成侧壁陡直的高深宽比扇贝结构;深反应离子刻蚀技术的具体过程为:首先使用SF6刻蚀Si表面,然后在侧壁上沉积一层(CF2)n高分子钝化膜,再通入SF6刻蚀掉钝化膜,接着进行Si基材的刻蚀,如此反复,从而形成一个局部的各向异性刻蚀。
3.根据权利要求1所述基于改进硅通孔技术的多层芯片三维堆叠封装方法,其特征在于:所述步骤二中,具体步骤包括:
采用等离子体增强化学气相沉积技术进行绝缘层的沉积,隔断填充金属与Si之间的电导通;通孔内壁绝缘层材料包括硅氧化物、硅氮化物和聚合物等。
4.根据权利要求1所述基于改进硅通孔技术的多层芯片三维堆叠封装方法,其特征在于:所述步骤三中,具体步骤包括:
在Cu和半导体本体之间沉积一层阻挡层,阻挡Cu向SiO2中扩散,提高Cu在SiO2表面的黏附强度;采用电镀的方式来生长Cu,在阻挡层表面覆盖一层Cu种子层用以导电,电镀液中的Cu离子与电子结合形成镀在种子层表面的Cu。
5.根据权利要求1所述基于改进硅通孔技术的多层芯片三维堆叠封装方法,其特征在于:所述步骤四中,具体步骤包括:
选用Cu作为硅通孔的填充材料,采用电镀Cu工艺来填充硅通孔;利用特殊的电镀促进剂和抑制剂来加速通孔内部的沉积速率和抑制通孔外表面的沉积速率,调整促进剂和抑制剂的比例而防止产生电镀空洞。
6.根据权利要求1所述基于改进硅通孔技术的多层芯片三维堆叠封装方法,其特征在于:所述步骤五中,具体步骤包括:
采用化学机械抛光技术将多余的Cu去除并将晶圆表面平坦化;Cu的研磨工艺分三步进行:首先用较快的研磨速率去除晶圆表面大部分的Cu;其次通过降低研磨速率研磨掉与阻挡层接触的Cu,使研磨停留在阻挡层上;最后研磨掉阻挡层和少量的氧化硅。
7.根据权利要求1所述基于改进硅通孔技术的多层芯片三维堆叠封装方法,其特征在于:所述步骤六中,具体步骤包括:
进行晶圆背面的减薄使硅通孔露出,在晶圆级多层堆叠技术中将多片晶圆进行堆叠键合;采用复合方法进行晶圆的减薄,首先利用机械磨削将晶圆减薄到一定程度后,然后利用化学机械抛光技术和湿法腐蚀等减薄工艺进一步减薄至目标厚度。
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