CN116126288B - Random number generation circuit and method based on resistive random access memory - Google Patents
Random number generation circuit and method based on resistive random access memory Download PDFInfo
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Abstract
本发明公开一种基于阻变存储器的随机数发生电路及方法，涉及半导体技术领域。所述电路包括：第一熵产生模块、第二熵产生模块和电流比较模块；第一熵产生模块包括：第一熵产生阻变存储器单元和第一晶体管；第二熵产生模块包括：第二熵产生阻变存储器单元和第二晶体管；第一晶体管用于根据第一控制信号输出第一电流信号；第一熵产生阻变存储器单元用于根据第一电流信号输出第一熵电导值；第二晶体管用于根据第一控制信号输出第二电流信号；第二熵产生阻变存储器单元用于根据第二电流信号输出第二熵电导值；电流比较模块用于：对第一熵电导值和第二熵电导值求差，得到熵电导差值；根据熵电导差值产生随机数。本发明能够提高随机数的产生随机性。
The invention discloses a random number generation circuit and method based on a resistive switching memory, and relates to the field of semiconductor technology. The circuit includes: a first entropy generation module, a second entropy generation module and a current comparison module; the first entropy generation module includes: a first entropy generation resistive memory unit and a first transistor; the second entropy generation module includes: a second an entropy generating resistive switching memory unit and a second transistor; the first transistor is used to output a first current signal according to the first control signal; the first entropy generating resistive switching memory unit is used to output a first entropy conductance value according to the first current signal; The two transistors are used to output a second current signal according to the first control signal; the second entropy generating resistive memory unit is used to output a second entropy conductance value according to the second current signal; the current comparison module is used to: compare the first entropy conductance value and The difference between the second entropy conductance values is obtained to obtain the entropy conductance difference value; a random number is generated based on the entropy conductance difference value. The invention can improve the randomness of random number generation.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a random number generation circuit and method based on a resistance random access memory.
Background
The true random number generator uses the inherent randomness of the physical variable as an entropy source, and plays an important role in encryption communication and reliable information storage in the current Internet of things age. Conventional true random number generators using complementary metal oxide semiconductors (ComplementaryMetalOxideSemiconductor, CMOS) are limited by the low quality of entropy generation, excessive entropy source area, and excessive power consumption. The true random number generator based on a resistive random number memory (ResistiveRandomAccessMemory, RRAM) has the advantage that entropy is easy to extract and supports the generation of highly parallel random numbers. In view of this, a true random number generator based on a resistive random number memory is an important tool for supporting information storage and communication security.
In the prior art, as a commonly used method, randomness is achieved by changing the resistance state in the resistive random access memory, but it is difficult to achieve ideal speed and energy consumption by the method, because the switching of the resistance state in the resistive random access memory is often costly. As another commonly used method, by extracting from random telegraph noise (RTN, randomTelegraphNoise) or f-multiplied noise (1/fnoise), the randomness of this method is limited by the time for the oxygen vacancies in the resistive random access memory to capture and release electrons. Therefore, the randomness of generating true random numbers is not high in the prior art.
Disclosure of Invention
The invention aims to provide a random number generation circuit and a random number generation method based on a resistance random access memory, which can improve the randomness of random number generation.
In order to achieve the above object, the present invention provides the following solutions:
a truly resistive random number generation circuit, comprising: the device comprises a first entropy generation module, a second entropy generation module and a current comparison module; the first entropy generating module includes: a first entropy generating resistive memory cell and a first transistor; the second entropy generating module includes: a second entropy generating resistive memory cell and a second transistor;
the top electrode end of the first entropy generation resistive random access memory unit and the top electrode end of the second entropy generation resistive random access memory unit are connected with the current comparison module; the bottom electrode end of the first entropy generation resistance random access memory unit is connected with the drain electrode end of the first transistor; the second entropy produces resistive memory
A bottom electrode terminal of the memory cell is connected with a drain terminal of the second transistor; the source 5 terminal of the first transistor and the source terminal of the second transistor are both grounded; the gate terminal of the first transistor and the gate terminal of the second transistor are used for inputting a first control signal;
the first transistor is used for outputting a first current signal according to the first control signal;
the first entropy generation resistive random access memory unit is used for outputting a first entropy conductance value according to the first current signal;
0 the second transistor is used for outputting a second current signal according to the first control signal;
the second entropy generation resistive random access memory unit is used for outputting a second entropy conductance value according to the second current signal;
the current comparison module is used for:
obtaining an entropy conductance difference value by differentiating the first entropy conductance value and the second entropy conductance value; and 5, generating random numbers according to the entropy conductance difference value.
Optionally, the current comparison module employs a current sense amplifier.
Optionally, the method further comprises: a current replication module;
the input end of the current copying module is respectively connected with the first entropy generating module and the second entropy generating module; the output end of the current copying module is connected with the current comparing module; the current copying module is used for transmitting the first entropy conductance value and the second entropy conductance value to the current comparing module.
Optionally, the current replication module specifically includes: a first current mirror and a second current mirror;
the input end of the first current mirror is connected with the first entropy generation module; the input end of the second current mirror is connected with the second entropy generating module; the output end of the first current mirror and the output end of the second 5 current mirror are connected with the current comparison module;
the first current mirror is used for transmitting the first entropy conductance value to the current comparison module;
the second current mirror is configured to transmit the second entropy conductance value to the current comparison module.
Optionally, the first current mirror and the second current mirror are each comprised of two identically sized n-type substrate p-channel transistors.
Optionally, the method further comprises: an oscilloscope; the oscilloscope is connected with the current comparison module;
the oscillograph is used for displaying a waveform chart of the random number sequence; the random number sequence is composed of a plurality of the random numbers.
The invention also provides a random number generation method based on the resistance random number memory, which is applied to the random number generation circuit based on the resistance random number memory, and comprises the following steps:
acquiring a first entropy conductance value and a second entropy conductance value; the first entropy conductance value is generated by the first entropy generating resistive random access memory unit when a first current signal is input; the first current signal is output by the first transistor under the action of a first control signal; the second entropy conductance value is generated by the second entropy generating resistive random access memory unit when a second current signal is input; the second current signal is output by the second transistor under the action of the first control signal;
obtaining an entropy conductance difference value by differentiating the first entropy conductance value and the second entropy conductance value;
and generating random numbers according to the entropy conductance difference value.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention discloses a random number generation circuit and a random number generation method based on a resistance random number memory. Wherein the first entropy generating module comprises: a first entropy generating resistive memory cell and a first transistor; the second entropy generating module includes: the second entropy produces a resistive memory cell and a second transistor. The invention forms a differential circuit through the first entropy generating module, the second entropy generating module and the current comparing module, and can effectively eliminate the damage of non-Gaussian noise of the resistance random access memory in the circuit to randomness because of no extra pulse operation and complex conductance value extracting circuit, thereby realizing high random bit stream output and low power consumption, and improving the generation probability offset of random numbers and the generation randomness of true random numbers by controlling the conductance value of the transistor-resistance random access memory unit through the first control signal.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a random number generating circuit based on a resistive random access memory according to the present invention;
FIG. 2 is a schematic diagram of waveforms of control signals and corresponding output results under different conditions generated by a random number generating circuit based on a resistive random access memory according to the present embodiment;
FIG. 3 is a schematic diagram showing variation of entropy conductance values of the first entropy generating module and the second entropy generating module when the random number generating circuit based on the resistive random number memory generates random numbers according to the present embodiment;
FIG. 4 is a flow chart of a random number generation method based on a resistive random access memory according to the present invention.
Symbol description:
11-a first entropy generation module; 12-a second entropy generation module; 21-a first current mirror; 22-a second current mirror; 111-a first entropy generating resistive memory cell; 121-a second entropy generating resistive memory cell; 112-a first transistor; 122-a second transistor; 31-current sense amplifier.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention aims to provide a random number generation circuit and a random number generation method based on a resistance random access memory, which can improve the randomness of random number generation.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
As shown in the embodiment of fig. 1, the present invention provides a random number generating circuit based on a resistive random access memory, comprising: a first entropy generating module 11, a second entropy generating module 12 and a current comparing module; the first entropy generating module 11 includes: a first entropy generating resistive memory cell 111 and a first transistor 112; the second entropy generating module 12 comprises: the second entropy produces a resistive memory cell 121 and a second transistor 122.
The top electrode terminal of the first entropy generation resistive random access memory unit 111 and the top electrode terminal of the second entropy generation resistive random access memory unit 121 are connected with the current comparison module; a bottom electrode terminal of the first entropy generating resistive memory cell 111 is connected to a drain terminal of the first transistor 112; a bottom electrode terminal of the second entropy generating resistive memory cell 121 is connected to a drain terminal of the second transistor 122; the source terminal of the first transistor 112 and the source terminal of the second transistor 122 are both grounded; the gate terminal of the first transistor 112 and the gate terminal of the second transistor 122 are both used for inputting a first control signal.
The first transistor 112 is configured to output a first current signal according to the first control signal.
The first entropy generating resistive random access memory unit 111 is configured to output a first entropy conductance value according to the first current signal.
The second transistor 122 is configured to output a second current signal according to the first control signal.
The second entropy generating resistive random access memory unit 121 is configured to output a second entropy conductance value according to the second current signal.
The current comparison module is used for: obtaining an entropy conductance difference value by differentiating the first entropy conductance value and the second entropy conductance value; and generating random numbers according to the entropy conductance difference value.
Based on the above structure, the random number generating circuit based on the resistive random access memory further comprises: and a current replication module.
The input end of the current copying module is respectively connected with the first entropy generating module 11 and the second entropy generating module 12; and the output end of the current copying module is connected with the current comparing module. The current replication module is configured to transmit the first entropy conductance value and the second entropy conductance value to the current comparison module.
As a specific embodiment of the current replication module, specifically including: a first current mirror 21 and a second current mirror 22.
The input end of the first current mirror 21 is connected with the first entropy generating module 11; the input end of the second current mirror 22 is connected with the second entropy generating module 12; the output end of the first current mirror 21 and the output end of the second current mirror 22 are both connected with the current comparison module. The first current mirror 21 is used for transmitting the first entropy conductance value to the current comparison module. The second current mirror 22 is used to transfer the second entropy conductance value to the current comparison module.
Wherein the input current of the first current mirror 21 is equal to the output current; the input current of the second current mirror 22 is equal to the output current;
as a specific embodiment, the first current mirror 21 and the second current mirror 22 are each composed of two n-type substrate p-channel transistors of the same size.
As a specific embodiment of the current comparison module, a current sense amplifier 31 is employed. When the current comparison module adopts the current sense amplifier 31, the output end of the first current mirror 21 is connected with the positive electrode input end of the first current sense amplifier 31; the output of the second current mirror 22 is connected to the negative input of the first current sense amplifier 31.
As a specific embodiment, the random number generating circuit based on the resistive random access memory further includes: an oscilloscope. The oscilloscope is connected with the current comparison module; the oscillograph is used for displaying a waveform chart of the random number sequence; the random number sequence is composed of a plurality of the random numbers.
In addition, when the random number generation circuit based on the resistive random number memory is actually operated, the reset of the current sense amplifier 31 and the random number generation operation are controlled by the second control signal
Wherein, the first control signal and the second control signal can be manually input or generated by a system when the system is applied in particular. The first current signal and the second current signal have the same waveform.
As in the embodiment shown in fig. 2, control signal waveforms are provided when random numbers are generated by the random number generation circuit based on the resistive random access memory, and corresponding output results in different situations.
Based on the random number generating circuit based on the resistive random access memory, the process of generating the random number provided in this embodiment can be divided into the following two steps:
in the first process, the gates of the first and second transistors 112 and 122 are controlled by the first control signal (CLK) to be applied to the high level VDD such that the first and second entropy generating blocks 11 and 12 are powered. The currents of the first entropy generating module 11 and the second entropy generating module 12 are copied to the positive and negative input of the current sense amplifier 31 through the first current mirror 21 and the second current mirror 22, respectively. If the current at the positive input is greater than the current at the negative input, the potential at the output node approaches "0", indicating a logic "0", otherwise the potential at the output node remains high, indicating a logic "1". In the second process, as the second control signal rises to a high level, the cross-coupled latch circuit in the current sense amplifier 31 enters a reset phase and the output node returns further to a high level in preparation for the next comparison to produce a random number operation cycle.
Based on the above embodiments, fig. 3 shows the change of the entropy conductance values of the first entropy generating module 11 and the second entropy generating module 12 when the random number generating circuit based on the resistive random access memory provided by the present invention generates random numbers.
In connection with the random number generation circuit based on the resistive random access memory shown in fig. 1, due to the process error in the actual complementary metal oxide semiconductor (ComplementaryMetalOxideSemiconductor, CMOS) process, the probability that the conductance values of the first entropy generating module 11 and the second entropy generating module 12 are equal to generate random numbers may deviate. The conductance value of the first entropy generating module 11 is adjusted according to the probability deviation of random number generation to fix the conductance value of the second entropy generating module 12. If the generation probability of the random number is just 0.5, the conductance values of the first entropy generation module 11 and the second entropy generation module 12 are equal; if the probability of generating the random number is greater than 0.5, selecting the conductance difference (delta G) between the first entropy generating module 11 and the second entropy generating module 12 to be greater than 0; if the probability of generating the random number is less than 0.5, the conductance difference (Δg) between the first entropy generating module 11 and the second entropy generating module 12 is selected to be less than 0.
The above embodiment has the following advantages:
the random number generation circuit based on the resistive random number generation memory provided by the embodiment completes the generation process of the random number by comparing the magnitude of the conductance values of the two entropy generation units. Compared with the prior art, the method and the device extract the conductance value fluctuation caused by high-frequency noise (mainly shot noise) in the resistive random access memory, and can realize high random bit stream output and low power consumption due to no extra pulse operation and complex extraction circuit. The embodiment adopts the differential circuit of the two entropy generating units, so that the damage to randomness caused by non-Gaussian noise can be effectively eliminated.
The embodiment shown in fig. 4 also provides a random number generation method based on a resistive random number memory, which is applied to the random number generation circuit based on the resistive random number memory, and the random number generation method based on the resistive random number memory comprises the following steps:
step 100: acquiring a first entropy conductance value and a second entropy conductance value; the first entropy conductance value is generated by the first entropy generating resistive random access memory unit 111 when the first current signal is input; the first current signal is output by the first transistor 112 under the action of a first control signal; the second entropy conductance value is generated by the second entropy generating resistive random access memory unit 121 when the second current signal is input; the second current signal is output by the second transistor 122 under the action of the first control signal.
Step 200: and obtaining an entropy conductance difference value by differentiating the first entropy conductance value and the second entropy conductance value.
Step 300: and generating random numbers according to the entropy conductance difference value.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to assist in understanding the core concept of the invention; also, it is within the scope of the present invention to be modified by those of ordinary skill in the art in light of the present teachings. In view of the foregoing, this description should not be construed as limiting the invention.
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