CN111562901A - Random number generator and random number generation method - Google Patents
Random number generator and random number generation method Download PDFInfo
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Abstract
A random number generator and a random number generation method. The random number generator includes: a resistive random access memory; the resistance value disturbance circuit is coupled to the resistive random access memory and configured to execute n resistance value disturbance operations on the resistive random access memory so as to disturb the resistance value of the resistive random access memory, so that the resistance value of the resistive random access memory becomes a disturbed resistance value, each resistance value disturbance operation in the n resistance value disturbance operations comprises a setting operation and a resetting operation on the resistive random access memory, and n is a positive integer; an encoding circuit coupled to the resistive random access memory and configured to encode the perturbed resistance value of the resistive random access memory to generate a random number. The random number generator utilizes the nonlinear characteristic of the resistive random access memory, can realize self calibration, has the advantages of high reliability, small circuit area, low power consumption and high speed, and is very suitable for large-scale parallel.
Description
Technical Field
Embodiments of the present disclosure relate to a random number generator and a random number generation method.
Background
Random Number generators can be divided into two categories, Pseudo Random Number Generators (PRNGs) and True Random Number Generators (TRNGs). TRNG can generate random numbers by extracting randomness in Complementary Metal Oxide Semiconductor (CMOS) circuits or novel devices, such as Resistive Random Access Memories (RRAMs). Compared to PRNGs, TRNGs are capable of generating infinitely long and theoretically unpredictable sequences of random numbers, with higher security and better randomness.
Disclosure of Invention
At least one embodiment of the present disclosure provides a random number generator, including: a resistive random access memory; a resistance value disturbance circuit, coupled to the resistive random access memory, configured to perform n resistance value disturbance operations on the resistive random access memory to disturb a resistance value of the resistive random access memory, so that the resistance value of the resistive random access memory becomes a disturbed resistance value, each of the n resistance value disturbance operations includes performing a set operation and a reset operation on the resistive random access memory, n is a positive integer; an encoding circuit coupled to the resistive random access memory and configured to encode the perturbed resistance value of the resistive random access memory to generate a random number.
For example, in the random number generator provided in at least one embodiment of the present disclosure, when performing a resistance value perturbation operation once, the resistance value perturbation circuit is configured to perform the reset operation on the resistive random access memory and perform the set operation on the resistive random access memory on which the reset operation is performed to perturb the resistance value of the resistive random access memory.
For example, in a random number generator provided in at least one embodiment of the present disclosure, the resistance value perturbation circuit includes a set operation sub-circuit and a reset operation sub-circuit; the setting operation sub-circuit is configured to apply a setting pulse to the resistive random access memory to perform the setting operation; the reset operation sub-circuit is configured to apply a reset pulse to the resistive random access memory to perform the reset operation.
For example, in the random number generator provided in at least one embodiment of the present disclosure, the resistance value perturbation circuit is configured to perform the n resistance value perturbation operations on the resistive random access memory, so that a perturbed resistance value of the resistive random access memory is in a resistance value symmetric region.
For example, in a random number generator provided in at least one embodiment of the present disclosure, the encoding circuit includes a voltage applying sub-circuit, a speed measuring sub-circuit, and an output sub-circuit; the voltage applying sub-circuit is coupled to the resistive random access memory and configured to apply a control voltage to a word line end of the resistive random access memory and apply a read voltage to a bit line end of the resistive random access memory to control a source line end output current of the resistive random access memory; the speed measuring sub-circuit is coupled to the resistive random access memory and is configured to measure and output an energy storage speed under the condition of storing energy by using the current output by a source line end of the resistive random access memory; the output sub-circuit is coupled to the speed measurement sub-circuit and configured to generate the random number according to the energy storage speed.
For example, in at least one embodiment of the present disclosure, a random number generator is provided, wherein the speed measurement sub-circuit includes a tank sub-circuit, a comparator sub-circuit, a clock pulse generation sub-circuit, and a counter sub-circuit; the energy storage sub-circuit is coupled to the resistive random access memory and configured to store energy by using the current output by a source line end of the resistive random access memory to obtain an energy storage voltage; the comparison sub-circuit is coupled to the energy storage sub-circuit and configured to compare the energy storage voltage with a reference voltage to obtain a voltage comparison result; the clock pulse generation sub-circuit is configured to generate clock pulses; the counting sub-circuit is coupled to the comparing sub-circuit and the clock pulse generating sub-circuit, and is configured to count the clock pulses, and stop counting and output a current count value as the energy storage speed in response to the voltage comparison result indicating that the energy storage voltage exceeds the reference voltage.
For example, in a random number generator provided in at least one embodiment of the present disclosure, the output sub-circuit is configured to operate on the current count value to obtain an intermediate number, and generate the random number according to the intermediate number.
For example, in a random number generator provided in at least one embodiment of the present disclosure, the operation includes modulo-2LOperation, said intermediate number being said randomThe number of machines, and the intermediate number is 2LCarry the number, L is a positive integer.
For example, in a random number generator provided in at least one embodiment of the present disclosure, the counting sub-circuit includes a 1-bit counter, the 1-bit counter is configured to output a 1-bit 2-ary number as the current count value, and the output sub-circuit is configured to output the current count value as the random number.
For example, in a random number generator provided in at least one embodiment of the present disclosure, the encoding circuit includes a voltage-applying sub-circuit, an analog-to-digital conversion sub-circuit, and an output sub-circuit; the voltage applying sub-circuit is coupled to the resistive random access memory and configured to apply a control voltage to a word line end of the resistive random access memory and apply a read voltage to a bit line end of the resistive random access memory to control a source line end output current of the resistive random access memory; the analog-to-digital conversion sub-circuit is coupled to the resistive random access memory and configured to convert the current output by a source line end of the resistive random access memory into a digital signal value; the output sub-circuit is coupled to the analog-to-digital conversion sub-circuit and configured to generate the random number according to the digital signal value.
For example, in a random number generator provided in at least one embodiment of the present disclosure, the output sub-circuit is configured to operate on the digital signal value to obtain an intermediate number, and generate the random number according to the intermediate number.
For example, in a random number generator provided in at least one embodiment of the present disclosure, the operation includes modulo-2LOperation, the intermediate number is the random number, and the intermediate number is 2LCarry the number, L is a positive integer.
For example, in a random number generator provided in at least one embodiment of the present disclosure, the output sub-circuit includes a register configured to register the digital signal value and take the lowest L bits of the digital signal value as the intermediate number.
For example, at least one embodiment of the present disclosure provides that the random number generator further includes a control circuit, coupled to the resistance value perturbation circuit and the encoding circuit, configured to control the resistance value perturbation circuit and the encoding circuit to generate a predetermined number of random numbers.
At least one embodiment of the present disclosure further provides a method for generating a random number, including: executing n resistance value disturbance operations on a first resistive random access memory to disturb the resistance value of the first resistive random access memory so that the resistance value of the first resistive random access memory becomes a disturbed first resistance value, wherein each resistance value disturbance operation in the n resistance value disturbance operations comprises a setting operation and a resetting operation on the first resistive random access memory, and n is a positive integer; encoding a first perturbed resistance value of the first resistive random access memory to generate a first random number.
For example, in at least one embodiment of the present disclosure, a method is provided, in which each of the n resistance value perturbation operations includes: the reset operation is performed on the first resistance change memory, and the set operation is performed on the first resistance change memory on which the reset operation is performed, so as to disturb a resistance value of the first resistance change memory.
For example, in a method provided in at least one embodiment of the present disclosure, the performing the set operation includes: applying a set pulse to the first resistive random access memory; performing the reset operation includes: and applying a reset pulse to the first resistive random access memory.
For example, in a method provided by at least one embodiment of the present disclosure, performing n resistance value perturbation operations on a first resistive random access memory to perturb a resistance value of the first resistive random access memory so that the resistance value of the first resistive random access memory becomes a perturbed first resistance value includes: and executing the n resistance value disturbance operations on the first resistive random access memory so as to enable the first disturbed resistance value of the first resistive random access memory to be in a resistance value symmetrical region.
For example, in a method provided by at least one embodiment of the present disclosure, encoding a first disturbed resistance value of the first resistive random access memory to generate a first random number includes: applying a control voltage to a word line end of the first resistive random access memory and applying a read voltage to a bit line end of the first resistive random access memory to control a source line end of the first resistive random access memory to output current; storing energy by using the current output by the source line end of the first resistive random access memory to measure and output an energy storage speed; and generating the first random number according to the energy storage speed.
For example, in a method provided by at least one embodiment of the present disclosure, storing energy using the current output from a source line end of the first resistive random access memory to measure and output an energy storage speed includes: storing energy by using the current output by the source line end of the first resistive random access memory to obtain an energy storage voltage; comparing the energy storage voltage with a reference voltage to obtain a voltage comparison result; generating a clock pulse; counting the clock pulses, stopping counting in response to the voltage comparison result indicating that the energy storage voltage exceeds the reference voltage, and outputting a current count value as the energy storage speed.
For example, in at least one embodiment of the present disclosure, a method for generating the first random number according to the energy storage speed includes: and operating the current count value to obtain an intermediate number, and generating the first random number according to the intermediate number.
For example, in a method provided by at least one embodiment of the present disclosure, encoding a first disturbed resistance value of the first resistive random access memory to generate a first random number includes: applying a control voltage to a word line end of the first resistive random access memory and applying a read voltage to a bit line end of the first resistive random access memory to control a source line end of the first resistive random access memory to output current; converting the current output by the source line end of the first resistive random access memory into a digital signal value; generating the first random number from the digital signal value.
For example, in at least one embodiment of the present disclosure, a method for generating the first random number according to the digital signal value includes: and operating the digital signal value to obtain an intermediate number, and generating the first random number according to the intermediate number.
For example, the method provided by at least one embodiment of the present disclosure further includes: performing m1 resistance value disturbance operations on a second resistive random access memory to disturb the resistance value of the second resistive random access memory so that the resistance value of the second resistive random access memory becomes a second disturbed resistance value, wherein each resistance value disturbance operation in the m1 resistance value disturbance operations includes performing a set operation and a reset operation on the second resistive random access memory, the first resistive random access memory and the second resistive random access memory are different, and m1 is a positive integer; encoding a second disturbed resistance value of the second resistive random access memory to generate a second random number.
For example, the method provided by at least one embodiment of the present disclosure further includes: performing m2 resistance value disturbance operations on the first resistive random access memory to disturb the resistance value of the first resistive random access memory so that the resistance value of the first resistive random access memory becomes a third disturbed resistance value, wherein each resistance value disturbance operation in the m2 resistance value disturbance operations comprises a setting operation and a resetting operation on the first resistive random access memory, and m2 is a positive integer; encoding a third perturbed resistance value of the first resistive random access memory to generate a third random number.
For example, in a method provided in at least one embodiment of the present disclosure, the first disturbed resistance value and the third disturbed resistance value are different.
Drawings
To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.
Fig. 1 is a schematic block diagram of a random number generator provided in at least one embodiment of the present disclosure;
fig. 2A illustrates a schematic diagram of one example of a resistive-switching memory;
fig. 2B illustrates a schematic diagram of performing a set operation on a resistance change memory;
fig. 2C illustrates a schematic diagram of performing a reset operation on the resistance change memory;
fig. 3A illustrates a schematic diagram of a set operation and a reset operation in relation to a change in a resistance value of a resistance change memory;
fig. 3B illustrates a diagram of a resistance value disturbance operation in relation to a change in a resistance value of the resistance change memory;
fig. 4A and 4B illustrate disturbed resistance values of the resistance change memory;
fig. 5 is a schematic block diagram of one example of a random number generator provided by at least one embodiment of the present disclosure;
FIG. 6 is a schematic block diagram of a speed measurement sub-circuit provided in at least one embodiment of the present disclosure;
fig. 7 is a schematic diagram of one example of a random number generator provided in at least one embodiment of the present disclosure;
fig. 8 illustrates a schematic diagram of random numbers generated by a random number generator provided by at least one embodiment of the present disclosure;
fig. 9 is a schematic block diagram of another example of a random number generator provided by at least one embodiment of the present disclosure;
fig. 10 is a schematic diagram of another example of a random number generator provided in at least one embodiment of the present disclosure;
fig. 11 is a flowchart of a method for generating a random number according to at least one embodiment of the present disclosure;
fig. 12 is a flowchart of an example of a method for generating a random number according to at least one embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.
Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
Currently, the TRNG technology is mainly implemented by the following methods: (1) CMOS thermal noise; (2) RRAM (or Magnetic Random Access Memory (MRAM)) switching speed; (3) RRAM (or MRAM) switching threshold; (4) RRAM read noise. For a design that implements a TRNG using approaches (1) (2) (3), additional calibration circuitry is required to ensure that the TRNG can operate in a desired state to generate high entropy random numbers. First, the use of calibration circuitry increases power consumption; second, many applications require TRNGs to be able to work in parallel to achieve very high speeds, and the use of calibration circuits exacerbates the speed-area conflict. Therefore, implementing the design of the TRNG using the means (1) (2) (3) increases power consumption and makes it difficult to achieve balance between circuit area and speed.
One design for realizing TRNG by using the above method (4) includes: reading the resistance value of the RRAM twice continuously; comparing the resistance values read twice; if the resistance value read for the first time is larger than the resistance value read for the second time, outputting 1; if the resistance value read for the first time is smaller than the resistance value read for the second time, outputting 0; if the resistance value read for the first time is equal to the resistance value read for the second time, the output is kept unchanged. For a TRNG design implemented in the manner (4) described above, the uncontrollable nature of RRAM read noise may result in the inability to generate random numbers with high randomness. For example, for a partial RRAM, the read noise may be so small as to be undetectable by the circuit. For example, for a partial RRAM, read noise may be initially large but become small after a period of time. Therefore, it is difficult to ensure reliability in the TRNG design implemented by the above-described method (4).
It should be noted that the indexes for evaluating TRNG include speed, reliability, circuit area, power consumption, and the like, where speed refers to the number of random numbers generated per second (bits/second); the reliability refers to whether unpredictable random numbers can be generated under different temperatures, voltages and working durations; the circuit area refers to the size of the area occupied by the device; power consumption refers to the energy (joules/bit) required to generate a random number per bit.
In summary, the TRNGs in the prior art have respective disadvantages.
At least one embodiment of the present disclosure provides a random number generator, including: a resistive random access memory; the resistance value disturbance circuit is coupled to the resistive random access memory and configured to execute n resistance value disturbance operations on the resistive random access memory so as to disturb the resistance value of the resistive random access memory, so that the resistance value of the resistive random access memory becomes a disturbed resistance value, each resistance value disturbance operation in the n resistance value disturbance operations comprises a setting operation and a resetting operation on the resistive random access memory, and n is a positive integer; an encoding circuit coupled to the resistive random access memory and configured to encode the perturbed resistance value of the resistive random access memory to generate a random number.
At least one embodiment of the present disclosure further provides a method for generating a random number corresponding to the random number generator.
The random number generator and the random number generation method provided by the embodiment of the disclosure utilize the nonlinear characteristics of the resistive random access memory, can realize self calibration, have the advantages of high reliability, small circuit area, low power consumption and high speed, and are very suitable for large-scale parallel. It should be noted that in the embodiment of the present disclosure, the self-calibration means that the resistance value of the resistance change memory in the random number generator may spontaneously fluctuate within a specific range without human intervention.
Embodiments of the present disclosure and examples thereof are described in detail below with reference to the accompanying drawings.
Fig. 1 is a schematic block diagram of a random number generator provided in at least one embodiment of the present disclosure. As shown in fig. 1, the random number generator 100 includes a resistance change memory 110, a resistance value perturbation circuit 120, and an encoding circuit 130. The resistance value perturbation circuit 120 is coupled to the resistive random access memory 110 and configured to perform n resistance value perturbation operations on the resistive random access memory 110 to perturb the resistance value of the resistive random access memory 110, so that the resistance value of the resistive random access memory 110 becomes a perturbed resistance value, each of the n resistance value perturbation operations includes performing a set operation and a reset operation on the resistive random access memory 110, where n is a positive integer; the encoding circuit 130 is coupled to the resistive random access memory 110 and configured to encode the perturbed resistance value of the resistive random access memory 110 to generate a random number.
For example, the random number generator is a true random number generator, and the generated random number is a true random number.
The random number may be a 2-ary random number (i.e., the random number is 0 or 1), or may be another random number, such as a 4-ary, 10-ary, 16-ary random number. In the embodiments of the present disclosure, in order to describe the technical solutions of the present disclosure more clearly, if there is no special description, the random number refers to the random number in the 2-ary form as an example for description.
For example, fig. 2A illustrates a schematic diagram of one example of a resistance change memory, fig. 2B illustrates a schematic diagram of performing a set operation on the resistance change memory, and fig. 2C illustrates a schematic diagram of performing a reset operation on the resistance change memory. The structure of the resistance change memory and the set operation and the reset operation are explained below with reference to fig. 2A to 2C.
For example, the resistance change memory may employ a 1T1R structure. As shown in fig. 2A, the resistive random access memory includes a transistor M1 and a resistive random access element R1, a gate of the transistor M1 is connected to the word line terminal WL, a first pole of the transistor M1 may be a drain and configured to be connected to a second pole (e.g., a cathode) of the resistive random access element R1, a first pole (e.g., an anode) of the resistive random access element R1 is connected to the bit line terminal BL, and a second pole of the transistor M1 may be a source and configured to be connected to the source line terminal SL. If the transistor M1 is an N-type transistor, as shown in fig. 2A and 2B, for the set operation, the voltage V is applied to the word line terminal WL of the resistance change memoryWLFor high level of control voltage, for resistance changeVoltage V applied to bit line terminal BL of memoryBLA voltage V applied to a source line terminal SL of the resistive random access memory for a SET (SET) pulseSLA low level voltage (e.g., ground). As shown in fig. 2A and 2C, for the reset operation, the voltage V applied to the word line terminal WL of the resistance change memoryWLA voltage V applied to a source line terminal SL of the resistance change memory for a high-level control voltageSLA voltage V applied to a bit line terminal BL of the resistance change memory for a RESET (RESET) pulseBLA low level voltage (e.g., ground).
It should be noted that, in the embodiments of the present disclosure, in order to distinguish two poles of a transistor except for a gate, one pole is directly described as a first pole, and the other pole is directly described as a second pole.
For example, the transistor M1 may be a thin film transistor or a field effect transistor (e.g., MOS field effect transistor) or other switching device with the same characteristics, and the source and drain of the transistor may be symmetrical in structure, so that the source and drain may not be different in structure. For example, the transistor M1 may be an N-type transistor as shown in fig. 2A-2C, but the disclosure is not limited thereto, and the transistor M1 may also be a P-type transistor. For clarity and consistency, the following embodiments are described by taking the transistor M1 as an N-type transistor as an example.
For example, the number n of resistance value disturbance operations for disturbing the resistance value of the resistive random access memory 110 may be determined according to actual circumstances. For example, in the case where n is equal to 1 (i.e., one resistance perturbation operation corresponds to generation of one random number), the total time of the resistance perturbation operation is the shortest, and the random number generator generates the random number the fastest. For example, the speed of generating random numbers per resistance change memory is 1 Mbit/s.
For example, when performing a resistance value disturbance operation once, the resistance value disturbance circuit 120 is configured to perform a reset operation on the resistance change memory and perform a set operation on the resistance change memory on which the reset operation is performed to disturb the resistance value of the resistance change memory. For example, when performing the resistance value perturbation operation once, the resistance value perturbation circuit 120 may also be configured to perform a set operation on the resistive random access memory and perform a reset operation on the resistive random access memory on which the set operation is performed to perturb the resistance value of the resistive random access memory. For clarity and consistency, the following embodiments are described by taking the example of performing the reset operation first and then performing the set operation.
It should be noted that each resistance value disturbing operation may also include performing a set operation and a reset operation a plurality of times, or performing a set operation and a plurality of reset operations, or performing a set operation and a reset operation. The order and the number of the set operation and the reset operation in the resistance value disturbance operation are not particularly limited by the embodiments of the present disclosure.
For example, as shown in fig. 1, in at least one embodiment of the present disclosure, the resistance value perturbation circuit 120 includes a set operation sub-circuit 121 and a reset operation sub-circuit 122; the set operation sub-circuit 121 is configured to apply a set pulse to the resistance change memory to perform a set operation; the reset operation sub-circuit 122 is configured to apply a reset pulse to the resistance change memory to perform a reset operation.
It should be noted that, in the embodiment of the present disclosure, the resistance value disturbance operation performed on the resistive random access memory is different from the conventional read and write operation performed on the resistive random access memory. Firstly, the resistance value variation range of the resistive random access memory corresponding to the resistance value disturbance operation is different from the resistance value variation range of the resistive random access memory corresponding to the conventional read-write operation. For example, the resistance value disturbance operation is intended to cause the resistance value of the resistive random access memory to generate small-amplitude fluctuation, and the resistance value of the resistive random access memory corresponding to the resistance value disturbance operation has a small change range, for example, typically 50k Ω to 100k Ω; the conventional read/write operation aims to generate a change which can be clearly distinguished in the resistance value of the resistive random access memory, and the resistance value of the resistive random access memory corresponding to the conventional read/write operation has a large change range, for example, 20k Ω to 1M Ω. Secondly, the amplitudes of the set pulse and the reset pulse corresponding to the resistance value disturbance operation are different from the amplitudes of the set pulse and the reset pulse corresponding to the conventional read-write operation. For example, when the resistance value disturbance operation is performed, the pulse width (set pulse and reset pulse) is 50 nanoseconds (ns), and for the set operation, VBL1.6 volts (V), VWL＝1.5V，VSL0V; for reset operation, VSL＝1.1V，VWL＝5.0V，VBL0V. For example, when performing a normal read and write operation, the pulse width is 50 nanoseconds (ns), and for a set operation, VBL＝2.5V，VWL＝1.8V，VSL0V; for reset operation, VSL＝2.0V，VWL＝5.0V，VBL＝0V。
For example, fig. 3A illustrates a schematic diagram of the relationship of the set operation and the reset operation with the resistance value change of the resistance change memory, with the abscissa being the number of applied pulses, i.e., the number of pulses, and the ordinate being the normalized resistance value. In the example shown in fig. 3A, 200 times of reset operation and 200 times of set operation are successively performed on the resistance change memory, that is, 200 reset pulses and 200 set pulses are successively applied, wherein V is set for the reset operationSL＝1.3V，VWL＝5.0V，VBL0V; for set operation, VBL＝1.5V，VWL＝1.7V，VSL0V. As shown in fig. 3A, the reset operation increases the resistance value of the resistance change memory, and the set operation decreases the resistance value of the resistance change memory, but the larger the resistance value of the resistance change memory, the weaker the effect of the reset operation and the stronger the effect of the set operation, and vice versa. In the embodiments of the present disclosure, a characteristic that the resistance value of the resistive random access memory changes non-linearly under the effect of the set operation and the reset operation is referred to as a non-linear characteristic of the resistive random access memory.
For example, fig. 3B illustrates a graph of resistance perturbation operation versus resistance value change of the resistive random access memory, with the abscissa being the number of applied resistance perturbation operations (labeled as cycle number in fig. 3B) and the ordinate being a normalized resistance value. In the example shown in fig. 3B, the resistance value disturbance operation is continuously performed 50 times on the resistance change memory, and the one resistance value disturbance operation includes one RESET (RESET) operation and the next SET (SET) operation. As shown in fig. 3B, based on the nonlinear characteristic of the resistive random access memory, when the resistance value of the resistive random access memory is large (for example, the resistance value is larger than the dark band interval shown in fig. 3B), the effect of the set operation is stronger than the effect of the reset operation, and the resistance value of the resistive random access memory is reduced (for example, gradually reduced to the dark band interval shown in fig. 3B) by the resistance value disturbance operation; when the resistance value of the resistive random access memory is small (for example, the resistance value is smaller than the dark band interval shown in fig. 3B), the effect of the set operation is weaker than the effect of the reset operation, and the resistance value of the resistive random access memory is increased (for example, gradually increased to the dark band interval shown in fig. 3B) by the resistance value disturbance operation; when the resistance value of the resistance change memory is in the middle range (for example, the resistance value is in the dark band section in fig. 3B), the effect of the set operation is equivalent to the effect of the reset operation, and the resistance value disturbance operation causes the resistance value of the resistance change memory to fluctuate by a small amount in the middle range (for example, fluctuate in the dark band section shown in fig. 3B). In the embodiments of the present disclosure, the middle range is referred to as a resistance symmetric region of the resistive random access memory.
For example, in at least one embodiment of the disclosure, the resistance value perturbation circuit 120 is configured to perform n resistance value perturbation operations on the resistive random access memory 110, so that a perturbed resistance value of the resistive random access memory is in a resistance value symmetric region.
For example, fig. 4A and 4B illustrate perturbed resistance values of the resistive random access memory, with the abscissa being the number of applied resistance perturbation operations (labeled as cycle number in fig. 4A and 4B) and the ordinate being the resistance value (k Ω). In the example shown in fig. 4A, 10000 times of resistance value disturbance operations are continuously performed on the resistance change memory, one time of resistance value disturbance operation including one reset operation and one subsequent set operation, where V is a reset operationSL＝1.1V，VWL＝5.0V，VBL0V; for set operation, VBL＝1.6V，VWL＝1.5V，VSL0V. As shown in fig. 4A, the range of the resistance symmetric region (the dark band region shown in fig. 4A) is 50 to 100k Ω, the disturbed resistance value of the resistive random access memory sometimes jumps out of the resistance symmetric region, but based on the nonlinear characteristics of the resistive random access memory, the disturbed resistance value of the resistive random access memory returns to the resistance symmetric region again after a plurality of resistance disturbing operations. For example, fig. 4B intercepts a change process of the resistance value of the resistance change memory in fig. 4A. As shown in fig. 4B, when the resistance value of the resistance change memory is greater than 1000k Ω, resistance of the resistance change memory is performed less than 10 timesThe resistance value of the resistive random access memory is in a resistance value symmetrical region (50-100k omega) by the value disturbance operation; when the resistance value of the resistive random access memory deviates less from the resistance symmetric region (for example, the resistance value corresponding to the 7 th resistance perturbation operation in fig. 4B), the resistance value of the resistive random access memory returns to the resistance symmetric region again only by performing the resistance perturbation operation on the resistive random access memory once.
Therefore, in the embodiment of the disclosure, based on the nonlinear characteristic of the resistive random access memory, after the disturbed resistance value of the resistive random access memory jumps out of the resistance value symmetric region, the disturbed resistance value can return to the resistance value symmetric region again through the resistance value disturbing operation, that is, the random number generator in the embodiment of the disclosure can realize self calibration without an additional calibration circuit, thereby having the advantages of small circuit area and low power consumption. In addition, the self-calibration can avoid the problem that the random number obtained by a subsequent coding circuit is low in randomness due to the fact that the disturbed resistance value of the resistive random access memory is too small, namely the random number generator in the embodiment of the disclosure has the advantage of high reliability; the self-calibration can also avoid the problem that the speed of obtaining the random number by a subsequent coding circuit is slow due to the fact that the disturbed resistance value of the resistive random access memory is too large, namely the random number generator in the embodiment of the disclosure has the advantage of high speed.
For example, in some embodiments, the resistance value of the resistive random access memory 110 may be in a resistance symmetric region before performing a resistance perturbation operation on the resistive random access memory 110.
For example, fig. 5 is a schematic block diagram of one example of a random number generator provided by at least one embodiment of the present disclosure. As shown in fig. 5, the encoding circuit 130 includes a voltage application sub-circuit 131, a speed measurement sub-circuit 132, and an output sub-circuit 133. The voltage applying sub-circuit 131 is coupled to the resistive random access memory 110 and configured to apply a control voltage to a word line end WL of the resistive random access memory 110 and a read voltage to a bit line end BL of the resistive random access memory 110 to control a source line end SL of the resistive random access memory 110 to output a current; the speed measurement sub-circuit 132 is coupled to the resistive random access memory 110, and is configured to measure and output an energy storage speed when storing energy by using a current output from a source line terminal SL of the resistive random access memory 110; the output sub-circuit 133 is coupled to the speed measurement sub-circuit 132 and configured to generate a random number according to the tank speed. In this example, different perturbed resistance values will result in different currents, and different currents will result in different energy storage speeds, and thus different random numbers are generated.
For example, fig. 6 is a schematic block diagram of a speed measurement sub-circuit provided in at least one embodiment of the present disclosure. As shown in FIG. 6, the speed measurement sub-circuit 132 includes a tank sub-circuit 132-1, a comparator sub-circuit 132-2, a clock generation sub-circuit 132-3, and a counter sub-circuit 132-4; the energy storage sub-circuit 132-1 is coupled to the resistive random access memory 110 and configured to store energy by using a current output by a source line terminal SL of the resistive random access memory 110 to obtain an energy storage voltage; the comparison sub-circuit 132-2 is coupled to the storage sub-circuit 132-1, and configured to compare the storage voltage with a reference voltage to obtain a voltage comparison result; the clock pulse generation sub-circuit 132-3 is configured to generate a clock pulse; the counting sub-circuit 132-4 is coupled to the comparing sub-circuit 132-2 and the clock pulse generating sub-circuit 132-3, and is configured to count the clock pulses, and stop counting and output a current count value as the energy storage speed in response to the voltage comparison result indicating that the energy storage voltage exceeds the reference voltage.
For example, fig. 7 is a schematic diagram of one example of a random number generator provided in at least one embodiment of the present disclosure. In the example shown in FIG. 7, the storage sub-circuit 132-1 may be implemented as a capacitor C (it should be noted that the storage sub-circuit 132-1 may include one or more capacitors), the comparison sub-circuit 132-2 may be implemented as a comparator, and the counting sub-circuit 132-4 may be implemented as a counter. As shown in fig. 7, a control voltage is applied to the word line terminal WL of the resistance change memory and a read voltage is applied to the bit line terminal BL of the resistance change memory to control the source line terminal SL of the resistance change memory to output a current. The current charges capacitor C, causing the stored energy voltage (i.e., the voltage at node 1) to gradually rise. The comparator compares the tank voltage with a reference voltage, and when the tank voltage exceeds the reference voltage, the output voltage comparison result (i.e., the signal at node 2) of the comparator is inverted, for example, from a positive supply voltage to a negative supply voltage (e.g., 0V). A clock signal end CLK of the counter receives clock pulses, an enable end EN of the counter receives a voltage comparison result, and the clock pulses are counted in response to the voltage comparison result being a positive power supply voltage; and stops counting in response to the voltage comparison result being a negative power supply voltage and outputs a current count value as the energy storage speed. For example, the pulse width of the read voltage and the control voltage is 1us, the read voltage is 0.2V, the control voltage is 5.0V, the capacitance value of the capacitor C is 10pF, the reference voltage is 0.1V, and the frequency of the clock pulse is 300 MHz.
For example, in the random number generator provided in at least one embodiment of the present disclosure, the output sub-circuit 133 is configured to operate on the current count value to obtain an intermediate number, and generate a random number according to the intermediate number. For example, the operation includes modulo-2LOperation, the intermediate number is a random number and the intermediate number is 2LCarry the number, L is a positive integer. For example, in some embodiments, L is 1, i.e., the operation comprises a modulo-2 operation, with the intermediate number being a 2-ary number, e.g., the output sub-circuit 133 performs a modulo-2 operation on the current count value to obtain an intermediate number of 0 or 1, with the intermediate number of 0 or 1 being a random number in 2-ary form. For example, in some embodiments, L is 2, i.e., the operation comprises a modulo-4 operation, the intermediate number being a 4-ary number, e.g., the output sub-circuit 133 modulo-4 operates on the current count value to obtain the intermediate number 0, 1, 2, or 3, the intermediate number 0, 1, 2, or 3 being a random number in 4-ary form.
For example, in the random number generator provided in at least one embodiment of the present disclosure, the counting sub-circuit 132-4 includes a 1-bit counter (i.e., a 1-bit counter), the 1-bit counter is configured to output a 1-bit 2-ary number as the current count value, and the output sub-circuit 133 is configured to output the current count value as the random number.
For example, fig. 8 illustrates a schematic diagram of random numbers generated by a random number generator provided by at least one embodiment of the present disclosure. Fig. 8 shows a random number array obtained by simultaneously performing the above resistance value disturbance operation on a plurality of resistive random access memories, and fig. 8 shows a random number of 100k bits, where a black dot represents 1 and a white dot represents 0. As shown in fig. 8, the black dots and white dots are uniformly distributed, that is, the random numbers generated by the random number generator provided by the embodiment of the present disclosure have good randomness.
For example, fig. 9 is a schematic block diagram of another example of a random number generator provided by at least one embodiment of the present disclosure. As shown in fig. 9, the encoding circuit 230 includes a voltage-applying sub-circuit 231, an analog-to-digital conversion sub-circuit 232, and an output sub-circuit 233. The voltage applying sub-circuit 231 is coupled to the resistive random access memory 210 and configured to apply a control voltage to a word line end of the resistive random access memory 210 and a read voltage to a bit line end of the resistive random access memory 210 to control a source line end output current of the resistive random access memory 210; the analog-to-digital conversion sub-circuit 232 is coupled to the resistive random access memory 210 and configured to convert a current output from a source line end of the resistive random access memory 210 into a digital signal value; the output sub-circuit 233 is coupled to the analog-to-digital conversion sub-circuit 232 and configured to generate a random number from the digital signal value. In this example, different perturbed resistance values will result in different currents, and different currents will result in different digital signal values, thereby generating different random numbers.
For example, fig. 10 is a schematic diagram of another example of a random number generator provided in at least one embodiment of the present disclosure. As shown in fig. 10, the analog-to-digital conversion sub-circuit 232 may be implemented as a high-precision analog-to-digital converter. In the example shown in fig. 10, a control voltage is applied to the word line end WL of the resistance change memory and a read voltage is applied to the bit line end BL of the resistance change memory to control the source line end output current of the resistance change memory. A high precision analog to digital converter converts the current into a multi-bit 2-ary digital signal value represented in 2-ary form. For example, the pulse width of the read voltage and the control voltage is 1us, the read voltage is 0.2V, and the control voltage is 5.0V.
For example, the output sub-circuit 233 is configured to operate on the digital signal value to obtain an intermediate number, and generate a random number from the intermediate number. For example, the operation includes modulo-2LOperation, the intermediate number is a random number and the intermediate number is 2LCarry the number, L is a positive integer. For example, in some embodiments, L is 1, i.e., the operation comprises a modulo-2 operation, and the intermediate number is a 2-ary number, i.e., the output sub-circuit 233 performs a modulo-2 operation on the digital signal value to obtain the intermediate number 0 or 1, the intermediate number 0 or 1 being a random number in 2-ary form. For example, in some embodiments, L is 2, i.e., the operation includes a modulo-4 operation, and the intermediate number is a 4-ary number, i.e., the output sub-circuit 233 pairs the digital signalsThe value is modulo-4, and an intermediate number of 0, 1, 2 or 3 is obtained, the intermediate number of 0, 1, 2 or 3 being a random number in 4-ary form.
For example, in some embodiments, output subcircuit 233 includes a register configured to register a digital signal value with the lowest L bits of the digital signal value as an intermediate number. For example, as shown in fig. 10, the register is an N-bit register, and N is a positive integer equal to or greater than L. In this embodiment, the process of registering the digital signal value in the register and using the lowest L bit of the digital signal value as the middle number is equivalent to the modulo-2 processLAnd (6) operation.
For example, at least one embodiment of the present disclosure provides that the random number generator further includes a control circuit, which is coupled to the resistance value perturbation circuit and the encoding circuit, and configured to control the resistance value perturbation circuit and the encoding circuit to generate a predetermined number of random numbers. For example, in the case where the random number generator includes one resistance change memory, the control circuit is configured to control the resistance value disturbance circuit and the encoding circuit to repeatedly perform the corresponding resistance value disturbance operation on the resistance change memory to generate a predetermined number of random numbers. For example, in the case where the random number generator includes a plurality of resistive random access memories, the control circuit is configured to control the resistance value disturbance circuit and the encoding circuit to repeatedly perform the corresponding resistance value disturbance operation on one of the plurality of resistive random access memories to generate a predetermined number of random numbers, or the control circuit is configured to control the resistance value disturbance circuit and the encoding circuit to repeatedly perform the corresponding resistance value disturbance operation on the plurality of resistive random access memories to generate a predetermined number of random numbers.
For example, the control circuitry may be implemented in software, hardware, firmware, or any combination thereof. In some embodiments, the control circuitry includes code and programs stored in memory; the processor may execute the code and programs to implement some or all of the functionality of the control circuitry as described above, which in some embodiments may be dedicated hardware devices to implement some or all of the functionality of the control circuitry as described above.
In the random number generator provided by the embodiment of the disclosure, the random number generator applies perturbation to the resistive random access memory to cause the resistance value of the resistive random access memory to fluctuate randomly, and directly encodes the resistance value of the resistive random access memory to generate a random number. Since the resistance value of the resistive random access memory can be autonomously controlled below a specific range (e.g., 100k Ω), the random number encoding can be completed in a very short time (e.g., 1 μ sec), and thus the random number generator can operate at a high speed (i.e., a speed ≧ 1 Mbit/s); in addition, the random number generator can realize self calibration by utilizing the nonlinearity of the resistive random access memory without an additional calibration circuit, so that the random number generator is simple in design and very suitable for large-scale parallel; finally, under the operating condition of a small voltage, the characteristics of the resistive random access memory are slightly influenced by the environment and the self durability (namely, endiance), so that the random number generator provided by the embodiment of the disclosure has high reliability.
At least one embodiment of the present disclosure further provides a method for generating a random number, which may be used in the random number generator 100 provided in the embodiments of the present disclosure, and fig. 11 is a flowchart of the method for generating a random number. As shown in fig. 11, the random number generation method includes steps S310 and S320.
Step S310: executing n resistance value disturbance operations on the first resistive random access memory to disturb the resistance value of the first resistive random access memory so that the resistance value of the first resistive random access memory becomes a disturbed first resistance value, wherein each resistance value disturbance operation in the n resistance value disturbance operations comprises a setting operation and a resetting operation of the first resistive random access memory, and n is a positive integer;
step S320: the first perturbed resistance value of the first resistive random access memory is encoded to generate a first random number.
For example, in at least one embodiment of the present disclosure, a method is provided, in which each of the n resistance perturbation operations includes: the reset operation is performed on the first resistance change memory, and the set operation is performed on the first resistance change memory on which the reset operation is performed, so as to disturb the resistance value of the first resistance change memory.
For example, in a method provided in at least one embodiment of the present disclosure, performing a set operation includes: applying a set pulse to the first resistive random access memory; performing a reset operation includes: and applying a reset pulse to the first resistive random access memory.
For example, in a method provided by at least one embodiment of the present disclosure, performing n resistance value perturbation operations on a first resistive random access memory to perturb a resistance value of the first resistive random access memory so that the resistance value of the first resistive random access memory becomes a first perturbed resistance value includes: and executing n resistance value disturbance operations on the first resistive random access memory so that the disturbed resistance value of the first resistive random access memory is in the resistance value symmetric region.
For example, fig. 12 is a flowchart of an example of a method for generating a random number according to at least one embodiment of the present disclosure. In this example, encoding the first disturbed resistance value of the first resistance change memory to generate a first random number includes steps S321, S322, and S323.
S321: applying a control voltage to a word line end of the first resistive random access memory and applying a read voltage to a bit line end of the first resistive random access memory to control a source line end output current of the first resistive random access memory;
s322: storing energy by using the current output by the source line end of the first resistive random access memory to measure and output the energy storage speed;
s323: and generating a first random number according to the energy storage speed.
For example, in a method provided by at least one embodiment of the present disclosure, storing energy by using a current output from a source line terminal of a first resistive random access memory to measure and output an energy storage speed includes: storing energy by using current output by a source line end of the first resistive random access memory to obtain energy storage voltage; comparing the stored energy voltage with a reference voltage to obtain a voltage comparison result; generating a clock pulse; and counting the clock pulses, stopping counting in response to the voltage comparison result indicating that the energy storage voltage exceeds the reference voltage, and outputting the current count value as the energy storage speed.
For example, in at least one embodiment of the present disclosure, a method for generating a first random number according to an energy storage speed includes: and operating the current counting value to obtain an intermediate number, and generating a first random number according to the intermediate number. For example, the operation includes modulo-2LOperation with intermediate numbers asRandom number and an intermediate number of 2LCarry the number, L is a positive integer.
For example, in a method provided by at least one embodiment of the present disclosure, encoding a first disturbed resistance value of a first resistive random access memory to generate a first random number includes: applying a control voltage to a word line end of the first resistive random access memory and applying a read voltage to a bit line end of the first resistive random access memory to control a source line end output current of the first resistive random access memory; converting a current output by a source line end of the first resistive random access memory into a digital signal value; a first random number is generated based on the digital signal value.
For example, in at least one embodiment of the present disclosure, a method for generating a first random number according to a digital signal value includes: the digital signal value is operated to obtain an intermediate number, and a first random number is generated according to the intermediate number. For example, the operation includes modulo-2LOperation, the intermediate number is a random number and the intermediate number is 2LCarry the number, L is a positive integer.
For example, the method provided by at least one embodiment of the present disclosure further includes: performing m1 resistance value disturbance operations on the second resistive random access memory to disturb the resistance value of the second resistive random access memory so that the resistance value of the second resistive random access memory becomes a second disturbed resistance value, wherein each resistance value disturbance operation in the m1 resistance value disturbance operations comprises performing a set operation and a reset operation on the second resistive random access memory, the first resistive random access memory and the second resistive random access memory are different, and m1 is a positive integer; and encoding the second disturbed resistance value of the second resistive random access memory to generate a second random number. That is, in the embodiment of the present disclosure, the resistance perturbation operation may be performed on different resistive random access memories to generate a plurality of random numbers.
For example, the method provided by at least one embodiment of the present disclosure further includes: performing m2 resistance value disturbance operations on the first resistive random access memory to disturb the resistance value of the first resistive random access memory so that the resistance value of the first resistive random access memory becomes a third disturbed resistance value, wherein each of the m2 resistance value disturbance operations includes performing a set operation and a reset operation on the first resistive random access memory, and m2 is a positive integer; encoding the third disturbed resistance value of the first resistive random access memory to generate a third random number. That is, in the embodiment of the present disclosure, the resistance perturbation operation may be repeatedly performed on the same resistive random access memory to generate a plurality of random numbers.
For example, in some embodiments, n, m1, and m2 may be the same (e.g., each is 1), and n, m1, and m2 may also be different from each other. n, m1 and m2 can be set according to actual conditions.
For example, the first random number and the second random number may collectively constitute a sequence of random numbers, and the first random number and the third random number may collectively constitute a sequence of random numbers.
For example, in a method provided in at least one embodiment of the present disclosure, the first disturbed resistance value and the third disturbed resistance value are different. For example, the first disturbed resistance value and the second disturbed resistance value may also be different. However, the disclosure is not limited thereto, and any two of the first disturbed resistance value, the second disturbed resistance value, and the third disturbed resistance value may be the same, or the first disturbed resistance value, the second disturbed resistance value, and the third disturbed resistance value may all be the same.
For technical effects of the random number generation method in different embodiments, reference may be made to the technical effects of the random number generator provided in the embodiments of the present disclosure, and details are not described here.
The following points need to be explained:
(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to the common design.
(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.
The above description is intended to be exemplary of the present disclosure, and not to limit the scope of the present disclosure, which is defined by the claims appended hereto.
Claims (10)
1. A random number generator, comprising:
a resistive random access memory;
a resistance value perturbation circuit, coupled to the resistive random access memory, configured to perform n resistance value perturbation operations on the resistive random access memory to perturb a resistance value of the resistive random access memory so that the resistance value of the resistive random access memory becomes a perturbed resistance value, wherein each of the n resistance value perturbation operations includes performing a set operation and a reset operation on the resistive random access memory, where n is a positive integer;
an encoding circuit coupled to the resistive random access memory and configured to encode the perturbed resistance value of the resistive random access memory to generate a random number.
2. The random number generator according to claim 1, wherein, when a resistance value perturbation operation is performed once, the resistance value perturbation circuit is configured to perform the reset operation on the resistance change memory and perform the set operation on the resistance change memory on which the reset operation is performed to perturb a resistance value of the resistance change memory.
3. The random number generator of claim 1, wherein the resistance perturbation circuit comprises a set operation sub-circuit and a reset operation sub-circuit; wherein the content of the first and second substances,
the setting operation sub-circuit is configured to apply a setting pulse to the resistive random access memory to perform the setting operation;
the reset operation sub-circuit is configured to apply a reset pulse to the resistive random access memory to perform the reset operation.
4. The random number generator according to claim 1, wherein the resistance value perturbation circuit is configured to perform the n resistance value perturbation operations on the resistive random access memory so that a perturbed resistance value of the resistive random access memory is in a resistance value symmetric region.
5. The random number generator of any of claims 1-4, wherein the encoding circuit comprises a voltage application sub-circuit, a speed measurement sub-circuit, and an output sub-circuit; wherein the content of the first and second substances,
the voltage applying sub-circuit is coupled to the resistive random access memory and configured to apply a control voltage to a word line end of the resistive random access memory and apply a read voltage to a bit line end of the resistive random access memory to control a source line end output current of the resistive random access memory;
the speed measuring sub-circuit is coupled to the resistive random access memory and is configured to measure and output an energy storage speed under the condition of storing energy by using the current output by a source line end of the resistive random access memory;
the output sub-circuit is coupled to the speed measurement sub-circuit and configured to generate the random number according to the energy storage speed.
6. The random number generator of claim 5, wherein the speed measurement sub-circuit comprises a tank sub-circuit, a comparator sub-circuit, a clock generation sub-circuit, and a counter sub-circuit; wherein the content of the first and second substances,
the energy storage sub-circuit is coupled to the resistive random access memory and configured to store energy by using the current output by a source line end of the resistive random access memory to obtain an energy storage voltage;
the comparison sub-circuit is coupled to the energy storage sub-circuit and configured to compare the energy storage voltage with a reference voltage to obtain a voltage comparison result;
the clock pulse generation sub-circuit is configured to generate clock pulses;
the counting sub-circuit is coupled to the comparing sub-circuit and the clock pulse generating sub-circuit, and is configured to count the clock pulses, and stop counting and output a current count value as the energy storage speed in response to the voltage comparison result indicating that the energy storage voltage exceeds the reference voltage.
7. The random number generator of any of claims 1-4, wherein the encoding circuit comprises a voltage multiplier sub-circuit, an analog-to-digital conversion sub-circuit, and an output sub-circuit; wherein the content of the first and second substances,
the voltage applying sub-circuit is coupled to the resistive random access memory and configured to apply a control voltage to a word line end of the resistive random access memory and apply a read voltage to a bit line end of the resistive random access memory to control a source line end output current of the resistive random access memory;
the analog-to-digital conversion sub-circuit is coupled to the resistive random access memory and configured to convert the current output by a source line end of the resistive random access memory into a digital signal value;
the output sub-circuit is coupled to the analog-to-digital conversion sub-circuit and configured to generate the random number according to the digital signal value.
8. A method of generating random numbers, comprising:
executing n resistance value disturbance operations on a first resistive random access memory to disturb the resistance value of the first resistive random access memory so that the resistance value of the first resistive random access memory becomes a disturbed resistance value, wherein each resistance value disturbance operation of the n resistance value disturbance operations comprises executing a set operation and a reset operation on the first resistive random access memory, and n is a positive integer;
encoding a first perturbed resistance value of the first resistive random access memory to generate a first random number.
9. The method of claim 8, wherein encoding the perturbed first resistance value of the first resistive-switching memory to generate a first random number comprises:
applying a control voltage to a word line end of the first resistive random access memory and applying a read voltage to a bit line end of the first resistive random access memory to control a source line end of the first resistive random access memory to output current;
storing energy by using the current output by the source line end of the first resistive random access memory to measure and output an energy storage speed;
and generating the first random number according to the energy storage speed.
10. The method of claim 9, wherein storing energy with the current output by a source line terminal of the first resistive random access memory to measure and output an energy storage speed comprises:
storing energy by using the current output by the source line end of the first resistive random access memory to obtain an energy storage voltage;
comparing the energy storage voltage with a reference voltage to obtain a voltage comparison result;
generating a clock pulse;
counting the clock pulses, stopping counting in response to the voltage comparison result indicating that the energy storage voltage exceeds the reference voltage, and outputting a current count value as the energy storage speed.
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| CN112650472A (en) * | 2020-12-15 | 2021-04-13 | 中国科学院上海微系统与信息技术研究所 | Device for constructing pseudo spin |
| WO2023155240A1 (en) * | 2022-02-15 | 2023-08-24 | 清华大学 | Random number generator, electronic device, and operating method |
| CN116126288A (en) * | 2023-01-04 | 2023-05-16 | 北京大学 | Random number generation circuit and method based on resistive random access memory |
| CN116126288B (en) * | 2023-01-04 | 2023-12-01 | 北京大学 | Random number generation circuit and method based on resistive random access memory |
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