CN116126231A - Storage device, storage system, and writing method for storage device - Google Patents
Storage device, storage system, and writing method for storage device Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The application relates to a storage device, a storage system and a writing method of the storage device, wherein the storage device comprises a front-end module, a back-end module, a cache module, a storage medium and a processor; the cache module is connected with the front end module, the processor and the rear end module, and the rear end module is connected with the processor and the storage medium; the cache module comprises a cache management unit, a first cache and a second cache, wherein the capacity of the second cache is larger than or equal to that of the first cache, and the reading and writing speed of the second cache is smaller than that of the first cache; the front-end module transmits data to be written to the first cache; the buffer management unit controls the first buffer and the second buffer to transfer the data to be written into each other; and the back-end module writes the target data to be written into the storage medium through the first cache. The first cache with high reading and writing speed, the front end module and the rear end module form a writing passage, the delay is less, the second cache with large use capacity and the first cache are used for carrying out data mutual transfer so as to increase cache data, and the writing performance is effectively improved.
Description
Technical Field
The present disclosure relates to the field of storage devices, and in particular, to a storage device, a storage system, and a writing method of the storage device.
Background
In the design of a storage device such as a solid state disk SSD, data to be written from a host is written into a memory of the solid state disk through a controller or a processor of the solid state disk, and then the written data is written into a storage medium such as flash memory particles of the solid state disk from the memory, so that the function of data storage is achieved. Because the prior art generally directly carries out read-write access to the memory, and the read-write speed of the memory is slower, the delay of each module of the solid state disk for directly reading and writing the memory is high, the scheduling of the solid state disk controller is occupied, and the influence on the writing performance is large.
Disclosure of Invention
Aiming at the technical problems, the application provides a storage device, a storage system and a writing method of the storage device, wherein a first cache with high reading and writing speed, a front-end module and a back-end module are used for forming a writing path, time delay is low, and a second cache with high capacity and the first cache are used for carrying out data mutual transfer so as to increase cache data, so that writing performance is effectively improved.
In order to solve the technical problems, the application provides a storage device, which comprises a front end module, a back end module, a cache module, a storage medium and a processor; the cache module is connected with the front end module, the processor and the back end module, and the back end module is connected with the processor and the storage medium; the buffer memory module comprises a buffer memory management unit, a first buffer memory and a second buffer memory, wherein the capacity of the second buffer memory is larger than or equal to that of the first buffer memory, and the read-write speed of the second buffer memory is smaller than that of the first buffer memory;
the front-end module is used for transmitting data to be written into the first cache;
the cache management unit is used for controlling the first cache and the second cache to transfer the data to be written into each other according to a preset strategy;
and the back-end module is used for writing the target data to be written into the storage medium through the first cache.
Optionally, software is solidified in the processor, and the front-end module is connected with the source equipment end of the data to be written and the processor;
the front-end module sends the write command of the source equipment end to the processor;
the processor establishes a new cache management node after receiving the write command, and sends a data transmission instruction to the front-end module;
and the front-end module transmits the data to be written acquired from the source equipment end to the first cache according to the data transmission instruction.
Optionally, the preset policy includes at least one of the following:
transferring the data to be written with high priority in the second cache to the first cache;
transferring the low-priority data to be written in the first cache to the second cache;
transferring the latest written data to be written into the second cache;
transferring the target data to be written into the first cache;
when the storage state of the first cache reaches a preset maximum threshold, transferring a part of data to be written in the first cache to the second cache;
and when the storage state of the first cache reaches a preset minimum threshold, transferring a part of data to be written in the second cache to the first cache.
Optionally, the cache management unit is further configured to:
and responding to the writing instruction sent by the back-end module, and locking target data to be written in the first cache and/or the second cache, which correspond to the writing instruction, in the first cache.
Optionally, the priority of the data to be written in the first buffer is not lower than the priority of the data to be written in the second buffer, and the buffer management unit is configured to set the target data to be written to the highest priority, so as to lock in the first buffer.
Optionally, the cache management unit is further configured to:
and after locking target data to be written corresponding to the writing instruction in the first cache and/or the second cache in the first cache, responding to a data transmission instruction of the back-end module, and transmitting the target data to be written to the back-end module through the first cache.
Optionally, the back-end module is configured to send a data release instruction to the cache management unit and send a successful write signal to the processor after the target data to be written is successfully written into the storage medium;
and the processor is used for processing the software resource of the target data to be written according to the successful writing signal.
Optionally, the cache management unit is a hardware module.
The application also provides a storage system, which comprises a host and the storage device according to any one of the above, wherein the host is used for providing the data to be written to a front-end module of the storage device.
The application also provides a writing method of the storage device, which is applied to any storage device, and the method comprises the following steps:
transmitting data to be written into a first cache;
controlling the first buffer memory and the second buffer memory to transfer the data to be written into according to a preset strategy, wherein the capacity of the second buffer memory is larger than that of the first buffer memory, and the reading and writing speed of the second buffer memory is smaller than that of the first buffer memory;
and responding to the writing instruction, and writing the target data to be written into the storage medium through the first cache.
The storage device, the storage system and the writing method of the storage device comprise a front-end module, a back-end module, a cache module, a storage medium and a processor; the cache module is connected with the front end module, the processor and the rear end module, and the rear end module is connected with the processor and the storage medium; the cache module comprises a cache management unit, a first cache and a second cache, wherein the capacity of the second cache is larger than or equal to that of the first cache, and the reading and writing speed of the second cache is smaller than that of the first cache; the front-end module transmits data to be written to the first cache; the buffer management unit controls the first buffer and the second buffer to transfer the data to be written into each other; and the back-end module writes the target data to be written into the storage medium through the first cache. The writing method of the storage device comprises the following steps: transmitting data to be written into a first cache; controlling the first buffer memory and the second buffer memory to transfer the data to be written into each other according to a preset strategy, wherein the capacity of the second buffer memory is larger than that of the first buffer memory, and the reading and writing speed of the second buffer memory is smaller than that of the first buffer memory; and responding to the writing instruction, and writing the target data to be written into the flash grains through the first cache. The first cache with high reading and writing speed, the front end module and the rear end module form a writing passage, the delay is less, and the second cache with large use capacity and the first cache are used for carrying out data mutual transfer so as to increase cache data, thereby effectively improving writing performance.
Drawings
FIG. 1 is a schematic diagram of a memory device shown according to one embodiment;
FIG. 2 is a schematic diagram of a write process of a memory device according to one embodiment;
FIG. 3 is a schematic diagram of a storage system shown according to one embodiment;
fig. 4 is a flow chart illustrating a writing method of a memory device according to an embodiment.
Detailed Description
In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. The drawings illustrate preferred embodiments of the invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items. In the present invention, "each" includes one and two or more numbers.
FIG. 1 is a schematic diagram of a memory device, according to one embodiment. As shown in fig. 1, the storage device of the present application includes a front-end module 1, a back-end module 2, a cache module 3, a storage medium 4, and a processor 5. The cache module 3 is connected with the front-end module 1, the processor 5 and the back-end module 2, and the back-end module 2 is connected with the processor 5 and the storage medium 4. The buffer module 3 includes a buffer management unit 31, a first buffer 32 and a second buffer 33, the capacity of the second buffer 33 is greater than that of the first buffer 32, and the read-write speed of the second buffer 33 is less than that of the first buffer 32.
The front-end module 1 is configured to transmit data to be written to the first buffer 32. The buffer management unit 31 is configured to control the first buffer 32 and the second buffer 33 to transfer the data to be written to each other according to a preset policy. The back-end module 2 is configured to write target data to be written into the storage medium 4 through the first buffer 32.
Through the above manner, the first buffer 32 with high reading and writing speed, the front end module 1 and the back end module 2 form a writing path, the delay is less, and the second buffer 33 with large capacity and the first buffer 32 are used for carrying out data mutual transfer so as to increase the buffer data, thereby effectively improving the writing performance. In addition, the design of the application enables the storage device to reply to the host to complete writing state earlier, and improves writing performance under the condition of single writing command or small data volume.
Wherein the storage medium 4 is a NAND flash memory granule; the target data to be written is data to be written down from the first cache 32 into the storage medium 4. The front end module 1, the back end module 2 and the buffer memory management unit 31 can be integrated in a processor such as a controller Chip, for example, integrated in a form of a System on Chip (SoC), and then connected with the first buffer memory 32, the second buffer memory 33 and the storage medium 4 through corresponding interfaces; the front-end module 1 may be PCIe interface supported and NVMe protocol, and communicates with the host through the front-end module 1, and communicates with the storage medium through the back-end module 2. Alternatively, the first buffer 32 may be a Static Random-Access Memory (SRAM), which has a small capacity and a fast read/write speed. The first buffer 32 may be a Double Data Rate (DDR) dram, which has a large capacity and a slower read/write speed than the SRAM. The selection of the two memories can achieve a more comprehensive optimization between total capacity, read-write speed and cost.
Optionally, software is solidified in the processor 5, and the front-end module 1 connects the source device side of the data to be written with the processor 5. The front-end module 1 sends a write command from the source device side to the processor 5. After receiving the write command, the processor 5 creates a new cache management node and sends a data transmission instruction to the front-end module 1. The front-end module 1 is configured to transmit data to be written to the first buffer 32, and it can be understood that, according to a data transmission instruction, the front-end module 1 transmits the data to be written obtained from the source device side to the first buffer 32 and writes the data into the first buffer 32, and receives successful writing information sent by the buffer management unit 31, and sends the successful writing information to the processor 5 and the source device side. The source device side to be written with data is, for example, a host. In this way, in the front-end module 1, the operation of writing data is executed by the logic of the solidified software (also referred to as firmware) in the processor 5, and has the function of performing signal interaction transmission writing state, so that the participation of the software in data writing is avoided or reduced, the software overhead is further reduced, the scheduling occupation degree of the storage device controller is lower, and the writing performance is improved.
Optionally, the preset policy used by the cache management unit 31 includes at least one of the following:
transferring the data to be written with high priority in the second buffer memory to the first buffer memory 32;
transferring the low priority data to be written in the first buffer memory to the second buffer memory 33
Transferring the latest written data to be written to the second buffer memory 33;
transferring the target data to be written into the first cache;
when the storage state of the first cache 32 reaches a preset maximum threshold, transferring a part of data to be written in the first cache 32 to the second cache 33;
when the storage state of the first cache 32 reaches the preset minimum threshold, a part of data to be written in the second cache 33 is transferred to the first cache 32.
The priority of the data to be written may be given by the front-end module 1 or by the source device, and the data to be written may be divided into a high priority, a medium priority and a low priority with sequentially reduced priorities. The first buffer 32 preferentially stores the data to be written with higher priority, so as to improve the utilization rate of the first buffer 32, and the second buffer 33 preferentially stores the data to be written with lower priority, so as to fully utilize the storage capacity of the second buffer 33. For the newly written data to be written, the read data is generally extracted in time order from the first buffer 32 based on the back end, and thus can be written preferentially in the second buffer 33. For transferring the target data to be written to the first buffer memory 32, the target data to be written in the second buffer memory 33 is written in the first buffer memory 32 in response to a writing instruction sent by the back-end module 2, so that the back-end module 2 can write the target data to be written into the storage medium 4 from the first buffer memory 32 in a down-flushing mode. In addition, data transfer may also be performed between the first buffer 32 and the second buffer 33 according to the storage state of the first buffer 32, for example, when the storage state of the first buffer 32 reaches a preset maximum threshold, a portion of data to be written, which is not the highest priority and is written at the latest, in the first buffer 32 is transferred to the second buffer 33 until the storage state of the first buffer 32 reaches a preset centering threshold, where the preset centering threshold is greater than a preset minimum threshold and less than the preset maximum threshold. It is also possible to transfer a part of the data to be written in the second buffer 33 to the first buffer 32 when the storage state of the first buffer 32 reaches the preset minimum threshold, for example, when the storage state of the first buffer 32 reaches the preset minimum threshold, transfer a part of the data to be written in the second buffer 33 with higher priority and earlier writing time to the first buffer 32 until the storage state of the first buffer 32 reaches the preset centering threshold. By the above strategy, the automatic movement of the data to be written between the first buffer 32 and the second buffer 33 can be realized, and the utilization rate of the first buffer 32 and the second buffer 33 can be dynamically ensured.
Optionally, the cache management unit 31 is further configured to: in response to the write instruction sent by the back-end module 2, the target data to be written corresponding to the write instruction in the first cache 32 and/or the second cache 33 is locked in the first cache 32.
When the back-end module 2 needs to extract the data to be written, the write instruction informs the cache management unit 31 of the logical address of the data to be written to the storage medium 4, and the cache management unit 31 locks the target data to be written corresponding to the write instruction in the first cache 32 and/or the second cache 33. If the target data to be written is stored in the first buffer 32, the target data to be written is not transferred any more, and if the target data to be written is stored in the second buffer 33, the target data to be written is transferred to the first buffer 32 for waiting.
Alternatively, the priority of the data to be written in the first buffer 32 is not lower than the priority of the data to be written in the second buffer 33, and the buffer management unit 31 is configured to set the target data to be written to the highest priority to lock in the first buffer 32. Based on the above-mentioned preset policy, the target data to be written may be locked in the first cache 32 by setting the target data to be written to the highest priority, so as to ensure that the target data to be written will not be transferred before being read, thereby realizing the locking effect.
Optionally, the cache management unit 31 is further configured to: after locking the target data to be written corresponding to the write instruction in the first cache 32 and/or the second cache 33 in the first cache 32, the target data to be written is transferred to the back-end module 2 through the first cache 32 in response to the data transfer instruction of the back-end module 2. The buffer management unit 31 transfers the target data to be written into the first buffer 32 in advance, waits for receiving the data transmission instruction of the back-end module 2, and then transfers the target data to be written into the back-end module 2 through the first buffer 32, so as to realize the asynchronous prefetching function between the target data to be written, and in the process of writing the previous data into the storage medium 4, the step of transferring the next data into the first buffer 32 is completed, so that the data to be written flows between the first buffer 32 and the second buffer 33, thereby counteracting or reducing the read-write delay caused by the slower read-write speed of the second buffer 33. In addition, according to the preset policy, it can be ensured that new data transmitted by the host and data to be written into the storage medium 4 are stored in the first buffer 32 preferentially, but not temporarily stored in the second buffer 33, so that the reasonable utilization of the memory space is realized, different reading and writing capacities of the memory are exerted, and the writing performance is improved.
Alternatively, the cache management unit 31 is a hardware module. Therefore, the management of the first cache 32 and the second cache 33 can be performed based on logic of software, so that the participation of the software in the processor 5 in data writing is avoided or reduced, the software overhead is further reduced, the scheduling occupation degree of the storage device controller is lower, and the writing performance is improved.
Optionally, the back-end module 2 is connected between the processor 5 and the storage medium 4. The back-end module 2 is configured to send a data release instruction to the cache management unit 31 and send a successful write signal to the processor 5 after the target data to be written is successfully written to the storage medium 4. And the processor 5 is used for processing the software resource of the target data to be written according to the successful write signal. The cache management unit 31 is configured to release the corresponding space of the target data to be written according to the data release instruction, and return a release completion status to the back-end module 2. In this way, in the back-end module 2, the operation of reading and writing data is executed by the logic of the back-end module 2, and the function of performing signal interaction transmission writing state is provided, so that the participation of software in data writing is avoided or reduced, the software overhead is further reduced, the scheduling occupation degree of a storage device controller is lower, and the writing performance is improved.
The writing process of the memory device of the present application will be described in detail. Referring to fig. 2, numbers (1) - (5) represent command streams, numbers a-f represent data streams, and the writing process is as follows:
the host sends a write command (corresponding to command stream (1)) to the storage device;
the front-end module of the storage device informs the software (corresponding to the command stream (2)) after receiving the write command, and the software is solidified in the processor;
after receiving the write command, the software builds a buffer management node and informs the front-end module to start data transmission (corresponding to the command stream (2));
the front-end module moves the write data of the host from the host end to a first buffer memory (corresponding to data streams a and b);
the cache management unit returns the successfully written state to the front-end module (corresponding to the command stream (3));
the front-end module transmits the information to software (corresponding to the command stream (2)) after receiving the information successfully written by the cache management unit;
the front-end module returns the information of successful writing of the data to the host end (corresponding to the command stream (1)) at the same time, so that the writing command is completed for the host end;
after receiving the write data, the buffer memory management unit automatically transfers the data to the second buffer memory according to the priority of the data and the storage state of the first buffer memory, and realizes the mutual transfer of the data between the first buffer memory and the second buffer memory (corresponding to data streams e and f) according to the priority of the data and the storage condition of the first buffer memory;
when the back-end module initiates a writing instruction and data of the buffer memory module is to be written into the storage medium, the buffer memory management unit moves the data which needs to be written into the storage medium into a first buffer memory (corresponding to the data stream f) in advance;
the software initiates a writing instruction to the back-end module, and the cache data is required to be written into a storage medium (corresponding to the command stream (5));
the back-end module transmits the write instruction to a cache management unit (corresponding to the command stream (4));
the buffer management unit transmits data which needs to be written into a storage medium such as flash particles from the first buffer to the back-end module (corresponding to data streams e and c);
the back-end module writes the data transmitted by the cache management unit into a storage medium (corresponding to the data stream d);
after the data of the back-end module is successfully written, informing a cache management unit to release the cache data, and after the cache management unit releases the written cache data, informing the back-end module (corresponding to the command stream (4));
the back-end module returns information of the write success to the software, which releases the software resources associated with the write data (corresponding to command stream (5)).
According to the test result, compared with the traditional mode, the end-to-end writing performance of the storage device can be improved by nearly 50% under the condition of main frequency limitation, and the writing performance of the storage device is greatly improved.
The storage device, the storage system and the writing method of the storage device comprise a front-end module, a back-end module, a cache module, a storage medium and a processor; the cache module is connected with the front end module, the processor and the rear end module, and the rear end module is connected with the processor and the storage medium; the cache module comprises a cache management unit, a first cache and a second cache, wherein the capacity of the second cache is larger than that of the first cache, and the reading and writing speed of the second cache is smaller than that of the first cache; the front-end module transmits data to be written to the first cache; the cache management unit controls the first cache and the second cache to transfer the data to be written in according to a preset strategy; and the back-end module writes the target data to be written into the storage medium through the first cache.
FIG. 3 is a schematic diagram of a memory system, according to one embodiment. As shown in fig. 3, the present application further provides a storage system, including a host 10 and the storage device 20 of the above embodiment, where the host 10 is configured to provide data to be written to a front-end module of the storage device 20. The writing process of the memory device 20 is described in detail above, and will not be described again here.
Fig. 4 is a flow chart illustrating a writing method of a memory device according to an embodiment. As shown in fig. 4, the writing method of the storage device of the present application is applied to the storage device described in the foregoing embodiment, and the method includes:
s1, transmitting data to be written into a first cache;
s2, controlling the first buffer memory and the second buffer memory to transfer the data to be written into each other according to a preset strategy, wherein the capacity of the second buffer memory is larger than that of the first buffer memory, and the reading and writing speed of the second buffer memory is smaller than that of the first buffer memory;
and S3, responding to the writing instruction, and writing the target data to be written into the storage medium through the first cache.
Optionally, transmitting the data to be written to the first buffer memory includes:
the front-end module sends a write command of the source equipment end to the processor;
after receiving the writing command, the processor establishes a new buffer management node and sends a data transmission instruction to the front-end module;
the front-end module acquires data to be written from the source equipment end according to the data transmission instruction, transmits the data to be written to the first cache, receives successful writing information sent by the cache management unit, and sends the successful writing information to the processor and the source equipment end.
Optionally, the preset policy includes at least one of the following:
transferring the data to be written with high priority in the second cache to the first cache;
transferring the low-priority data to be written in the first cache to the second cache
Transferring the data to be written which is written newly to a second cache;
transferring the target data to be written into the first cache;
when the storage state of the first cache reaches a preset maximum threshold, transferring a part of data to be written in the first cache to the second cache;
and when the storage state of the first cache reaches a preset minimum threshold, transferring a part of data to be written in the second cache to the first cache.
Optionally, the method further comprises:
and responding to the writing instruction, and locking target data to be written corresponding to the writing instruction in the first cache and/or the second cache in the first cache.
Optionally, the priority of the data to be written in the first buffer is not lower than the priority of the data to be written in the second buffer, and the method further includes: the target data to be written is set to the highest priority to be locked in the first cache.
Optionally, the method further comprises:
and after locking target data to be written corresponding to the writing instruction in the first cache and/or the second cache in the first cache, responding to the data transmission instruction, and transmitting the target data to be written to the back-end module through the first cache.
Optionally, the method further comprises:
the back-end module sends a data release instruction to the cache management unit and sends a successful writing signal to the processor after the target data to be written is successfully written into the storage medium;
the processor processes the software resource of the target data to be written according to the successful writing signal;
and the cache management unit releases the storage space of the target data to be written according to the data release instruction.
The specific implementation process of the above steps is described in the above embodiments, and is not described herein.
The writing method of the storage device comprises the following steps: transmitting data to be written into a first cache; controlling the first buffer memory and the second buffer memory to transfer the data to be written into each other according to a preset strategy, wherein the capacity of the second buffer memory is larger than that of the first buffer memory, and the reading and writing speed of the second buffer memory is smaller than that of the first buffer memory; and responding to the writing instruction, and writing the target data to be written into the storage medium through the first cache. The first cache with high reading and writing speed, the front end module and the rear end module form a writing passage, the delay is less, and the second cache with large use capacity and the first cache are used for carrying out data mutual transfer so as to increase cache data, thereby effectively improving writing performance.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (10)
1. The storage device is characterized by comprising a front-end module, a back-end module, a cache module, a storage medium and a processor; the cache module is connected with the front end module, the processor and the back end module, and the back end module is connected with the processor and the storage medium; the buffer memory module comprises a buffer memory management unit, a first buffer memory and a second buffer memory, wherein the capacity of the second buffer memory is larger than or equal to that of the first buffer memory, and the read-write speed of the second buffer memory is smaller than that of the first buffer memory;
the front-end module is used for transmitting data to be written into the first cache;
the cache management unit is used for controlling the first cache and the second cache to transfer the data to be written into each other according to a preset strategy;
and the back-end module is used for writing the target data to be written into the storage medium through the first cache.
2. The memory device of claim 1, wherein the processor has software cured therein, the front-end module connecting the source device side of the data to be written with the processor;
the front-end module sends the write command of the source equipment end to the processor;
the processor establishes a new cache management node after receiving the write command, and sends a data transmission instruction to the front-end module;
and the front-end module transmits the data to be written acquired from the source equipment end to the first cache according to the data transmission instruction.
3. The storage device of claim 1, wherein the preset policy comprises at least one of:
transferring the data to be written with high priority in the second cache to the first cache;
transferring the low-priority data to be written in the first cache to the second cache;
transferring the latest written data to be written into the second cache;
transferring the target data to be written into the first cache;
when the storage state of the first cache reaches a preset maximum threshold, transferring a part of data to be written in the first cache to the second cache;
and when the storage state of the first cache reaches a preset minimum threshold, transferring a part of data to be written in the second cache to the first cache.
4. The storage device of claim 1, wherein the cache management unit is further configured to:
and responding to the writing instruction sent by the back-end module, and locking target data to be written in the first cache and/or the second cache, which correspond to the writing instruction, in the first cache.
5. The storage device according to claim 4, wherein the priority of the data to be written in the first buffer is not lower than the priority of the data to be written in the second buffer, and the buffer management unit is configured to set the target data to be written to the highest priority to lock in the first buffer.
6. The storage device of claim 4, wherein the cache management unit is further configured to:
and after locking target data to be written corresponding to the writing instruction in the first cache and/or the second cache in the first cache, responding to a data transmission instruction of the back-end module, and transmitting the target data to be written to the back-end module through the first cache.
7. The storage device of claim 1, wherein the memory is configured to store the data,
the back-end module is used for sending a data release instruction to the cache management unit and sending a successful writing signal to the processor after the target data to be written is successfully written into the storage medium;
and the processor is used for processing the software resource of the target data to be written according to the successful writing signal.
8. The storage device of any of claims 1-7, wherein the cache management unit is a hardware module.
9. A storage system comprising a host and a storage device according to any one of claims 1-8, the host being configured to provide the data to be written to a front-end module of the storage device.
10. A method of writing to a memory device as claimed in any one of claims 1 to 8, the method comprising:
transmitting data to be written into a first cache;
controlling the first buffer memory and the second buffer memory to transfer the data to be written into according to a preset strategy, wherein the capacity of the second buffer memory is larger than that of the first buffer memory, and the reading and writing speed of the second buffer memory is smaller than that of the first buffer memory;
and responding to the writing instruction, and writing the target data to be written into the storage medium through the first cache.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211656113.8A CN116126231A (en) | 2022-12-22 | 2022-12-22 | Storage device, storage system, and writing method for storage device |
| PCT/CN2023/089079 WO2024130909A1 (en) | 2022-12-22 | 2023-04-18 | Storage device, storage system and method for writing into storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211656113.8A CN116126231A (en) | 2022-12-22 | 2022-12-22 | Storage device, storage system, and writing method for storage device |
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| Publication Number | Publication Date |
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| CN116126231A true CN116126231A (en) | 2023-05-16 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202211656113.8A Pending CN116126231A (en) | 2022-12-22 | 2022-12-22 | Storage device, storage system, and writing method for storage device |
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| Country | Link |
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| CN (1) | CN116126231A (en) |
| WO (1) | WO2024130909A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102117248A (en) * | 2011-03-09 | 2011-07-06 | 浪潮(北京)电子信息产业有限公司 | Caching system and method for caching data in caching system |
| CN105117180B (en) * | 2015-09-28 | 2018-08-17 | 北京联想核芯科技有限公司 | A kind of date storage method and device and solid state disk |
| US11822817B2 (en) * | 2020-07-31 | 2023-11-21 | Seagate Technology Llc | Ordering reads to limit collisions in a non-volatile memory (NVM) |
| CN112947869A (en) * | 2021-04-25 | 2021-06-11 | 联芸科技（杭州）有限公司 | Solid state disk and write operation method |
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| WO2024130909A1 (en) | 2024-06-27 |
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