CN116112087B - Driving circuit based on multi-path current segmentation delay and merging output architecture - Google Patents
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Abstract
The invention discloses a drive circuit based on a multi-path current segmentation delay and merging output framework, which is used for a transmitting end in an optical fiber communication link and comprises an input transmission network, an amplifying unit comprising N transconductance units, an output transmission network and an input matching load, wherein the input transmission network is used for receiving and correspondingly distributing signals output by an optical modulator in the transmitting end to the transconductance units according to preset delay time; the input matching load is used for absorbing the signal reflected to the optical modulator; the output transmission network is used for respectively superposing amplified current signals output by the transconductance units according to preset delay time and combining and outputting the amplified current signals, wherein the delay time between the ith port and the (i+1) th port in the input transmission network is equal to the delay time between the ith port and the (i+1) th port in the output transmission network or the delay time between the ith port and the (i+1) th port in the output transmission network is different from the delay time by an integral multiple of a signal period. The invention can effectively compromise the overall bandwidth and energy efficiency performance of the driving circuit.
Description
Technical Field
The invention belongs to the technical field of analog and radio frequency amplifiers, and particularly relates to a driving circuit based on a multi-path current segmentation delay and merging output framework.
Background
With the rapid development of high-traffic services such as 5G communication, virtual reality, edge computing and the like, optical fiber communication is used as a main force of the current wired communication backbone network, industry standards are continuously developed from 200GBE, 400GBE, 800GBE to 1.6TBE, and the transmission rate and data throughput capability of a core network are continuously updated and iterated. The driving circuit is used as the last stage circuit of the transmitting end in the optical fiber communication link, is directly connected with the optical modulator and needs to work in a full-rate mode, and the working speed of the driving circuit directly determines the upper limit of the communication speed of the transmitter; meanwhile, the driving circuit needs to provide enough signal output power, so that the energy efficiency performance of the driving circuit is also a key factor influencing the overall power consumption performance of the transmitter. Therefore, the ultra-wideband high-energy-efficiency driving circuit has important research significance.
The main architecture of the current broadband driving circuit includes a lumped open drain output architecture and a distributed architecture. As shown in fig. 1, the lumped open drain output architecture mainly comprises a single transconductance transistor for providing voltage-current conversion, and since the output node has only one branch, the signal current generated by the transistor can only flow to the output node, so that the energy efficiency theory of the driving of the architecture can reach 100%. But is subject to parasitic capacitance C caused by large-sized transistors gs ，C gd ，C ds The frequency of the main pole point is low, and the bandwidth is difficult to reach more than 100 GHz; the distributed driving architecture is shown in fig. 2, and mainly comprises an input network, an input matching load, a transconductance unit, an output network and an output matching load. The distributed architecture has the advantage of high bandwidth because of the research on the working bandwidth reaching 170GHz without being influenced by the frequency of the input/output poles. Since the output node of the distributed architecture has an additional output matching load compared to the open drain, a portion of the signal current generated by the transistor will flow to the output matching load and the remainder will flow from the output port, with a full match, half of the current will flow to the load, resulting in an energy efficiency of the distributed drive of about 50%. In summary, the two existing driving circuits have the problem of high efficiency and high bandwidth.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide a driving circuit based on a multi-path current segmentation delay and merging output architecture, which can effectively compromise the performance of the driving circuit in terms of overall bandwidth and energy efficiency.
The invention provides a driving circuit based on a multi-path current segmented delay and merging output architecture, which is used for a transmitting end in an optical fiber communication link, and comprises an input transmission network, an amplifying unit, an output transmission network and an input matching load, wherein the amplifying unit comprises N transconductance units M 1 ～M N ；
The input transmission network comprises n+1 inductors Lg which are sequentially connected in series 1 ～Lg N+1 Inductance Lg 1 ～Lg N+1 The connection points of two adjacent inductors sequentially form 1-N ports of an input transmission network, and the input transmission network is used for receiving and correspondingly distributing signals output by an optical modulator in a transmitting end to a transconductance unit M through the 1-N ports according to preset delay time 1 ～M N Amplifying, voltage and current conversion treatment is carried out;
the input is matched with a load and is used for absorbing signals reflected to the optical modulator;
the output transmission network comprises N inductors Ld which are sequentially connected in series 1 ～Ld N Inductance Ld 1 ～Ld N Sequentially forming 1-N ports of an output transmission network, wherein the output transmission network is used for respectively superposing amplified current signals output by each transconductance unit according to preset delay time and combining and outputting the amplified current signals; wherein the delay time delta Tg between the ith port and the (i+1) th port in the input transmission network i_i+1 Delay time DeltaTd with i-th and i+1-th ports in output transmission network i_i+1 Equal, or the difference between the two is an integer multiple of the period of the signal processed by the ith transconductance cell, i e (1, 2, …, N-1).
The driving circuit based on the multi-path current segmentation delay and merging output framework provided by the invention uses multi-path transconductance units to merge to form a large amplifying unit, and because each transconductance unit is a small-size circuit, the parasitic capacitance introduced is smaller, and series resonance is formed between the driving circuit and an inductive element in an input transmission network, so that the bandwidth of the circuit can be greatly expanded; the output port of the driving circuit provided by the invention adopts an open-drain design, so that the driving efficiency of the amplifier can be effectively improved, and the purpose of effectively compromising the overall bandwidth and energy efficiency of the driving circuit is achieved.
In one embodiment, when the signal output by the optical modulator is a spectrum signal, the delay time between the ith port and the (i+1) th port in the input transmission network is equal to the delay time between the ith port and the (i+1) th port in the output transmission network; when the signal output by the optical modulator is a single-frequency or periodic signal, the delay time between the ith port and the (i+1) th port in the input transmission network and the delay time between the ith port and the (i+1) th port in the output transmission network are different by integer times of the signal period processed by the ith transconductance unit.
In one embodiment, the inductance values Lg in the input transmission network are equal, and the inductance values Ld in the output transmission network are equal; the delay time DeltaTg i_i+1 And delay time DeltaTd i_i+1 According to the difference of the transconductance unit M i The input parasitic capacitance and the output parasitic capacitance of (2) are realized by adjusting the inductance value Lg and the inductance value Ld.
In one embodiment, inductance Lg 1 Is connected to the output of the optical modulator in the transmitting terminal, inductance Lg N+1 Is grounded through the input matching load, inductance Lg 1 ～Lg N+1 The connection point of two adjacent inductors corresponds to the transconductance unit M 1 ～M N Is connected with the input end of the power supply; inductance Ld 1 ～Ld N Corresponds to the first end of the transconductance unit M 1 ～M N Is connected with the output end of the inductor Ld N Is connected to an external load.
In one embodiment, the input matching load includes a resistor R1, and the impedance of the input matching load is equal to the characteristic impedance of the input transmission network.
In one embodiment, the transconductance cell employs a plurality of stacked amplification circuits, each including a bipolar transistor or a field effect transistor.
In one embodiment, the transconductance cell is a gilbert cell.
Drawings
FIG. 1 is a schematic circuit diagram of a conventional single-stage lumped open drain architecture driver circuit;
FIG. 2 is a schematic circuit diagram of a conventional distributed architecture driver circuit;
FIG. 3 is a schematic circuit diagram of a driving circuit with multiple combined current structures according to an embodiment of the present invention;
fig. 4 is a schematic circuit diagram of a first embodiment based on a field effect transistor according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a differential form circuit based on field effect transistors according to an embodiment of the present invention;
FIG. 6 is a schematic circuit diagram of a bipolar transistor according to a first embodiment of the present invention;
FIG. 7 is a graph comparing S-parameter simulation results of driving circuits of a single-stage lumped open drain architecture, a distributed architecture and a multi-path combined current architecture provided by the invention;
fig. 8 is a comparison diagram of transient output current amplitude simulation results of a driving circuit of a single-stage lumped open drain type architecture, a distributed architecture and a multi-channel combined current architecture provided by the invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
In order to solve the contradiction between high efficiency and high bandwidth of the traditional lumped open drain output architecture and the driving circuit of the distributed architecture, the invention provides a driving circuit based on a multi-path current segmentation delay and merging output architecture, which is applied to a transmitting end in an optical fiber communication link,as shown in FIG. 3, the driving circuit comprises an input transmission network including N transconductance units M 1 ～M N An output transmission network and an input matching load.
Wherein the input transmission network comprises n+1 inductors Lg which are sequentially connected in series 1 ～Lg N+1 Inductance Lg 1 Is connected to the output of the optical modulator in the transmitting terminal, inductance Lg N+1 Is grounded through the input matching load, inductance Lg 1 ～Lg N+1 The connection points of two adjacent inductors in the network sequentially form 1-N ports of the input transmission network, and the 1-N ports correspond to the transconductance units M 1 ～M N Is connected to the input terminal of the circuit.
The input transmission network provided in this embodiment is configured to receive a signal output by an optical modulator in a transmitting end, and distribute the signal to the transconductance unit M according to a preset delay time 1 ～M N And performing amplification and voltage-current conversion processing. Specifically, each transconductance unit may adopt a cascode or cascoded one-stage amplifying circuit, a cascode or cascoded two-stage stacked amplifying circuit, a three-stage stacked amplifying circuit or more stacked amplifying circuits, and each stacked amplifying circuit may be built by using a bipolar transistor (as shown in fig. 6) or a field effect transistor (as shown in fig. 4 and 5). Furthermore, the transconductance unit can also adopt a gain-controllable amplifying circuit such as a Gilbert unit and the like to realize the transconductance regulation and control function of the driving circuit.
The input matching load may employ a resistor R1 for absorbing the signal reflected toward the optical modulator, preventing the signal from being reflected toward the optical modulator, and minimizing inter-stage crosstalk. Preferably, the resistance value of the resistor R1 is equal to the characteristic impedance of the input transmission network, so as to achieve the best matching effect.
The output transmission network comprises N inductors Ld which are sequentially connected in series 1 ～Ld N Inductance Ld 1 ～Ld N The first ends of the (a) sequentially form 1-N ports of an output transmission network, and an inductor Ld 1 ～Ld N Corresponds to the first end of the transconductance unit M 1 ～M N Is connected with the output end of the inductor Ld N Is negative with the outside at the second end of (2)The carrier is connected. The output transmission network provided in this embodiment is configured to superimpose amplified current signals output from the transconductance units according to a preset delay time, and combine and output the amplified current signals.
The invention uses the drive circuit of the multi-path current sectionalized delay and merging output framework to replace the traditional single-path open drain output framework as the main circuit framework, and compared with the single-path open drain output, the multi-path current merging output has strict requirements on the relative time delay between each transconductance unit, and the in-phase superposition of current signals can be realized only when the current components generated by each transconductance unit reach the output end at the same time, so that the output current amplitude is maximized. As shown in fig. 3, a transconductance unit M 1 And transconductance unit M 2 For example, to ensure that the two currents are superimposed on the transconductance cell M 2 In-phase superposition at the output node of (a) and delay Δtg between 1,2 ports of the input transmission network 1_2 Delay Δtd between 1,2 ports of the desired and output transmission network 1_2 Exactly equal (for any spectral signal) or both differ by an integer multiple of the signal period T (only for single frequency or periodic signals). Further generalizations from the above analysis may lead to the following requirements: delay ΔTg between i, i+1 ports of input transmission network i_i+1 Delay Δtd between i, i+1 ports of the output transmission network should be i_i+1 Exactly equal (for any spectral signal), or the difference between them is an integer multiple of the signal period T processed by the ith transconductance cell (for only single frequency or periodic signals), expressed as follows:
ΔTG i_i+1 ＝ΔTD i_i+1 for arbitrary spectrum signals (1)
|ΔTG i_i+1 -ΔTD i_i+1 |=m×t (m is a positive integer) for single frequency or periodic signals only (2)
Compared with the traditional open drain output driving circuit, the invention uses the multi-channel transconductance units to combine to form a large amplifying unit, and because each transconductance unit is a small-size circuit, the parasitic capacitance is smaller, and the parasitic capacitance and the inductive element in the input transmission network form series resonance, so that the bandwidth of the circuit can be greatly expanded. Compared with the traditional distributed driving circuit, the invention has no output matching load, so that the invention is a current output type circuit, a modulation voltage signal can be formed only by matching with a load on the side of the optical modulator, and the traditional distributed amplifier can directly output the voltage signal for the voltage output type circuit; second, most conventional distributed amplifiers have symmetry requirements, i.e. the circuit is symmetrical along the center of the middle transconductance cell, which increases the constraints on the input-output transmission network, whereas the inventive circuit cannot be symmetrical, but should require the same delay between two adjacent transconductance cells.
The invention is described in detail below with reference to specific examples:
FIG. 4 shows a first embodiment of the present invention, a multiple current combined output driver amplifier including a field effect transistor Q 1 To Q 2N From inductance Lg 1 To Lg N+1 Field effect transistor Q 1 To Q N An input transmission network composed of input parasitic capacitances; by inductance Ld 1 To Ld N Field effect transistor Q N+1 To Q 2N An output transmission network consisting of the output parasitic capacitance of (2) and a resistor R1 as an input matching load. The whole circuit is based on 28nm CMOS technology, wherein the field effect transistor Q 1 To Q 2N The size of 12u/30n adopts a cascode structure as a transconductance unit to provide signal amplification and voltage-current conversion functions; the resistor R1 is equal to 50 ohms and is used for absorbing an input signal to improve input matching, preventing the input signal from being reflected to the transimpedance amplifier and reducing inter-stage interference to the greatest extent; inductance Lg1 to LgN +1 in an input transmission network has a inductance value of about hundreds of pH, and the specific size needs to be optimized based on imitation software according to the bandwidth target of a design circuit, and the specific size is used for receiving an input signal and respectively distributing the input signal to each transconductance unit according to the designed delay time; the output transmission network is used for respectively superposing amplified current signals from the transconductance units according to the designed delay time and combining and outputting the amplified current signals.
In the present embodiment, the inductance Lg in the input transmission network 1 To Lg N+1 Is used for M 1 To M N Separated from the input parasitic capacitance of (a) and simultaneously separated from the electricityThe capacitance resonance forms a pi-type structure consisting of a series inductance and a parallel capacitance so as to form a grid equivalent transmission line, and theoretically, the transmission line has infinite cutoff frequency in a non-consumption state, but the Q value of an actual device is limited, and the input of a transistor inevitably has resistive loss, so that the grid equivalent transmission line has the cutoff frequency which is still far higher than the cutoff frequency of RC low-pass filtering; likewise, inductance Ld in the output transmission network 1 To Ld N Is effective in combining with M N+1 To M 2N The output parasitic capacitance of the capacitor is resonated to form a drain electrode equivalent transmission line; the increase of the cut-off frequency of the inductance to the transmission network is the increase of the working bandwidth of the multi-path combined current output amplifier.
Assuming that the input parasitic capacitance of each transconductance unit is Cgs, each inductance value in the input transmission network is Lg, the output parasitic capacitance is Cds, each inductance value in the output transmission network is Ld, and the equivalent impedance Z0 of the input transmission network can be obtained according to a transmission line equation under the ideal state of no loss g Equivalent impedance Z0 of output transmission network d Delay deltat between adjacent ports g ，ΔT d The method comprises the following steps of:
it can be seen from the above formula that in order to ensure DeltaT g And DeltaT d The correspondence of the delay in equation 1 or 2 requires careful design of the inductance values of the inductances Ld and Lg and the capacitance values of the parasitic capacitances Cgs and Cds to ensure that the square root of the products are equal or differ by an integer multiple of the signal period. However, since the parasitic capacitances Cgs and Cds are determined by the dimensions of the transistors themselves, and the transistor dimensions are directly related to the transconductance, the dimensions of Cgs and Cds cannot be controlled at will in the design, and inductance control is a main design measure.
Assume that the output matching load of the traditional distributed architecture is a resistor R 2 The load of the output end connection is R Load Intrinsic transconductance of transconductance unit is g m2 The distributed architecture equivalent transconductance G can be obtained from the definition of the whole circuit equivalent transconductance m1 The method comprises the following steps:
equation 5 shows that the equivalent transconductance (i.e., voltage-to-current conversion efficiency) of the circuit is only a fraction of the intrinsic transconductance of the transistor, R is typically used for impedance matching 2 Equal to R Load At this time, the efficiency was only 50%. The invention cancels R 2 Is equivalent to R 2 Infinity, i.e. the equivalent transconductance of the circuit is the same as the intrinsic transconductance of the transistor, and the efficiency can reach 100%.
It should be noted that, in the driving circuit based on the multi-path current segmentation delay and merging output architecture provided in this embodiment, each unit circuit may be designed correspondingly according to different requirements in application, and when differential output is required, each unit circuit needs to be selected from differential circuits, see fig. 5 specifically.
Fig. 7 is a comparison diagram of S-parameter simulation results of a driving circuit of a conventional single-stage lumped open-drain architecture and a distributed architecture and a multi-path combined current architecture provided by the present embodiment, and according to fig. 7, it can be known that the bandwidth of an electrical signal of the architecture provided by the present embodiment is slightly smaller than the bandwidth of the distributed architecture but is far greater than the bandwidth of the conventional lumped open-drain architecture, so as to achieve a bandwidth improvement effect on the open-drain architecture. Fig. 8 is a graph comparing the transient output current amplitude simulation results of the driving circuit of the conventional single-stage lumped open drain architecture and the distributed architecture with the multi-path combined current architecture provided by the present embodiment, and according to fig. 8, it can be known that, under the same voltage signal input amplitude of 500mVpp, the output current amplitude of the architecture provided by the present embodiment is substantially the same as that of the conventional open drain circuit, which is approximately twice the current amplitude of the distributed architecture, which on the one hand, demonstrates the efficiency difference analysis of the distributed architecture and the proposed architecture, on the other hand, demonstrates the high driving efficiency characteristic of the proposed architecture.
By combining the discussion, the multi-path combined current output framework adopted by the invention has the broadband characteristic, the open-drain design of the output port simultaneously improves the driving efficiency of the amplifier, and the multi-path combined current output framework is used for replacing the traditional lumped type amplifier as a driving circuit, so that the circuit bandwidth can be improved; the traditional distributed amplifier is replaced by a multi-path combined current output framework to serve as a driving circuit, so that the driving efficiency of the circuit can be improved; the purpose of effectively compromising the performance of the whole bandwidth and energy efficiency of the driving circuit is achieved.
It will be readily appreciated by those skilled in the art that the foregoing description is merely a preferred embodiment of the invention and is not intended to limit the invention, but any modifications, equivalents, improvements or alternatives falling within the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (7)
1. A drive circuit based on a multipath current segmentation delay and merging output architecture is used for a transmitting end in an optical fiber communication link and is characterized by comprising an input transmission network, an amplifying unit, an output transmission network and an input matching load, wherein the amplifying unit comprises N transconductance units M 1 ～M N ；
The input transmission network comprises n+1 inductors Lg which are sequentially connected in series 1 ～Lg N+1 Inductance Lg 1 ～Lg N+1 The connection points of two adjacent inductors sequentially form 1-N ports of an input transmission network, and the input transmission network is used for receiving and correspondingly distributing signals output by an optical modulator in a transmitting end to a transconductance unit M through the 1-N ports according to preset delay time 1 ～M N Amplifying, voltage and current conversion treatment is carried out;
the input is matched with a load and is used for absorbing signals reflected to the optical modulator;
the output transmission network comprises N inductors Ld which are sequentially connected in series 1 ～Ld N Inductance Ld 1 ～Ld N Sequentially form an output transmission at the first end ofThe output transmission network is used for respectively superposing amplified current signals output by each transconductance unit according to preset delay time and combining and outputting the amplified current signals; wherein the delay time delta Tg between the ith port and the (i+1) th port in the input transmission network i_i+1 Delay time DeltaTd with i-th and i+1-th ports in output transmission network i_i+1 Equal, or the difference between the two is an integer multiple of the period of the signal processed by the ith transconductance cell, i e (1, 2, …, N-1).
2. The drive circuit based on the multi-path current segment delay and merge output architecture according to claim 1, wherein when the signal output by the optical modulator is a spectrum signal, the delay time between the i-th port and the i+1th port in the input transmission network is equal to the delay time between the i-th port and the i+1th port in the output transmission network; when the signal output by the optical modulator is a single-frequency or periodic signal, the delay time between the ith port and the (i+1) th port in the input transmission network and the delay time between the ith port and the (i+1) th port in the output transmission network are different by integer times of the signal period processed by the ith transconductance unit.
3. The drive circuit based on a multi-path current segment delay and merge output architecture according to claim 1 or 2, wherein inductance values Lg in the input transmission network are equal, and inductance values Ld in the output transmission network are equal; the delay time DeltaTg i_i+1 And delay time DeltaTd i_i+1 According to the difference of the transconductance unit M i The input parasitic capacitance and the output parasitic capacitance of (2) are realized by adjusting the inductance value Lg and the inductance value Ld.
4. The drive circuit based on a multiple current segment delay and merge output architecture as claimed in claim 1, wherein the inductor Lg 1 Is connected to the output of the optical modulator in the transmitting terminal, inductance Lg N+1 Is grounded through the input matching load, inductance Lg 1 ～Lg N+1 The connection point of two adjacent inductors corresponds to the transconductance unit M 1 ～M N Is connected with the input end of the power supply; inductance Ld 1 ～Ld N Corresponds to the first end of the transconductance unit M 1 ～M N Is connected with the output end of the inductor Ld N Is connected to an external load.
5. The drive circuit based on a multi-path current-segment delay and merge output architecture according to claim 1, wherein the input matching load comprises a resistor R1, and the impedance of the input matching load is equal to the characteristic impedance of the input transmission network.
6. The drive circuit based on the multi-path current-segment delay and merge output architecture according to claim 1, wherein the transconductance unit employs a plurality of stages of stacked amplifying circuits, each comprising a bipolar transistor or a field effect transistor.
7. The drive circuit based on a multi-path current-segment delay and merge output architecture of claim 1, wherein the transconductance unit employs gilbert cells.
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| CN116112087A (en) | 2023-05-12 |
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