CN116112003A

CN116112003A - Off-chip configurable frequency modulation continuous wave phase-locked loop system and control method

Info

Publication number: CN116112003A
Application number: CN202310162226.0A
Authority: CN
Inventors: 万祝娟; 吴博文; 段宗明; 金微微; 汪功兵
Original assignee: CETC 38 Research Institute
Current assignee: CETC 38 Research Institute
Priority date: 2023-02-21
Filing date: 2023-02-21
Publication date: 2023-05-12

Abstract

The invention discloses an off-chip configurable frequency modulation continuous wave phase-locked loop system and a control method, wherein the system comprises a phase-locked loop circuit, an on-chip digital circuit, an off-chip digital circuit and a tri-state interface circuit, wherein the output end of the on-chip digital circuit is connected with the phase-locked loop circuit, the output ends of the on-chip digital circuit and the off-chip digital circuit are respectively connected with a first input end and a second input end of the tri-state interface circuit to respectively output an on-chip frequency division ratio control signal and an off-chip frequency division ratio control signal to the tri-state interface circuit, the first output end of the tri-state interface circuit is connected with the phase-locked loop circuit to respectively send the on-chip frequency division ratio control signal to the phase-locked loop circuit through the first output end when the tri-state interface circuit is in an on-chip mode, and the off-chip frequency division ratio control signal is sent to the phase-locked loop circuit through the first output end and the second output end is set to be in a high-resistance state.

Description

Off-chip configurable frequency modulation continuous wave phase-locked loop system and control method

Technical Field

The invention relates to the technical field of integrated circuits, in particular to an off-chip configurable frequency modulation continuous wave phase-locked loop system and a control method.

Background

A frequency synthesizer is a device that generates multiple frequencies from one or more reference frequencies and is an essential key circuit for electronic systems. It is widely used in wireless communication, radar and electronic measuring instrument, and plays a decisive role in the overall performance of electronic system. The output frequency range, frequency resolution, frequency switching speed, phase noise, spurious components and other technical indexes of the frequency synthesizer have very important values for the development of the fields of wireless communication, radars, instruments and meters and the like.

At present, a phase-locked loop frequency synthesizer is widely used, and the phase-locked loop frequency synthesizer comprises a frequency and phase discriminator, a charge pump, a voltage-controlled oscillator, a loop filter, a controllable frequency divider and other functional units. When a frequency modulated continuous wave (Frequency Modulated Continuous Wave, FMCW) phase locked loop is used in a radar system, the radar system transmits a series of continuous frequency modulated millimeter waves outwards through an antenna and receives a reflected signal from a target. Meanwhile, with the development of modern digital circuit technology, phase-locked loop digitization is also becoming popular due to the characteristics of high reliability, high flexibility, strong robustness and the like of digital circuits. In the frequency modulation continuous wave phase-locked loop system, the phase-locked loop realizes functions of different frequency points, frequency variation, waveform generation and the like by means of digital control through programming by a digital circuit system.

However, the application specific integrated circuit (Application Specific Integrated Circuit, ASIC) has the disadvantages of long design cycle, high cost, etc., which presents challenges for debugging and iteration of the design. In the related art, a programmable gate array (FPGA) is introduced into a design phase-locked loop to perform auxiliary design, for example, chinese patent application publication No. CN102208911a discloses a method for generating and dynamically configuring a window clock based on an FPGA on-chip phase-locked loop, and configuration parameters of the FPGA on-chip phase-locked loop are set according to a required window clock and a frequency of an input clock, and the window clock is synthesized in the FPGA, so that there is little requirement for externally configured hardware. The Chinese patent document with the authority of CN212850459U discloses a high-precision digital phase-locked loop system based on an FPGA, which comprises a phase discriminator, a TDC time-to-digital converter, a time-temperature calibration module, a digital loop filter, a numerical control oscillator and a temperature sensor which are connected, wherein the phase signal counting smaller than the system clock period is realized through a first counting unit formed by an FPGA high-speed carry chain.

The utility model patent application document of China with the application publication number of CN114024547A discloses a digital circuit system of a linear frequency modulation continuous wave phase-locked loop and the phase-locked loop, and according to an input mode selection signal, a sweep frequency maximum value, a sweep frequency minimum value and a sweep frequency step, a control signal under a corresponding mode is generated to control a control signal generating unit, an address code generating unit, a frequency dividing ratio searching unit, a differential integral modulator, a frequency dividing ratio decoding unit and a dual-mode frequency divider, so that a multifunctional sweep frequency mode with adjustable continuous frequency and fixed frequency output is realized.

The scheme applies the digital circuit to the design of the phase-locked loop circuit, and realizes the functions of continuous frequency adjustment and fixed frequency output; but cannot support both on-chip and off-chip modes to realize on-chip data reading or writing functions.

Disclosure of Invention

The technical problem to be solved by the invention is how to improve the stability, reliability and configurability of the whole phase-locked loop system.

The invention solves the technical problems by the following technical means:

in one aspect, an off-chip configurable frequency modulation continuous wave phase-locked loop system is provided, the system includes a phase-locked loop circuit, an on-chip digital circuit, an off-chip digital circuit, and a tri-state interface circuit, an output end of the on-chip digital circuit is connected to the phase-locked loop circuit, output ends of the on-chip digital circuit and the off-chip digital circuit are respectively connected to a first input end and a second input end of the tri-state interface circuit to output an on-chip frequency division ratio control signal and an off-chip frequency division ratio control signal to the tri-state interface circuit, a first output end of the tri-state interface circuit is connected to the phase-locked loop circuit, and a second output end of the tri-state interface circuit is connected to the off-chip digital circuit to transmit the on-chip frequency division ratio control signal to the phase-locked loop circuit through the first output end when the tri-state interface circuit is in an on-chip mode, and to set the off-chip frequency division ratio control signal to the phase-locked loop circuit through the first output end to a high impedance state.

Further, the phase-locked loop circuit comprises a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator and a dual-mode frequency divider, wherein the output of the phase frequency detector is connected with the voltage-controlled oscillator after passing through the charge pump and the filter in sequence, the output of the voltage-controlled oscillator is respectively connected with the phase frequency detector and the on-chip digital circuit through the dual-mode frequency divider, and the output end of the on-chip digital circuit is connected with the voltage-controlled oscillator;

a first output of the tri-state interface circuit is coupled to the dual-mode frequency divider.

Further, the second output end of the tri-state interface circuit is also connected with the input end of the off-chip digital circuit to output the on-chip frequency division ratio control signal to the off-chip digital circuit.

Further, the on-chip digital circuit comprises a serial peripheral interface, a control signal generating unit, a frequency dividing unit, an address code generating unit, a frequency dividing ratio lookup table, a differential integral modulator, a frequency dividing ratio decoding unit and a voltage-controlled oscillator digital control code generating unit;

the serial peripheral interface comprises a configuration register which is written with a frequency division ratio set value, a time step set value and a frequency step set value, and the control signal generating unit is used for generating control signals corresponding to a frequency sweep mode and a fixed frequency division ratio mode; the output end of the serial peripheral interface is respectively connected with the frequency dividing unit, the control signal generating unit and the voltage-controlled oscillator digital control code generating unit, the output end of the frequency dividing unit and the output end of the control signal generating unit are respectively connected with the address code generating unit, the output end of the address code generating unit is respectively connected with the frequency dividing ratio lookup table and the voltage-controlled oscillator digital control code generating unit, the output end of the frequency dividing ratio lookup table and the output end of the control signal generating unit are respectively connected with the differential integral modulator, and the output end of the differential integral modulator is connected with the frequency dividing ratio decoding unit;

The output end of the frequency division ratio decoding unit is connected with the tri-state interface circuit, and the output end of the voltage-controlled oscillator digital control code generating unit is connected with the voltage-controlled oscillator in the phase-locked loop circuit.

Further, the control signal of the address code generating unit is 0 in the sweep frequency mode, and the control signal of the address code generating unit is changed from 0 to 1 in the fixed frequency division ratio mode; the time when the control signal of the address code generating unit is 0 is longer than the locking time of the phase-locked loop circuit.

Further, the input signal of the digital control code generating unit of the voltage-controlled oscillator comprises a reference clock, an address code sent by the address code generating unit, an address code initial value and a control initial value sent by the serial peripheral interface;

when the address code is a fixed value, the voltage-controlled oscillator digital control code generation unit sends a voltage-controlled oscillator digital control code of the voltage-controlled oscillator to be equal to the initial value of the control code;

when the address code continuously changes and exceeds the initial value of the address code, the voltage-controlled oscillator digital control code generation unit starts to continuously change the voltage-controlled oscillator digital control code sent to the voltage-controlled oscillator, and the change step length is related to the frequency characteristic of the voltage-controlled oscillator.

Further, the control signal generating unit is connected with an external system and is used for receiving an interface signal wave_start sent by the external system and sending an effective frame_en signal to the external system when the interface signal wave_start is effective, wherein the interface signal wave_start is used for controlling the starting time of the phase-locked loop waveform generation, and the frame_en signal is used as a sign signal of the phase-locked loop waveform generation;

the address code generating unit is connected with the external system for transmitting an active adc_en signal to the external system when the interface signal wave_start is active, the adc_en signal being used as a flag signal for a phase-locked loop waveform linearization area.

Further, the off-chip digital circuit comprises a data acquisition module, a data storage module and a control signal generation circuit; the input end of the data acquisition module is connected with the tri-state interface circuit, the output end of the data acquisition module is connected with the data storage module, and the output end of the control signal generation circuit is connected with the tri-state interface circuit;

the output end of the data storage module is connected with an analysis instrument, and the output end of the analysis instrument is connected with the control signal generation circuit.

Further, the off-chip digital circuit is integrated by adopting an FPGA chip.

In a second aspect, the present invention further provides a control method of the off-chip configurable fm continuous wave pll system, where the control method includes:

outputting a digital control code to the phase-locked loop circuit by using the on-chip digital circuit so as to control the phase-locked loop circuit to work;

generating an on-chip frequency division ratio control signal and an off-chip frequency division ratio control signal by using the on-chip digital circuit and the off-chip digital circuit respectively;

when the tri-state interface circuit is in an on-chip mode, the on-chip frequency division ratio control signal is obtained through a first input end of the tri-state interface circuit and is forwarded to the phase-locked loop circuit through a first output end, and meanwhile, the on-chip frequency division ratio control signal is output to an off-chip digital circuit through a second output end, so that off-chip reading of on-chip data is realized;

when the tri-state interface circuit is in an off-chip mode, the off-chip frequency division ratio control signal is obtained through the second input end of the tri-state interface circuit and is forwarded to the phase-locked loop circuit through the first output end, and meanwhile the second output end is set to be in a high-resistance state.

Further, generating an on-chip divide ratio control signal using the on-chip digital circuit includes:

Writing operation of configuration registers in different modes of the phase-locked loop is carried out by utilizing the serial peripheral interface, writing information comprises a frequency dividing ratio set value, a time step set value, a frequency step value, an address code initial value and a control initial value, and the modes of the phase-locked loop comprise a fixed frequency dividing ratio mode and a sweep frequency mode;

the frequency dividing unit reads a frequency dividing ratio setting value set in the configuration register, divides the input reference clock to obtain a frequency-divided clock and outputs the frequency-divided clock to the address code generating unit as a clock signal of the address code generating unit;

the control signal generating unit generates a control signal in a sweep frequency mode based on the writing information in different modes, and inputs the control signal to the address code generating unit and the differential integral modulator;

the address code generating unit generates an address code based on the control signal and sends the address code to the frequency division ratio lookup table so that the frequency division ratio lookup table outputs a frequency division ratio corresponding to the address code to the differential integral modulator;

the differential integral modulator modulates the frequency division ratio, generates the modulated frequency division ratio, sends the modulated frequency division ratio to a frequency division ratio decoding unit, converts the modulated frequency division ratio into a frequency division ratio control signal through the frequency division ratio decoding unit and outputs the frequency division ratio control signal to the tri-state interface circuit.

Further, the outputting a digital control code to the pll circuit by the on-chip digital circuit to control the pll circuit to operate includes:

the digital control code generating unit of the voltage-controlled oscillator acquires a reference clock, an address code sent by the address code generating unit, an address code initial value and a control initial value sent by the serial peripheral interface;

in a fixed frequency division ratio mode, when the address code is a fixed value, the voltage-controlled oscillator digital control code sent to the voltage-controlled oscillator by the voltage-controlled oscillator digital control code generation unit is equal to the control code initial value;

in the sweep frequency mode, when the address code continuously changes and exceeds the initial value of the address code, the voltage-controlled oscillator digital control code generation unit starts to continuously change the voltage-controlled oscillator digital control code sent to the voltage-controlled oscillator.

Further, the address code generating unit adjusts the period and slope of the waveform in the sweep frequency mode according to the frequency step written in by the register in the serial peripheral interface and the time step output by the frequency dividing unit.

Further, the control signal of the address code generating unit is 0 in the sweep frequency mode, and the control signal of the address code generating unit is changed from 0 to 1 in the fixed frequency division ratio mode; the time when the control signal of the address code generating unit is 0 and the time when the control signal of the address code generating unit is 1 are adjustable, and the time when the control signal of the address code generating unit is 0 is longer than the locking time of the phase-locked loop circuit.

Further, the method further comprises:

when the phase-locked loop circuit starts to work, a fixed frequency dividing ratio mode is entered, when the control signal generating unit detects that a wave_start signal input by an external system is effective, a control signal in a frequency sweeping mode is generated and sent to the address code generating unit, otherwise, the phase-locked loop circuit continues to work in the fixed frequency dividing ratio mode;

when the waveform generation starts, the control signal generation unit generates an effective frame_en signal and outputs the signal to the external system;

when the frequency of the waveform output by the address code generating unit enters a set area, generating an effective adc_en signal and outputting the effective adc_en signal to an external system;

when all waveforms are generated completely, the fixed division ratio mode is returned.

The invention has the advantages that:

(1) The digital control system for realizing the phase-locked loop frequency modulation continuous wave function can be realized in the on-chip digital circuit or the off-chip digital circuit by arranging the tri-state interface circuit, so that the functions of the phase-locked loop system can be configured and controlled off-chip, and the off-chip digital circuit can replace part of the functions of the on-chip digital circuit system; the digital systems both on-chip and off-chip can input control signals to the dual-mode frequency divider, so that the stability, reliability and configurability of the whole phase-locked loop system are improved.

(2) The off-chip digital circuit can read the output of the on-chip digital circuit and replace part of the functions of the on-chip digital circuit, thereby improving the reliability, the configurability and the stability of the frequency modulation continuous wave phase-locked loop.

(3) The on-chip digital circuit is adopted to realize any one of a fixed frequency division ratio mode or a sweep frequency mode, wherein the sweep frequency mode can determine the waveform type, the sweep frequency range, sweep frequency stepping and the like according to the requirements of a system, and different working modes are realized by controlling the address code generating unit, the differential integral modulator and other units through the frequency division unit and the control signal generating unit based on the requirements of the system function, so that the on-chip digital circuit is suitable for the requirements of different systems.

(4) The frequency modulation continuous wave phase-locked loop waveform generation function is realized, and the method is applicable to different requirements of an FMCW radar system.

(5) The phase-locked loop circuit, the tri-state interface circuit and the on-chip digital circuit are realized by an ASIC (application specific integrated circuit), the off-chip digital circuit system is realized by an FPGA (field programmable gate array), the advantages of small ASIC area, excellent performance and low power consumption and the advantages of high flexibility, programmability and short development period of the FPGA are utilized, the two are combined with each other, the frequency synthesis source with wide frequency range, fine frequency stepping, low phase noise and rapid frequency switching is realized by taking the complementary short, the function of continuous frequency adjustability or fixed frequency output is realized, and the requirements of different phase-locked loop systems are met.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

FIG. 1 is a schematic diagram of an off-chip configurable frequency-modulated continuous wave PLL system according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a linear FM continuous wave PLL according to the present invention;

FIG. 3 is a schematic diagram of an on-chip digital circuit according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a frequency dividing unit according to an embodiment of the invention;

FIG. 5 is a schematic diagram illustrating waveforms generated in a phase locked loop sweep mode according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a digital control code generation unit of a voltage controlled oscillator according to an embodiment of the present invention;

FIG. 7 is a schematic diagram illustrating the workflow of the interface signals between the PLL and the external system according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of an off-chip digital circuit according to an embodiment of the invention;

FIG. 9 is a schematic diagram of another off-chip digital circuit according to an embodiment of the invention;

FIG. 10 is a schematic diagram illustrating the operation of a tri-state interface circuit in an on-chip mode of operation in accordance with an embodiment of the present invention;

FIG. 11 is a schematic diagram illustrating the operation of the tri-state interface circuit in an off-chip mode of operation in accordance with an embodiment of the present invention;

FIG. 12 is a schematic diagram showing a specific configuration of a tri-state interface circuit according to an embodiment of the present invention;

fig. 13 is a flow chart of a control method of an off-chip configurable fm continuous wave pll system according to an embodiment of the invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described in the following in conjunction with the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

As shown in fig. 1, a first embodiment of the present invention proposes an off-chip configurable fm continuous wave pll system, the system includes a pll circuit 10, an on-chip digital circuit 20, an off-chip digital circuit 30, and a tri-state interface circuit 40, wherein an output terminal of the on-chip digital circuit 20 is connected to the pll circuit 10, output terminals of the on-chip digital circuit 20 and the off-chip digital circuit 30 are respectively connected to a first input terminal and a second input terminal of the tri-state interface circuit 40 to respectively output an on-chip divide ratio control signal and an off-chip divide ratio control signal to the tri-state interface circuit 40, and a first output terminal of the tri-state interface circuit 40 is connected to the pll circuit 10 to transmit the on-chip divide ratio control signal to the pll circuit 10 through the first output terminal when the tri-state interface circuit 40 is in an on-chip mode, and to transmit the off-chip divide ratio control signal to the pll circuit 10 through the first output terminal when the tri-state interface circuit 40 is in a high impedance state.

The tri-state interface circuit 40 is provided, so that the off-chip frequency division ratio control signals and the on-chip frequency division ratio control signals output by the off-chip digital circuit 30 and the on-chip digital circuit 20 can be respectively obtained, a digital control system for realizing the phase-locked loop frequency modulation continuous wave function can be realized in the on-chip digital circuit 20 or the off-chip digital circuit 30, and therefore, the function of the phase-locked loop system can be configured and controlled off-chip, and the off-chip digital circuit 30 can replace part of the functions of the on-chip digital circuit 20; the digital systems both on-chip and off-chip can input control signals to the dual-mode frequency divider 15, improving the stability, reliability and configurability of the overall system of the phase-locked loop.

In an embodiment, the pll circuit 10 includes a phase frequency detector 11, a charge pump 12, a loop filter 13, a voltage-controlled oscillator 14, and a dual-mode frequency divider 15, where an output of the phase frequency detector 11 is sequentially connected to the voltage-controlled oscillator 14 after passing through the charge pump 12 and the filter, an output of the voltage-controlled oscillator 14 is respectively connected to the phase frequency detector 11 and the on-chip digital circuit 20 through the dual-mode frequency divider 15, and an output end of the on-chip digital circuit 20 is connected to the voltage-controlled oscillator 14;

The output of the tri-state interface circuit 40 is connected to the dual-mode frequency divider 15.

As shown in fig. 2, the conventional fm continuous wave pll includes a Phase-frequency detector 11 (PFD), a Charge Pump 12 (CP), a Filter 13 (Filter), a Voltage-controlled oscillator 14 (Voltage-Controlled Oscillator, VCO), a dual-mode Divider 15 (Multi-module Divider, MMD), and a differential integrating modulator 26 (Digital SDM) connected in this order. The phase frequency detector 11 detects the phase difference and the frequency difference between the reference signal Fref at the input end and the loop feedback signal Fdiv, and outputs a corresponding voltage signal to the charge pump 12, and the charge pump 12 circuit converts the voltage signal into a control voltage. The filter filters out the high frequency component in the control voltage, outputs a direct current level, and finally serves as the control voltage of the voltage-controlled oscillator 14, and the output Fvco of the voltage-controlled oscillator 14 is the output signal of the phase-locked loop. As the frequency difference and the phase difference between the two input signals of the phase frequency detector 11 decrease, the phase locked loop reaches a locked state when the control voltage is a certain constant voltage value. When the loop is in the locked state, if the frequency and phase of the input reference signal change, the frequency and phase of the voltage controlled oscillator 14 can continuously track the change of the frequency of the input reference signal and change by the control action of the loop, so that the loop is re-in the locked state, and the dynamic process is called a tracking process of the loop. When the differential integral modulator 26 inputs continuously changes, the differential integral modulator 26 modulates and outputs the division ratio N.F including integers and fractions, and controls the division ratio change of the double modulus divider 15. When the frequency division ratio of the dual-mode frequency divider 15 continuously changes, the output of the dual-mode frequency divider 15, that is, the frequency and phase of the loop feedback signal Fdiv change, the phase-locked loop in the "tracking" state can continuously change the output Fvco of the voltage-controlled oscillator 14 through the control function of the loop, that is, the frequency sweeping function of the frequency-modulated continuous wave phase-locked loop is realized.

In this embodiment, the second output terminal of the tri-state interface circuit 40 is further connected to the input terminal of the off-chip digital circuit 30 to output the on-chip divide ratio control signal to the off-chip digital circuit 30.

The off-chip digital circuit 30 in this embodiment can not only read the output of the on-chip digital circuit 20, but also replace part of the functions of the on-chip digital circuit 20, thereby improving the reliability, configurability and stability of the frequency modulation continuous wave phase locked loop.

In one embodiment, as shown in fig. 3, the on-chip digital circuit 20 includes a serial peripheral interface 21, a control signal generating unit 23, a frequency dividing unit 22, an address code generating unit 24, a frequency dividing ratio lookup table 25, a differential integral modulator 26, a frequency dividing ratio decoding unit 27, and a voltage controlled oscillator digital control code generating unit 28;

the serial peripheral interface 21 includes a configuration register for writing a frequency division ratio setting value, a time step setting value and a frequency step setting value, and the control signal generating unit 23 is configured to generate control signals corresponding to a frequency sweep mode and a fixed frequency division ratio mode; the output end of the serial peripheral interface 21 is respectively connected with the frequency dividing unit 22, the control signal generating unit 23 and the voltage-controlled oscillator digital control code generating unit 28, the output end of the frequency dividing unit 22 and the output end of the control signal generating unit 23 are respectively connected with the address code generating unit 24, the output end of the address code generating unit 24 is respectively connected with the frequency dividing ratio lookup table 25 and the voltage-controlled oscillator digital control code generating unit 28, the output end of the frequency dividing ratio lookup table 25 and the output end of the control signal generating unit 23 are respectively connected with the differential integral modulator 26, and the output end of the differential integral modulator 26 is connected with the frequency dividing ratio decoding unit 27; an output terminal of the frequency division ratio decoding unit 27 is connected to the tri-state interface circuit 40, and an output terminal of the voltage-controlled oscillator digital control code generating unit 28 is connected to the voltage-controlled oscillator 14 in the phase-locked loop circuit 10.

It should be noted that, the serial peripheral interface 21 is a high-speed, full duplex, synchronous communication bus for the external device to exchange information with the on-chip digital circuit 20 internally; the frequency divider comprises a first output end, a second output end and a third output end which are respectively connected with a frequency dividing unit 22, a control signal generating unit 23 and a voltage-controlled oscillator digital control code generating unit 28. According to two different working modes of the phase-locked loop, namely a fixed frequency division ratio mode and a sweep frequency mode, the serial peripheral interface 21 completes the writing operation of the configuration register under the corresponding mode, and the control signal generating unit 23 and the voltage-controlled oscillator digital control code generating unit 28 read the value of the configuration register to complete the setting of the initial value.

The control signal generating unit 23 includes a sweep frequency mode and a fixed frequency division ratio mode, and is configured to provide control signals corresponding to the sweep frequency mode and the fixed frequency division ratio mode, so as to control the function of the frequency modulation continuous wave phase locked loop. It includes two inputs respectively connected to the serial peripheral interface 21 and the external system, and three outputs respectively connected to the address code generation unit 24, the differential integral modulator 26, and the external system. The control signal generating unit 23 is configured to generate control signals corresponding to the two modes, and control operations of the address code generating unit 24 and the differential integral modulator 26.

The frequency dividing unit 22 is configured to distribute clocks required by internal part modules of the on-chip digital circuit 20, as shown in fig. 4, and includes two input terminals and an output terminal, where one input terminal inputs a reference clock signal, the other input terminal is connected to the serial peripheral interface 21 to obtain a frequency division ratio set in a configuration register, and one output terminal is connected to the address code generating unit 24; the frequency dividing unit 22 divides the input reference clock according to the set frequency dividing ratio to obtain a frequency-divided clock and outputs the frequency-divided clock to the address code generating unit 24, and the frequency and period of the frequency-divided clock output by the frequency dividing unit 22 are different according to the difference of the set frequency dividing ratio, and the frequency-divided clock is connected to the address code generating unit 24 and used as a clock signal of the address code generating unit 24, so that the working frequency and period of the address code generating unit 24 are controlled.

An address code generating unit 24 for generating an input address code of the frequency division ratio lookup table 25, wherein in the fixed frequency division ratio mode, the address code generating unit 24 generates a fixed address code and sends the fixed address code to the frequency division ratio lookup table 25; in the sweep mode, the address code generating unit 24 generates address codes that continuously change, and sends the address codes to the frequency division ratio lookup table 25.

The frequency division ratio lookup table 25 is used to generate the frequency division ratio of the modulation required by the differential integral modulator 26.

A differential integral modulator 26 for modulating the preset frequency division ratio output from the frequency division ratio lookup table 25 to generate the frequency division ratio of the dual-mode frequency divider 15.

The frequency division ratio decoding unit 27 is configured to convert the modulated frequency division ratio output by the differential integral modulator 26 into a frequency division control signal, and output the frequency division control signal to the frequency division ratio control port of the dual-mode frequency divider 15.

A vco digital control code generating unit 28 for generating a vco digital control code for adjusting the size of the capacitor array in the vco 14, thereby modifying the frequency value of the vco 14. The initial value and the change step length of the digital control code of the voltage-controlled oscillator can be controlled by the digital control code generating unit, so that the frequency of the voltage-controlled oscillator 14 is controlled to be changed according to an expected rule.

Specifically, when the pll operates in the fixed frequency division ratio mode, the serial peripheral interface 21 unit completes the writing operation of the configuration register in the corresponding mode, and the control signal generating unit 23 and the vco digital control code generating unit 28 read the values of the configuration register, thereby completing the setting of the initial values of part of signals in the two units. The control signal generating unit 23 generates a control signal in the fixed frequency division ratio mode, and controls the operations of the address code generating unit 24 and the differential integral modulator 26. In the fixed frequency division ratio mode, the address code generating unit 24 generates a fixed address code and sends the address code to the frequency division ratio lookup table 25, and the frequency division ratio lookup table 25 outputs the frequency division ratio corresponding to the address code, and the differential integral modulator 26 modulates the frequency division ratio to generate a modulated frequency division ratio. The frequency division ratio decoding unit 27 converts the modulated frequency division ratio into a frequency division ratio control signal and outputs the frequency division ratio control signal.

Specifically, when the pll works in the sweep mode, the serial peripheral interface 21 unit completes the write operation of the configuration register in the corresponding mode, and the control signal generating unit 23 and the vco digital control code generating unit 28 read the values of the configuration register, thereby completing the setting of the initial values of part of signals in the two units. The control signal generating unit 23 generates a control signal in the sweep mode, and controls the operations of the address code generating unit 24 and the differential integral modulator 26. In the sweep frequency mode, the address code generating unit 24 generates address codes which continuously change and sends the address codes to the frequency division ratio lookup table 25, and the frequency division ratio lookup table 25 outputs the frequency division ratio corresponding to the address codes. Since the address code is continuously variable, the frequency division ratio output from the frequency division ratio lookup table 25 is also continuously variable. The differential integral modulator 26 modulates the frequency division ratio to produce a modulated frequency division ratio. The frequency division ratio decoding unit 27 converts the modulated frequency division ratio into a frequency division ratio control signal and outputs the frequency division ratio control signal.

The on-chip digital circuit 20 according to the present embodiment realizes different working modes based on the requirements of system functions by controlling the address code generating unit 24, the differential integral modulator 26 and other units through the frequency dividing unit 22 and the control signal generating unit 23, and adapts to the requirements of different systems. Any one of a fixed frequency division ratio mode or a sweep frequency mode can be realized, wherein the sweep frequency mode can determine waveform types, sweep frequency ranges, sweep frequency steps and the like according to the requirements of a system.

Further, in the FMCW radar system, the frequency modulation method mainly includes triangular wave, saw tooth wave, code modulation, noise modulation, and the like. The FMCW radar emits continuous waves with frequency change in a sweep frequency period, and performs coherent mixing by utilizing an echo signal and a part of the emitted signals to obtain intermediate frequency signals containing distance and speed information of the target, and then detects the intermediate frequency signals to obtain the distance and speed of the target. The frequency of the intermediate frequency signal is lower, which is beneficial to data acquisition and digital signal processing. Therefore, the waveform generation function of the frequency modulated continuous wave phase locked loop is critical to radar systems. The phase-locked loop system provided by the embodiment has the frequency modulation continuous wave phase-locked loop waveform generation function, realizes the waveform modulation such as triangular wave modulation and sawtooth wave, and is applicable to the conditions of different requirements of the FMCW radar system, and specifically comprises the following steps:

the phase-locked loop works in the sweep frequency mode, the control signal sent by the control signal generating unit 23 to the address code generating unit 24 is 0, at this time, the signal controls the address code generating unit 24 to output a fixed address code, the phase-locked loop works at a fixed frequency division ratio, after the phase-locked loop is locked, the control signal of the address code generating unit 24 is changed from 0 to 1, at this time, the signal controls the address code generating unit 24 to output a continuously variable address code, and the phase-locked loop starts to sweep frequency.

The control signal of the differential integral modulator 26 is first 0, at this time, the signal controls all registers in the differential integral modulator 26 to be cleared, and after a few clock cycles, the control signal of the differential integral modulator 26 becomes 1, at this time, the signal controls the differential integral modulator 26 to perform modulation operation according to the frequency division ratio corresponding to the address code output by the address code generating unit 24. It should be noted that, in this process, when the control signal of the address code generating unit 24 is changed from 0 to 1, the control signal of the differential integral modulator 26 is still kept at 1, and the differential integral modulator 26 modulates the continuously variable frequency division ratio, and when the sweep process is finished, i.e. the next working period begins, the control signal of the differential integral modulator 26 is changed to 0, and all registers in the differential integral modulator 26 are cleared, so that the values of the registers in the sweep process cannot affect the working of the next period.

When the control signal of the address code generation unit 24 is 1, the address code generation unit 24 outputs the address code that continuously changes. The manner in which the address code is continuously varied is determined by the waveform to be implemented, as shown in fig. 5. When sawtooth wave is needed to be generated, the address code needs to be continuously increased, and when the preset maximum value of the sweep frequency is reached, the address code needs to be reset again, and the initial value is changed back to the minimum value of the sweep frequency. When the triangular wave needs to be generated, the address code needs to be continuously increased, and after the preset maximum value of the sweep frequency is reached, the address code is continuously reduced until the initial value is reduced, namely the minimum value of the sweep frequency. It should be noted that the frequency of the pll cannot be suddenly changed, otherwise, the pll will lose lock during the frequency sweep, so in the actual implementation of the triangular wave, a holding section is added, that is, after the address code is continuously increased to the preset frequency sweep maximum value, the holding section will remain unchanged for a period of time, and then continuously decrease until the initial value is the frequency sweep minimum value.

In one embodiment, the control signal of the address code generating unit 24 is 0 in the sweep mode, and the control signal of the address code generating unit 24 is changed from 0 to 1 in the fixed frequency division ratio mode; the control signal of the address code generation unit 24 is 0 for a time longer than the lock time of the phase-locked loop circuit 10.

It should be noted that, the time when the control signal of the address code generating unit 24 is 0 and the time when the control signal of the address code generating unit 24 is 1 are adjustable, and the time when the control signal of the address code generating unit 24 is 0 is determined by the pll system, that is, the pll needs to lock to the frequency corresponding to the minimum value of the frequency sweep before the frequency sweep starts. Therefore, it is necessary to ensure that the time for which the control signal of the address code generating unit 24 is 0 is longer than the lock time of the phase locked loop, and specific setting can be achieved by configuring the control signal generating unit 23 through the serial peripheral interface 21.

Further, the rising time, idle time and repetition period of the sawtooth wave are all adjustable. The slope of the sawtooth wave can be adjusted by controlling the time step and the frequency step of the address code change, the time step can be realized by controlling the clock of the address code generating unit 24 by the frequency dividing unit 22, and the sweep frequency step can be realized by configuring the control signal generating unit 23 by the serial peripheral interface 21. The rise time, idle time, and repetition period can be realized by configuring the control signal generating unit 23 through the serial peripheral interface 21.

Further, the rise time, hold time, fall time, idle time, and repetition period of the triangular wave are all adjustable. The slope of the triangle wave can be adjusted by controlling the time step and the frequency step of the address code change, the time step can be realized by controlling the clock of the address code generating unit 24 by the frequency dividing unit 22, and the sweep frequency step can be realized by configuring the control signal generating unit 23 by the serial peripheral interface 21. The rise time, the hold time, the fall time, the idle time, and the repetition period can be realized by configuring the control signal generating unit 23 through the serial peripheral interface 21.

The waveform generating functions such as triangular wave and sawtooth wave provided by the above embodiment are realized by the control signal generating unit 23 controlling the address code generating unit 24 and the differential integral modulator 26; the slopes of the triangular wave and the sawtooth wave can be adjusted by the time step and the frequency step, and the time step and the frequency step can be realized by the frequency dividing unit 22 and the control signal generating unit 23; parameters such as time and repetition period of the triangle wave and the sawtooth wave can be realized by configuring the control signal generating unit 23 through the serial peripheral interface 21.

In this embodiment, the control signal generating unit 23 calculates the working time and period required by the address code generating unit 24 and the differential integral modulator 26 in the sweep mode according to the sweep maximum value, the sweep minimum value and the sweep step size, and the function is realized by the change of the control signal output by the control signal generating unit 23. And according to different setting values of time step and frequency step of the register in the serial peripheral interface 21, the period and slope of the waveform in the sweep frequency mode are adjustable.

In one embodiment, as shown in fig. 6, the input signals of the vco digital control code generating unit 28 include a reference clock, the address code sent by the address code generating unit 24, the initial value of the address code sent by the serial peripheral interface 21, and the initial value of the control;

when the address code is a fixed value, the voltage-controlled oscillator digital control code generating unit 28 sends a voltage-controlled oscillator digital control code to the voltage-controlled oscillator 14, wherein the voltage-controlled oscillator digital control code is equal to the initial value of the control code;

when the address code continuously changes and exceeds the initial value of the address code, the vco digital control code generating unit 28 starts to continuously change the vco digital control code sent to the vco 14, and the change step length is related to the frequency characteristic of the vco 14.

It should be noted that the address code initial value and the control initial value may be changed by the configuration of the serial peripheral interface 21.

When the pll is in the fixed frequency division ratio mode, the address code output by the address code generating unit 24 is a fixed value and equal to the initial value of the address code, and at this time, the digital control code of the vco is equal to the initial value of the control code and is output to the vco 14.

When the phase-locked loop is in sweep mode, the address code output by the address code generating unit 24 is continuously changed, and when the address code exceeds the initial value of the address code, the digital control code of the voltage-controlled oscillator starts to be continuously changed and is output to the voltage-controlled oscillator 14.

It should be noted that, the initial value of the vco digital control code is the initial value of the control code, the changing step length may be changed according to the frequency characteristic of the vco 14, and the number of bits of the outputted vco digital control code may also be changed according to the actual situation of the vco 14, which is only illustrated by way of example and not limitation in the embodiment of the present invention.

In an embodiment, the control signal generating unit is connected to an external system and is configured to receive an interface signal wave_start sent by the external system and send an active frame_en signal to the external system when the interface signal wave_start is active, where the interface signal wave_start is used to control a start time of a phase-locked loop waveform, and the frame_en signal is used as a flag signal of the phase-locked loop waveform generation;

the address code generation unit 24 is connected to the external system for transmitting an active adc en signal to the external system when the interface signal wave_start is active, the adc en signal serving as a flag signal for the phase-locked loop waveform linearization area.

When the frequency modulation continuous wave phase-locked loop starts to work, firstly, a fixed frequency division ratio mode is entered, and the phase-locked loop is locked at a preset frequency value; when the phase-locked loop detects that the wave_start signal input by an external system is valid, the phase-locked loop starts to enter a sweep frequency mode to prepare for waveform generation, otherwise, the phase-locked loop continues to work in a fixed frequency division ratio mode.

Specifically, the external system in the present embodiment includes, but is not limited to, an FMCW radar system, the core of which is a chirp signal, which is a sine wave whose frequency grows in a linear manner with time. The chirp signal may be generated by a sweep mode of a phase locked loop in an embodiment of the present invention. In the working process of the radar, the radar does not blur the distance and is related to the pulse repetition period, so that the radar system needs to configure the period of the linear frequency modulation pulse signal in order to avoid the occurrence of the distance discrimination blur, and the interface is arranged to interact with the FMCW radar system. According to the relation between the object reflected signal and the transmitted signal and the principle of radar ranging and speed measurement, the radar system needs to be configured with parameters such as waveform slope, bandwidth, frequency resolution and the like of the linear frequency modulation pulse.

As shown in fig. 7, when the waveform generation starts, the phase locked loop generates an active frame_en signal and outputs it to the external system; when the frequency of the output waveform of the phase-locked loop enters a set area, the phase-locked loop generates an effective adc en signal and outputs the effective adc en signal to an external system. When all waveforms are generated completely, i.e. the phase-locked loop waveform is completely ended, the phase-locked loop returns to the fixed frequency division ratio mode, otherwise the phase-locked loop will perform waveform generation of the next period, and the above flow is repeated.

It should be noted that, the wave_start signal controls the start time of the phase-locked loop waveform, and is used for triggering the operation of the sweep frequency mode of the frequency modulation continuous wave phase-locked loop, so that the external system can adjust the sweep frequency mode according to the requirement, and is used for controlling the operation of the phase-locked loop. The frame_en is provided to an external circuit of the phase-locked loop and used as a sign signal generated by the phase-locked loop waveform; the adc en is used to provide an external circuit of the phase-locked loop, and is used as a flag signal for the linearization region of the phase-locked loop waveform, which can be used as an enable signal for the analog-to-digital converter. The output time and the effective time of the frame_en and the adc_en signals are adjustable, and can be realized by changing the judging conditions. Therefore, the design of the phase-locked loop can be changed according to the requirements of the external system of the phase-locked loop.

The embodiment of the invention provides interface signals of the frequency modulation continuous wave phase-locked loop and an external system, namely wave_start, frame_en and adc_en. The wave_start signal is an input signal of the phase locked loop and is provided by an external system. frame_en, adc_en are output signals of the phase locked loop, which are provided to an external system. The external system may adjust the start time of the wave_start signal to control the waveform generation of the phase locked loop. The phase-locked loop can adjust the output time and the effective time of the frames_en and the adc_en so as to output the signals to an external system for use.

It should be noted that, in this embodiment, aiming at the requirements of waveform generation, period, frequency resolution and the like of the linear frequency modulation pulse in the FMCW radar system, the phase-locked loop is utilized to realize the generation of waveforms such as triangular waves, saw-tooth waves and the like, and the functions of configurable waveform repetition period, configurable waveform slope, configurable frequency resolution and the like can be realized according to the requirements of the FMCW radar system, and interface signals interacted with the FMCW radar system are generated. Aiming at the defects of long design period and high cost of an Application Specific Integrated Circuit (ASIC), a programmable gate array (FPGA) is introduced into a design phase-locked loop to carry out auxiliary design, so that partial functions of digital circuit systems in the phase-locked loop are replaced, an on-chip mode and an off-chip mode are supported, and the function of reading or writing data in the chip is realized.

In terms of structural composition, compared with the digital circuit system and the phase-locked loop of the linear frequency modulation continuous wave phase-locked loop proposed in the patent application document with publication number of CN114024547A, the phase frequency detector, the charge pump, the filter, the voltage-controlled oscillator, the dual-mode frequency divider, the tri-state interface circuit and the on-chip digital circuit system in the embodiment are realized by an ASIC (application specific integrated circuit), and the off-chip digital circuit system is realized by an FPGA (field programmable gate array). In the CN114024547a scheme, the circuit is composed of a phase frequency detector, a charge pump, a filter, a voltage controlled oscillator, a digital circuit system and other modules, where the digital circuit system includes a control signal generating unit, an address code generating unit, a frequency dividing ratio searching unit, a differential integral modulator, a frequency dividing ratio decoding unit, a dual-mode frequency divider and other modules. The digital circuit in the chip is composed of a serial peripheral interface, a frequency dividing unit, a control signal generating unit, an address code generating unit, a frequency dividing ratio searching unit, a differential integral modulator, a frequency dividing ratio decoding unit, a voltage controlled oscillator digital control code generating unit and other modules. The on-chip digital system comprises a serial peripheral interface, and a required initial value is set through a configuration register; the frequency dividing unit is used for providing frequency-divided clock signals corresponding to different settings; the digital control code generation unit of the voltage controlled oscillator is included, and the digital control code of the voltage controlled oscillator which is continuously changed is generated and transmitted. In addition, the control signal generating unit in the present embodiment provides generation of control signals under different waveforms, different periods, different frequencies, etc., and provides interface signals such as wave_start, frame_en, etc., which interact with the external FMCW radar system. The address code generating unit in this embodiment uses the clock divided by the frequency dividing unit as the working clock, generates the corresponding address code under the control of the control signal of different situations, and outputs the interface signal, such as adc_en, which interacts with the external FMCW radar system.

In the aspect of application scenes, the phase-locked loop provided in the CN114024547A scheme can generate different frequencies, can lock a single frequency point, generates sawtooth wave waveforms in a sweep frequency mode, is suitable for application scenes with different frequency requirements, is suitable for simple waveform generation functions in an FMCW radar system, and does not provide an interaction interface with the FMCW radar system. The embodiment of the invention provides waveform generation of linear frequency modulation pulses, such as sawtooth waves, triangular waves and the like, and is suitable for application scenes corresponding to different pulses in an FMCW radar system. The interaction interface with the FMCW radar system is provided, and the method is suitable for the configuration scene of the FMCW radar system to the embodiment of the invention and the application scene of the FMCW radar system to the information interaction of the embodiment of the invention.

In one embodiment, as shown in fig. 8, the off-chip digital circuit 30 includes a data acquisition module, a data storage module, and a control signal generation circuit; the input end of the data acquisition module is connected with the tri-state interface circuit 40, the output end of the data acquisition module is connected with the data storage module, and the output end of the control signal generation circuit is connected with the tri-state interface circuit 40;

The off-chip digital circuit 30 exchanges information with analytical instruments such as the chip interior and a computer. The data acquisition module is connected with the data storage module, and the data acquisition module acquires and outputs the on-chip frequency division ratio control signal sent by the tri-state interface circuit 40 to the data storage module. The data storage module is connected with the data acquisition module and is used for storing the data of the data acquisition module, so that a computer or other analysis instruments can conveniently read and analyze the data. The control signal generating circuit is used for generating an off-chip frequency division ratio control signal, and the control signal is sent to the chip through the tri-state interface circuit 40 in an off-chip mode.

The off-chip digital circuit 30 system can read the on-chip signals and generate signals to be sent into the chip, so that the on-chip digital circuit can be used for testing and analyzing the chip.

It should be noted that, the structure of the control signal generating circuit may refer to the on-chip frequency division ratio control signal generating circuit, so that the function of the frequency division ratio control signal in the on-chip digital circuit 20 system may be partially replaced. Other configurations may be employed to allow for comparative analysis with the on-chip digital circuitry 20 system.

In one embodiment, the off-chip digital circuit 30 off-chip frequency division ratio control signal generation logic may refer to the structure of the on-chip digital circuit 20, or may utilize the flexibility of the FPGA and its development platform, and one possible architecture is shown in fig. 9 below. As shown in fig. 9, the off-chip digital circuit 30 includes an FPGA clock network, a VIO IP core, and a frequency division ratio control signal storage unit. The outputs of the FPGA clock network and the VIO IP core are connected with the frequency division ratio control signal storage unit, and the FPGA clock network is used for providing corresponding clocks according to clock requirements of different modules. In the embodiment of the invention, the FPGA clock network is utilized to provide the clock signals required by the frequency division ratio control signal storage unit, and parameters such as clock frequency, phase and the like can be set and changed. The VIO IP core, namely Virtual input output, namely virtual IO, can monitor and drive signals in the FPGA in real time, and the number and the width of the input ports and the output ports can be set according to specific requirements. The frequency division ratio control signal storage unit, namely an exemplified storage unit, is used for storing the value of the frequency division ratio control signal.

In the embodiment of the invention, the signal interaction between the development platform and the interior of the FPGA is realized by using the VIO, and the enabling signal and the address signal of the frequency division ratio control signal storage unit are provided. In the off-chip mode, an FPGA clock network provides a working clock of an off-chip digital circuit, and the enable signal and the address signal of the frequency division ratio control signal storage unit are checked through the VIO IP to be changed, so that the expected off-chip frequency division ratio control signal is output.

Compared with the off-chip digital circuit 30 shown in fig. 8, the structure utilizes abundant clock network resources in the FPGA, can use clocks with different frequencies and phases, enhances the configurability and facilitates the debugging. And by using the VIO IP core in the FPGA, the interface is simple to operate and convenient for information interaction. The value stored in the frequency division ratio control signal storage unit can be changed, and the frequency division ratio control signal storage unit has the characteristics of being capable of being repeatedly configured, high in flexibility and the like.

In one embodiment, as shown in fig. 10-11, tri-state interface circuit 40 has two input ports and two output ports, including two modes of operation, i.e., on-chip and off-chip. The first input is coupled to an output on-chip divide ratio control signal of the on-chip digital circuitry 20 system and the second input is coupled to an output off-chip divide ratio control signal of the off-chip digital circuitry 30 system. The first output is coupled to the dual-mode frequency divider 15 and the second output is coupled to the off-chip digital circuitry 30.

When the mode switch is in-chip mode, the first output of the tri-state interface circuit 40 outputs an on-chip divide ratio control signal to the dual-mode frequency divider 15, while the second output outputs an on-chip divide ratio control signal to the off-chip digital circuitry 30.

When the mode switch is in off-chip mode, the first output terminal of the tri-state interface circuit 40 outputs the off-chip division ratio control signal of the off-chip digital circuit 30 system to the dual-mode frequency divider 15, and the second output terminal blocks the connection between the on-chip digital circuit 20 system and the off-chip digital circuit 30 system, i.e. is set to high resistance.

For the output port, there are three states, namely, an on-chip frequency division ratio control signal, an off-chip frequency division ratio control signal and a high resistance state.

In particular, a specific implementation of the tri-state interface circuit is shown in fig. 12:

as shown in fig. 12, the three-state interface circuit has an input port a, an output port B, and an input-output port INOUT; the EN signal represents the mode switch, EN is 1 for the on-chip mode, and EN is 0 for the off-chip mode.

When EN is 1, a is an input port, B is an output port, and INOUT is an output port. The input signal A is an on-chip frequency division ratio control signal, EN controls the transmission gate to be opened, and the input signal A is transmitted to the output port INOUT through the transmission gate through the combination logic 1, the combination logic 2 and the corresponding PMOS and NMOS. In addition, the input signal a is routed via wires to an output port B, which is connected to the chip pins, and to the on-chip dual-mode divider. Thus, when EN is 1, the tri-state interface circuit outputs an on-chip divide ratio control signal to the dual-mode divider, and also to the chip pins.

When EN is 0, a is an input port, B is an output port, and INOUT is an input port. The input signal A is an on-chip frequency division ratio control signal, and the EN controls the transmission gate to be turned off. The signal from the input port INOUT, i.e. the off-chip divide ratio control signal, is passed to the output port B via the combinational logic 3, combinational logic 4 and the corresponding PMOS, NMOS. The input port INOUT is connected to the chip pin and the output port B is connected to the on-chip dual-mode divider. Therefore, when EN is 0, the tri-state interface circuit outputs the off-chip division ratio control signal to the dual-mode frequency divider while blocking the connection of the input port a and the output port B, i.e., setting to high resistance.

The three-state interface circuit provided by the embodiment of the invention takes INOUT as an input/output port, and through multiplexing pins, the structure can read signals in the chip through the pins, and can turn off signal paths in the chip, so that signals are input into the chip from the chip pins. Therefore, the structure can reduce the number of chip pins, is convenient for chip test and debugging, and has the advantages of less hardware consumption, high flexibility and the like.

In one embodiment, the off-chip digital circuit 30 is integrated using an FPGA chip, and the phase-locked loop circuit 10, the on-chip digital circuit 20, and the tri-state interface circuit 40 are integrated using an ASIC chip.

It should be noted that, the pll circuit 10, the tri-state interface circuit 40, and the on-chip digital circuit 20 are implemented by ASIC, i.e. application specific integrated circuit, and the off-chip digital circuit 30 is implemented by FPGA, i.e. field programmable gate array, so that the advantages of small ASIC area, excellent performance, low power consumption, and high flexibility, programmability, and short development period of FPGA are combined with each other to make up for the complementary advantages to implement a frequency synthesis source with wide frequency range, fine frequency step, low phase noise, and fast frequency switching, and implement a function of continuous frequency adjustability or fixed frequency output, so as to adapt to the requirements of different pll systems.

In addition, as shown in fig. 13, a second embodiment of the present invention proposes a control method of an off-chip configurable fm continuous wave pll system, the control method comprising the steps of:

s10, outputting a digital control code to the phase-locked loop circuit by utilizing the on-chip digital circuit so as to control the phase-locked loop circuit to work;

s20, respectively utilizing the on-chip digital circuit and the off-chip digital circuit to generate an on-chip frequency division ratio control signal and an off-chip frequency division ratio control signal;

s30, when the tri-state interface circuit is in an on-chip mode, acquiring the on-chip frequency division ratio control signal through a first input end of the tri-state interface circuit, and forwarding the control signal to the phase-locked loop circuit through a first output end;

S40, when the tri-state interface circuit is in an off-chip mode, the off-chip frequency division ratio control signal is obtained through the second input end of the tri-state interface circuit and is forwarded to the phase-locked loop circuit through the first output end, and meanwhile the second output end of the tri-state interface circuit is set to be in a high-resistance state.

The tri-state interface circuit is arranged, so that an off-chip frequency division ratio control signal and an on-chip frequency division ratio control signal output by the off-chip digital circuit and the on-chip digital circuit can be respectively obtained, a digital control system for realizing the phase-locked loop frequency modulation continuous wave function can be realized in the on-chip digital circuit or the off-chip digital circuit, the function of the phase-locked loop system can be configured and controlled off-chip, and the off-chip digital circuit can replace part of functions of the on-chip digital circuit system; the digital systems outside the chip and outside the chip can input control signals to the dual-mode frequency divider, so that the stability, reliability and configurability of the whole phase-locked loop system are improved.

In one embodiment, in the step S20, the on-chip digital circuit is used to generate an on-chip frequency division ratio control signal, which includes the following steps:

writing operation of configuration registers in different modes of the phase-locked loop is carried out by utilizing the serial peripheral interface, writing information comprises a frequency dividing ratio set value, a time step set value, a frequency step set value, an address code initial value and a control initial value, and the modes of the phase-locked loop comprise a fixed frequency dividing ratio mode and a sweep frequency mode;

In one embodiment, the step S10: the digital control code is output to the phase-locked loop circuit by the on-chip digital circuit to control the phase-locked loop circuit to work, and the method comprises the following steps:

In an embodiment, the method further comprises:

and the control signal generating unit calculates working time and period required by the address code generating unit and the differential integral modulator in a frequency sweep mode according to the frequency sweep maximum value, the frequency sweep minimum value and the frequency sweep step, and realizes the function through the change of the control signal output by the control signal generating unit.

In an embodiment, the method further comprises:

the address code generating unit adjusts the period and the slope of the waveform in the sweep frequency mode according to the frequency step written in by the register in the serial peripheral interface and the time step output by the frequency dividing unit.

Specifically, the continuous change mode of the address code is determined by the waveform to be realized, when the sawtooth wave needs to be generated, the address code needs to be continuously increased, and when the preset sweep frequency maximum value is reached, the address code needs to be reset again, and the initial value is changed back to the sweep frequency minimum value. When the triangular wave needs to be generated, the address code needs to be continuously increased, and after the preset maximum value of the sweep frequency is reached, the address code is continuously reduced until the initial value is reduced, namely the minimum value of the sweep frequency. It should be noted that the frequency of the pll cannot be suddenly changed, otherwise, the pll will lose lock during the frequency sweep, so in the actual implementation of the triangular wave, a holding section is added, that is, after the address code is continuously increased to the preset frequency sweep maximum value, the holding section will remain unchanged for a period of time, and then continuously decrease until the initial value is the frequency sweep minimum value.

In an embodiment, the method further comprises:

It should be noted that, the control method of the off-chip configurable frequency-modulation continuous wave phase-locked loop system of the present invention is used to realize the control of the off-chip configurable frequency-modulation continuous wave phase-locked loop system, and other embodiments may refer to the above system embodiments, and are not repeated here.

In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.

While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.

Claims

1. The system comprises a phase-locked loop circuit, an on-chip digital circuit, an off-chip digital circuit and a tri-state interface circuit, wherein the output end of the on-chip digital circuit is connected with the phase-locked loop circuit, the output ends of the on-chip digital circuit and the off-chip digital circuit are respectively connected with a first input end and a second input end of the tri-state interface circuit to respectively output an on-chip frequency division ratio control signal and an off-chip frequency division ratio control signal to the tri-state interface circuit, the first output end of the tri-state interface circuit is connected with the phase-locked loop circuit, so that the on-chip frequency division ratio control signal is sent to the phase-locked loop circuit through the first output end when the tri-state interface circuit is in an on-chip mode, the off-chip frequency division ratio control signal is sent to the phase-locked loop circuit through the first output end when the tri-state interface circuit is in an off-chip mode, and the second output end of the tri-state interface circuit is set to be in a high-resistance state.

2. The off-chip configurable frequency-modulated continuous wave phase-locked loop system of claim 1, wherein the phase-locked loop circuit comprises a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator and a dual-mode frequency divider, wherein the output of the phase frequency detector is connected with the voltage-controlled oscillator after passing through the charge pump and the filter in sequence, the output of the voltage-controlled oscillator is respectively connected with the phase frequency detector and the on-chip digital circuit through the dual-mode frequency divider, and the output end of the on-chip digital circuit is connected with the voltage-controlled oscillator;

3. An off-chip configurable frequency modulated continuous wave phase locked loop system as set forth in claim 1, wherein said second output of said tri-state interface circuit is further coupled to an input of said off-chip digital circuit for outputting said on-chip divide ratio control signal to said off-chip digital circuit.

4. The off-chip configurable frequency-modulated continuous wave phase locked loop system of claim 1, wherein the on-chip digital circuit comprises a serial peripheral interface, a control signal generation unit, a frequency division unit, an address code generation unit, a frequency division ratio lookup table, a differential integral modulator, a frequency division ratio decoding unit, and a voltage controlled oscillator digital control code generation unit;

5. The off-chip configurable frequency-modulated continuous wave phase locked loop system of claim 4, wherein a control signal of said address code generation unit is 0 in said sweep mode and is changed from 0 to 1 in said fixed divide ratio mode; the time when the control signal of the address code generating unit is 0 is longer than the locking time of the phase-locked loop circuit.

6. The off-chip configurable frequency-modulated continuous wave phase locked loop system of claim 4, wherein the input signal of said voltage controlled oscillator digital control code generation unit comprises a reference clock, an address code transmitted by said address code generation unit, an address code initial value and a control initial value transmitted by said serial peripheral interface;

7. The off-chip configurable frequency-modulated continuous wave phase locked loop system of claim 1, wherein said control signal generating unit is connected to an external system for receiving an interface signal wave_start transmitted by said external system and transmitting an active frame_en signal to said external system when said interface signal wave_start is active, said interface signal wave_start being used for controlling a start time of a phase locked loop waveform generation, said frame_en signal being used as a flag signal of the phase locked loop waveform generation;

8. The off-chip configurable frequency-modulated continuous wave phase locked loop system of claim 3, wherein said off-chip digital circuit comprises a data acquisition module, a data storage module, and a control signal generation circuit; the input end of the data acquisition module is connected with the tri-state interface circuit, the output end of the data acquisition module is connected with the data storage module, and the output end of the control signal generation circuit is connected with the tri-state interface circuit;

9. The off-chip configurable frequency modulated continuous wave phase locked loop system of claim 8, wherein said off-chip digital circuitry is integrated using an FPGA chip and said phase locked loop circuitry, said on-chip digital circuitry, and said tri-state interface circuitry are integrated using an ASIC chip.

10. A method of controlling an off-chip configurable frequency-modulated continuous wave phase locked loop system according to any one of claims 1 to 9, said method comprising:

when the tri-state interface circuit is in an on-chip mode, the on-chip frequency division ratio control signal is obtained through a first input end of the tri-state interface circuit and is forwarded to the phase-locked loop circuit through a first output end;

when the tri-state interface circuit is in an off-chip mode, the off-chip frequency division ratio control signal is obtained through the second input end of the tri-state interface circuit and is forwarded to the phase-locked loop circuit through the first output end, and meanwhile the second output end of the tri-state interface circuit is set to be in a high-resistance state.

11. The method of controlling an off-chip configurable frequency-modulated continuous wave phase locked loop system of claim 10, wherein generating an on-chip divide ratio control signal using the on-chip digital circuit comprises:

12. The method of claim 11, wherein the outputting a digital control code to the pll circuit using the on-chip digital circuit to control the pll circuit comprises:

13. The method of claim 11, wherein the address code generating unit adjusts the period and slope of the waveform in the sweep mode according to the frequency step written in the register in the serial peripheral interface and the time step output by the frequency dividing unit.

14. The control method of an off-chip configurable frequency-modulated continuous wave phase locked loop system according to claim 13, wherein a control signal of said address code generation unit is 0 in said sweep mode, and the control signal of said address code generation unit is changed from 0 to 1 in said fixed frequency division ratio mode; the time when the control signal of the address code generating unit is 0 and the time when the control signal of the address code generating unit is 1 are adjustable, and the time when the control signal of the address code generating unit is 0 is longer than the locking time of the phase-locked loop circuit.

15. The method of controlling an off-chip configurable frequency-modulated continuous wave phase locked loop system of claim 11, said method further comprising: