CN116108789B - Analog circuit layout structural characteristic representation restoration method and component - Google Patents
Analog circuit layout structural characteristic representation restoration method and component Download PDFInfo
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Abstract
The invention provides a method and a component for restoring structural characteristic representation of an analog circuit layout, which comprises the following steps: splitting domain layout vector coding knowledge to obtain netlist vectorization data and domain vectorization data; generating netlist information describing the connection relation of circuit elements by using the netlist vectorization data; generating layout information describing the layout positions of the circuit elements by using the layout vectorization data; the layout information corresponds to the netlist information one by one; generating a netlist describing the connection relation of the circuit elements by using the netlist information; and generating a layout describing the layout positions of the circuit elements by using the layout information. The invention can better utilize the vectorization knowledge of the analog circuit structure, thereby meeting the demands of digital utilization and interpretability of the analog circuit layout knowledge, enabling the design of the analog circuit layout to be quickly checked and delivered, and improving the design efficiency of the analog circuit.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to a method and a component for restoring structural characteristic representation of an analog circuit layout.
Background
The new generation of artificial intelligence provides a feasible path for realizing digital intelligent upgrading transformation and cross-over development of various industries, and electronic design automation (Electronic Design Automation, EDA) technology is used as a basic tool of integrated circuit design, and the back-end design of the new generation of artificial intelligence has realized high automation due to relatively simple constraint in digital integrated circuit design. The automation degree of the analog integrated circuit layout is far lower than that of the digital integrated circuit, and most of analog integrated circuits are still designed manually at present due to various problems of constraint complexity, structural diversity of circuit structures and the like in the analog integrated circuit. The layout work lacking the automatic auxiliary design becomes time-consuming and labor-consuming and is easy to make mistakes, the layout delivery period is prolonged, and the design of the analog circuit becomes a chip research and development bottleneck.
With the continuous development of chip industry and artificial intelligence technology, practitioners and scholars begin to focus on solving various problems in the design of analog chips by utilizing the artificial intelligence technology, the circuit structure contains abundant expert experience, the circuit structure is expressed in a structured manner, and the method is a key link for realizing multiplexing of the circuit structure and application of the expert experience, however, the processable data form of the artificial intelligence technology is greatly different from the conventional visible data format.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, and provides a method and a component for restoring structural characteristic representation of an analog circuit layout, so that the analysis of knowledge vector data of the circuit layout can be rapidly realized, the usability and the interpretability of the vectorized representation of the layout are improved, and the design of the analog circuit is quickened.
The invention provides a method for restoring structural characteristic representation of an analog circuit layout, which comprises the following steps: splitting domain layout vector coding knowledge to obtain netlist vectorization data and domain vectorization data; generating netlist information describing the connection relation of circuit elements by using the netlist vectorization data; generating layout information describing the layout position of the circuit element by using the layout vectorization data; the layout information corresponds to the netlist information one by one; the netlist information is generated by vectorizing and decoding vectorized data of the netlist, and the layout information is generated by vectorizing and decoding vectorized data of the layout; generating a netlist describing the connection relation of circuit elements by using the netlist information; generating a layout describing the layout position of the circuit element by using the layout information; the netlist is generated by post-processing of the netlist information, and the layout is generated by post-processing of the layout information.
According to the method for restoring the structural characteristic representation of the analog circuit layout, the netlist at least comprises a module object, a pin object, a network cable object, a port object and a clock object.
According to the method for representing and restoring the structural characteristics of the analog circuit layout, the layout at least comprises a device size, a device position, a potential, a voltage domain, isolation, a wiring position and a line width line distance.
According to the method for restoring structural characteristic representation of analog circuit layout, which is provided by the invention, the netlist describing the connection relation of circuit elements is generated by utilizing the netlist information, and the method comprises the following steps: and deleting blank rows in the netlist information, and adjusting the format of the netlist information to obtain a netlist describing the connection relation of circuit elements.
According to the method for restoring the structural characteristic representation of the analog circuit layout, the layout for describing the layout position of the circuit element is generated by using the layout information, and the method comprises the following steps: and identifying the layout information through a preset read-write rule to obtain the layout describing the layout position of the circuit element.
According to the method for restoring structural characteristic representation of analog circuit layout, netlist information describing connection relation of circuit elements is generated by utilizing netlist vectorization data, and the method comprises the following steps: the netlist vectorization data is trained based on local information extraction and a global sparse transducer model to obtain the netlist information describing circuit element connection relationships.
According to the method for restoring the structural characteristic representation of the analog circuit layout, the layout information describing the layout position of the circuit element is generated by using the layout vectorization data, and the method comprises the following steps: and training the layout vectorization data based on local information extraction and a global sparse transducer model to obtain layout information describing the layout position of the circuit element.
The invention also provides a system for restoring the structural characteristic representation of the analog circuit layout, which comprises the following steps: the data splitting module is used for splitting domain layout vector coding knowledge to obtain netlist vectorization data and domain vectorization data; the netlist data decoding module is used for generating netlist information describing the connection relation of circuit elements by using the netlist vectorization data, wherein the netlist information is generated by vectorizing and decoding the netlist vectorization data; the layout data decoding module is used for generating layout information describing the layout position of the circuit element by using the layout vectorization data, wherein the layout information is generated by vectorization decoding of the layout vectorization data; the layout information corresponds to the netlist information one by one; the netlist information post-processing module is used for generating a netlist describing the connection relation of circuit elements by utilizing the netlist information, wherein the netlist is generated by post-processing the netlist information; the layout information post-processing module is used for generating a layout describing the layout position of the circuit element by utilizing the layout information, wherein the layout is generated by post-processing the layout information.
The invention also provides an electronic device, which comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor realizes the method for restoring the structural characteristic representation of the analog circuit layout when executing the program.
The present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a method of reducing a structural representation of a simulated circuit layout as described in any of the above.
The invention provides a method and a component for restoring structural characteristic representation of an analog circuit layout, which comprises the following steps: splitting domain layout vector coding knowledge to obtain netlist vectorization data and domain vectorization data; generating netlist information describing the connection relation of circuit elements by using the netlist vectorization data; generating layout information describing the layout positions of the circuit elements by using the layout vectorization data; the layout information corresponds to the netlist information one by one; the netlist information is generated by vectorizing and decoding netlist vectorization data, and the layout information is generated by vectorizing and decoding layout vectorization data; generating a netlist describing the connection relation of the circuit elements by using the netlist information; generating a layout describing the layout position of the circuit element by using the layout information; the netlist is generated by post-processing netlist information, and the layout is generated by post-processing layout information. The invention can better utilize the vectorization knowledge of the analog circuit structure, thereby meeting the demands of digital utilization and interpretability of the analog circuit layout knowledge, enabling the design of the analog circuit layout to be quickly checked and delivered, and improving the design efficiency of the analog circuit.
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In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic flow chart of a method for restoring structural characteristic representation of an analog circuit layout;
FIG. 2 is a schematic diagram of a local information extraction and global sparsification based transducer model provided by the present invention;
FIG. 3 is a schematic diagram of multi-layer convolution based local information extraction provided by the present invention;
FIG. 4 is a diagram showing the comparison of the self-attentive mechanisms of a transducer model according to the present invention;
FIG. 5 is a schematic diagram of the self-attention mechanism computation of the globally sparsified transducer provided by the present invention;
FIG. 6 is a schematic diagram of a calculation process of a global sparsification and softMax module provided by the invention;
FIG. 7 is a schematic diagram of a system for restoring structural characteristics of an analog circuit layout;
fig. 8 is a schematic structural diagram of an electronic device provided by the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The following describes a method and components for restoring structural characteristics of an analog circuit layout according to the present invention with reference to fig. 1 to 8.
Referring to fig. 1, fig. 1 is a schematic flow chart of a method for representing and restoring structural characteristics of an analog circuit layout according to the present invention.
The invention provides a method for restoring structural characteristic representation of an analog circuit layout, which comprises the following steps:
101: splitting domain layout vector coding knowledge to obtain netlist vectorization data and domain vectorization data;
102: generating netlist information describing the connection relation of circuit elements by using the netlist vectorization data;
generating layout information describing the layout positions of the circuit elements by using the layout vectorization data; the layout information corresponds to the netlist information one by one;
the netlist information is generated by vectorizing and decoding netlist vectorization data, and the layout information is generated by vectorizing and decoding layout vectorization data;
103: generating a netlist describing the connection relation of the circuit elements by using the netlist information;
generating a layout describing the layout position of the circuit element by using the layout information;
the netlist is generated by post-processing netlist information, and the layout is generated by post-processing layout information.
Considering that the structural design of analog circuits is still mostly designed manually at present, but the problems of high labor cost and long exchange period exist. In order to solve the technical problems in the prior art, the invention provides a method for representing and restoring structural characteristics of an analog circuit layout, which comprises the steps of firstly splitting layout vector coding knowledge to obtain netlist vectorization data and layout vectorization data, then vectorizing and decoding the netlist vectorization data to obtain netlist information describing connection relation of circuit elements, vectorizing and decoding the layout vectorization data to obtain layout information describing layout positions of the circuit elements, wherein the layout information has a one-to-one correspondence with the netlist information, and finally obtaining a netlist and a layout meeting rule requirements by post-processing editing and finishing the netlist information and the layout information.
In addition, the netlist vectorized data can be vectorized and decoded by a netlist decoder, and the layout vectorized data can be vectorized and decoded by a layout decoder, and the invention is not particularly limited herein.
Based on the above embodiments:
as a preferred embodiment, the netlist includes at least a module object, a pin object, a net wire object, a port object, and a clock object.
It should be noted that, the netlist (netlist) is a file generated in the circuit design process, for example, a txt format file, where the netlist has 5 kinds of important objects, namely, a module (cell), a pin (pin), a network cable (net), a port (port) and a clock (clock), and the netlist includes: module objects, pin objects, net wire objects, port objects, and clock objects.
As a preferred embodiment, the layout includes at least device size, device location, potential, voltage domain, isolation, routing location, and linewidth spacing.
It should be noted that, the layout (layout) is used to describe the layout of circuit elements, and is a file generated in the circuit design process, for example, a GDSII format file, and the layout has important characteristics of device size, device position, potential, voltage domain, isolation, routing position, line width and line distance, etc.
As a preferred embodiment, generating a netlist describing the connection relationship of circuit elements using netlist information, comprising: and deleting blank rows in the netlist information, and adjusting the format of the netlist information to obtain a netlist describing the connection relation of circuit elements.
For example, character strings, blank lines or paragraph marks, etc. in the netlist information txt file, which are irrelevant to the module, pin, wire, port and clock information, are deleted.
As a preferred embodiment, generating a layout describing layout positions of circuit elements using layout information includes: and identifying layout information through a preset read-write rule to obtain a layout describing the layout position of the circuit element.
For example, the layout information GDSII format file is read according to a preset read-write rule and then displayed to obtain a block diagram containing devices and network cable nodes, so that the block diagram is aligned with character strings representing module objects, pin objects, network cable objects, port objects and clock objects in a netlist in a unified manner, and one-to-one correspondence between netlist information and layout information is realized.
As a preferred embodiment, generating netlist information describing circuit element connection relationships using netlist vectorization data includes: the netlist vectorization data is trained based on local information extraction and a global sparse transducer model to obtain netlist information describing the connection relationship of circuit elements.
As a preferred embodiment, generating layout information describing layout positions of circuit elements using layout vectorization data includes: and training the layout vectorization data based on the local information extraction and the global sparse transducer model to obtain layout information describing the layout position of the circuit element.
Referring to fig. 2, fig. 2 is a schematic diagram of a local information extraction and global sparse transform model according to the present invention.
Specifically, the decoder uses a transducer model as a backbone, unlike a recurrent neural network, the transducer does not need to rely on past states to learn transition relationships between sequences, can efficiently process longer input sequences, and has proven effectiveness in sequence prediction, but the following problems still remain:
(1) In the sequence prediction task, local correlation between adjacent projects and remote dependency between long-distance projects have a great influence on a prediction result. The Transformer has the advantage of being capable of directly capturing remote dependency information among long-distance projects, but because the process only calculates the correlation among any two projects and does not consider the influence of adjacent projects on a calculation result, the Transformer model ignores local correlation information among the adjacent projects.
(2) There is some information in the sequence that is irrelevant to the prediction task, which may be noise, which does not contribute to the prediction effect at all, and may even have a negative impact. The transducer calculates the attention score among projects through a self-attention mechanism, and the value size reflects the attention degree of the attention of the model. When the score value is low, the representation model is less concerned with its corresponding information, in contrast, this part may be irrelevant noise information for the prediction task, but the transducer does not cancel this part of the information. However, after the attention score is generated, the attention score can participate in subsequent operation no matter the value of the attention score, so that the prediction effect of the model is affected. In order to solve the two problems, improvement work of a transducer is provided, and a transducer model based on local information extraction and global sparsification is provided.
The method mainly comprises the following steps of extracting based on local information and dividing a global sparse transducer model into two sub-modules: a local module and a global module. These two modules are briefly described below, respectively.
A local module. Aiming at the problem that the transducer model ignores local related information between adjacent projects, local connection characteristics of convolution operation are utilized in a local module, the local related information between the adjacent projects is captured by utilizing multi-layer convolution, and then the local related information is fused to global dependent information of a learning sequence in a architecture of the transducer, so that the problems of local conversion between the adjacent projects and complex conversion between remote projects are solved, and the defect of the transducer model in local information extraction is overcome.
And a global module. In order to reduce the influence of noise information in a sequence on a prediction result, a global module improves a self-attention mechanism in a transducer, and a global sparse transducer model is provided. The model converts global attention focus into global sparse focus by introducing a sparse function, and adaptively selects and reserves important information to improve the attention concentration degree of global context; meanwhile, irrelevant information is deleted, so that the purpose of eliminating noise is achieved.
Referring to fig. 3, fig. 3 is a schematic diagram of local information extraction based on multi-layer convolution according to the present invention.
The self-attention mechanism of the transducer can directly focus on all items in the sequence, any one item can be calculated with all other items in the sequence no matter the distance between the items or the distance between the items, and the operation is completed through weighting and summation, so that the calculation process can capture the global dependency information of the sequence. However, since the process only calculates the correlation between any two items, the influence of the adjacent items on the calculation result is not considered, and thus the transducer model ignores the local correlation information between the adjacent items. Because convolution operations in convolutional neural networks have the property of local connections, and adjacent items in the sequence also have the property of local correlations, the convolution operations are well suited for extracting local features of the sequence to learn patterns of internal correlations of the sequence.
Based on the problem analysis, the local information between adjacent projects is extracted by utilizing convolution operation and then fused to the global dependency information of the learning sequence in the architecture of the transducer, so that the problems of local conversion between adjacent projects and complex conversion between remote projects are solved, and the defect of the transducer model in local information extraction is overcome.
Sequence data is typically represented in one-dimensional data form and is therefore processed using one-dimensional convolution in a manner that scans the entire sequence using one-dimensional convolution kernel. However, for a single convolution operation, the capability of extracting local information between adjacent items in a sequence is limited, on one hand, the feeling is limited due to single-layer convolution, and on the other hand, the sequence mode learned by a model is fixed due to the operation of a single convolution kernel. To more fully and effectively mine the local related information of the sequence, a multi-layer convolution operation is adopted, convolution kernels with different sizes are configured in each layer of convolution operation, and then the maximum is passedPooling (Max Pooling) performs feature selection on information calculated by different convolution kernels. For sequences
Which embeds the representation +.>
After the convolution processing, the outputs of the layers are denoted as +.>
. In the case of partial information extraction of a sequence by using multi-layer convolution, it is assumed that the number of convolution layers used isgThe number of convolution kernels configured by each layer of convolution operation is ℎ, and the convolution kernels are +.>
Whereinl h Is a convolution kernelW lh h Corresponding dimensions. Based on the firstjLayer convolution with input +.>
The calculation procedure of the convolution operation.
In order to avoid the problem of gradient disappearance which is easy to occur after the network deepens, and simultaneously ensure that the distribution of the intermediate layer results is consistent, batch normalization (Batch Normalization, BN for short) and Relu activation functions are added after the convolution operation. Thus, the convolution operation, batch normalization, and the Relu activation function together constitute a convolution block. Through the above processing, output can be obtainedSE (j) Its calculation process.
Meanwhile, in order to make the model pay attention to the current difference part, the degradation phenomenon is slowed down, residual connection is performed after convolution processing of each layer, and the residual connection result is used as input of the next layer. Since there is an imbalance in the dimensions of the input and output vectors before and after the convolution process, the output is normalized by zero padding at both ends of the sequence.
By the multi-layer convolution operation, the sequence can be obtained
Output result of (2)
WhereingIndicating the number of convolution layers;LE i g（） involving the provision ofL i Local correlation information between adjacent items of>
。
After the local information extraction processing based on the multi-layer convolution, the result is outputSE g() Fusion into a transducer enables the model to learn the global dependency information of the sequence. At this time, when the self-attention mechanism of the transducer model calculates the correlation, the influence of adjacent items on the calculation result is considered, and the correlation between any two items is not calculated, so that the problems of local conversion between adjacent items and complex conversion between remote items are solved, and the defect of the transducer model in local information extraction is overcome.
Global sparsified transducer model
The self-attention mechanism in the transducer learns the global dependency information in the sequence by modeling all items in the sequence, but the predictive effect of the model is also affected by irrelevant information in the sequence. Such irrelevant information may be noise information, which does not contribute to the prediction effect at all, and may even have a negative impact. To solve this problem, an improvement in the self-attention mechanism is proposed, and a global sparsity transducer model. The model converts global attention focus into global sparse focus by introducing a sparse function, and adaptively selects and reserves important information to improve the attention concentration degree of global context; meanwhile, irrelevant information is deleted, so that the purpose of eliminating noise is achieved.
(1) Global sparsification function
From the above, the sequence
After being extracted based on local information, the output is that
WhereingIndicating the number of convolutions. In the self-attention mechanism, willSE g() Converted into its input: queryingQKey and keyKSum valueV. Assuming its output asHThe embedding dimension is->
The SoftMax function is denoted +.>
The calculation formula of the self-attention mechanism.
Let the attention score matrix be
Which is a two-dimensional matrix,nis the length of the sequence. ProjectL i With respect to the sequenceSAttention score of->
The method comprises the steps of carrying out a first treatment on the surface of the ProjectL i With respect to the sequenceSSome item in (a)L j Attention score of->
。
Attention scoreSC ij The value of (2) reflects the attention degree of the attention of the model, and when the score is lower, the model is less concerned about the corresponding modelV j In contrast, this portion of information may be uncorrelated noise information for the prediction task. But in the process of generatingSC ij After all, no matterSC ij How the value of the model is, the model can participate in subsequent operation, and then the detection effect of the model is affected. Therefore, from the perspective of improving global up-down attention, the model should be allowed to retain important information with larger attention, while deleting irrelevant information with smaller attention.
Based on the above analysis of the problem, a global sparsified transducer model is proposed. The model generates a attention score matrix in the self-attention mechanism, unlike the original transducerSCThen, the scoring matrix is not directly usedSCThe method is put into a SoftMax function for normalization operation, and is transmitted into a global sparsing module (global Spare) for processing. The global sparsification module is used for introducing adaptive parametersθGlobal sparsification functionG θ （x) Attention score matrixSCAnd (3) performing a thinning operation so that important information is reserved and irrelevant information is deleted.
Referring to fig. 4, fig. 4 is a schematic diagram showing the comparison of the self-attentiveness mechanisms of the transducer model according to the present invention.
Specifically, a global sparsification functionG θ （x) By comparing the concentration score with the adaptive parametersθTo determine whether information in the attention score matrix is retained. When the score value is greater thanθWhen the corresponding information of the part is relatively important, the model keeps the information of the part; conversely, when the score of attention is less than or equal toθWhen the information describing the part is less relevant and is more likely to be noise information, the model will delete the part of the information.
Referring to fig. 5, fig. 5 is a schematic diagram illustrating calculation of a self-attention mechanism of a global sparse transducer according to the present invention.
Global sparsification processing functionG θ （x) The expression form of (a) is as follows:
when calculating itemsL i With respect to itemsL j When the attention score of (2) is found:
expansion to computationL i And sequence
And adding a SoftMax function for normalization to obtain the attention score of (2):
due to
The establishment is so that:
when (when)
When (I)>
The model retains the partial information;
when (when)
When (I)>
The model deletes the partial information;
after the above treatment, the item can be obtainedL i Output of (2):
and then extends it to the whole sequence
The output of the self-attention mechanism is available:
wherein, the liquid crystal display device comprises a liquid crystal display device,
，G θ （x) In order to sparsify the function,θsigma is a SoftMax function for the adaptive parameter.
The above is the self-attention mechanism calculation process of the global sparsified transducer. The global sparsification Transformer can convert global attention into global sparsification attention, and the important information is self-adaptively reserved by introducing a global sparsification function, so that the attention concentration degree of a global context is improved; meanwhile, irrelevant information is deleted, so that the irrelevant information does not participate in subsequent calculation, and the aim of eliminating noise is fulfilled.
(2) Implementation of global sparsification and SoftMax modules
Referring to fig. 6, fig. 6 is a schematic diagram of a global sparsification and SoftMax module calculation process provided in the present invention.
In the network structure, the model cannot be directly based on the global sparsification functionG θ （x) Information transfer is performed on the expression form of (2), and thus, the expression form is aimed atG θ （x) A corresponding numerical conversion method is designed to complete the functions of the global sparsification and softMax module, and the calculation process of the module is shown in the figure. Model attention score matrixSCPerforming numerical conversion to calculate
。
Specifically, first, attention score matrixSCFirst and self-adaptive parametersθPerforming difference operation, and then placing the obtained difference into an indication functionsignAnd (3) marking the symbol, wherein the difference value is marked as 1 if the difference value is larger than 0, and is marked as 0 if the difference value is smaller than or equal to 0. Then, after subtracting 1 from the sign, multiplying the sign with an infinite value to convert the value of 1 into 0 and convert the value of 0 into a negative infinite value. Finally, attention score matrixSCAdding the values, and reserving the value corresponding to the important information after the softMax function is carried out; the value corresponding to the irrelevant information is changed to 0 (meaning that the part of information does not participate in the subsequent operation of the model), so that the functions of global sparsification and SoftMax modules are completed.
Wherein the method comprises the steps ofINFRepresenting an infinite number of values to be taken,sign（x) To indicate a function.
Referring to fig. 7, fig. 7 is a schematic structural diagram of a system for representing and restoring structural characteristics of an analog circuit layout according to the present invention.
The invention also provides a system for restoring the structural characteristic representation of the analog circuit layout, which comprises the following steps:
the data splitting module 701 is configured to split the layout vector coding knowledge to obtain netlist vectorization data and layout vectorization data;
a netlist data decoding module 702, configured to generate netlist information describing a connection relationship of circuit elements by using netlist vectorization data, where the netlist information is generated by performing vectorization decoding on the netlist vectorization data;
the layout data decoding module 703 is configured to generate layout information describing a layout position of the circuit element by using the layout vectorization data, where the layout information is generated by performing vectorization decoding on the layout vectorization data, and the layout information corresponds to the netlist information one by one;
a netlist information post-processing module 704, configured to generate a netlist describing a connection relationship of circuit elements by using netlist information, where the netlist is generated by post-processing the netlist information;
the layout information post-processing module 705 is configured to generate a layout describing a layout position of the circuit element by using the layout information, where the layout is generated by post-processing the layout information.
The netlist data decoding module 702 and the layout data decoding module 703 can use the public data set to train the decoder, then use the parameters trained in the public data set in a transfer learning mode, and initialize the decoder to retrain on the small-scale standard layout data set to obtain the trained decoder. And editing and sorting the decoded netlist information and layout information to obtain the final netlist and layout meeting the rule requirements.
For the description of the system for representing and restoring the structural characteristics of the analog circuit layout provided by the invention, refer to the above method embodiment, and the description of the invention is omitted here.
Fig. 8 illustrates a physical structure diagram of an electronic device, as shown in fig. 8, which may include: a processor 801, a communication interface (Communications Interface) 802, a memory 803, and a communication bus 804, wherein the processor 801, the communication interface 802, and the memory 803 communicate with each other through the communication bus 804. The processor 801 may invoke logic instructions in the memory 803 to perform a simulated circuit layout structural feature representation restoration method comprising: splitting domain layout vector coding knowledge to obtain netlist vectorization data and domain vectorization data; generating netlist information describing the connection relation of circuit elements by using the netlist vectorization data; generating layout information describing the layout positions of the circuit elements by using the layout vectorization data; the layout information corresponds to the netlist information one by one; the netlist information is generated by vectorizing and decoding netlist vectorization data, and the layout information is generated by vectorizing and decoding layout vectorization data; generating a netlist describing the connection relation of the circuit elements by using the netlist information; generating a layout describing the layout position of the circuit element by using the layout information; the netlist is generated by post-processing netlist information, and the layout is generated by post-processing layout information.
Further, the logic instructions in the memory 803 described above may be implemented in the form of software functional units and may be stored in a computer readable storage medium when sold or used as a stand alone product. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method of the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
In another aspect, the present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, is implemented to perform the method for restoring structural characteristics representation of an analog circuit layout provided by the above methods, the method comprising: splitting domain layout vector coding knowledge to obtain netlist vectorization data and domain vectorization data; generating netlist information describing the connection relation of circuit elements by using the netlist vectorization data; generating layout information describing the layout positions of the circuit elements by using the layout vectorization data; the layout information corresponds to the netlist information one by one; the netlist information is generated by vectorizing and decoding netlist vectorization data, and the layout information is generated by vectorizing and decoding layout vectorization data; generating a netlist describing the connection relation of the circuit elements by using the netlist information; generating a layout describing the layout position of the circuit element by using the layout information; the netlist is generated by post-processing netlist information, and the layout is generated by post-processing layout information.
The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. The method for restoring the structural characteristic representation of the analog circuit layout is characterized by comprising the following steps of:
splitting domain layout vector coding knowledge to obtain netlist vectorization data and domain vectorization data;
generating netlist information describing the connection relation of circuit elements by using the netlist vectorization data;
generating layout information describing the layout position of the circuit element by using the layout vectorization data; the layout information corresponds to the netlist information one by one;
the netlist information is generated by vectorizing and decoding vectorized data of the netlist, and the layout information is generated by vectorizing and decoding vectorized data of the layout;
generating a netlist describing the connection relation of circuit elements by using the netlist information;
generating a layout describing the layout position of the circuit element by using the layout information;
the netlist is generated by post-processing of the netlist information, and the layout is generated by post-processing of the layout information.
2. The method for restoring a structured property representation of an analog circuit layout according to claim 1, wherein the netlist comprises at least a module object, a pin object, a net wire object, a port object and a clock object.
3. The method for restoring a structural characterization representation of an analog circuit layout according to claim 1, wherein the layout comprises at least device size, device location, potential, voltage domain, isolation, routing location, and linewidth spacing.
4. The method for reducing structural feature representation of analog circuit layout according to claim 1, wherein generating a netlist describing connection relations of circuit elements by using the netlist information comprises:
and deleting blank rows in the netlist information, and adjusting the format of the netlist information to obtain a netlist describing the connection relation of circuit elements.
5. The method for restoring structural characteristic representation of analog circuit layout according to claim 1, wherein generating a layout describing layout positions of circuit elements by using the layout information comprises:
and identifying the layout information through a preset read-write rule to obtain the layout describing the layout position of the circuit element.
6. The method for restoring structural characteristics representation of analog circuit layout according to any one of claims 1 to 5, wherein generating netlist information describing connection relations of circuit elements by using the netlist vectorization data comprises:
the netlist vectorization data is trained based on local information extraction and a global sparse transducer model to obtain the netlist information describing circuit element connection relationships.
7. The method for restoring structural feature representation of analog circuit layout according to any one of claims 1 to 5, wherein generating layout information describing layout positions of circuit elements by using the layout vectorization data comprises:
and training the layout vectorization data based on local information extraction and a global sparse transducer model to obtain layout information describing the layout position of the circuit element.
8. An analog circuit layout structured property representation restoration system, comprising:
the data splitting module is used for splitting domain layout vector coding knowledge to obtain netlist vectorization data and domain vectorization data;
the netlist data decoding module is used for generating netlist information describing the connection relation of circuit elements by using the netlist vectorization data, wherein the netlist information is generated by vectorizing and decoding the netlist vectorization data;
the layout data decoding module is used for generating layout information describing the layout position of the circuit element by using the layout vectorization data, wherein the layout information is generated by vectorization decoding of the layout vectorization data, and the layout information corresponds to the netlist information one by one;
the netlist information post-processing module is used for generating a netlist describing the connection relation of circuit elements by utilizing the netlist information, wherein the netlist is generated by post-processing the netlist information;
the layout information post-processing module is used for generating a layout describing the layout position of the circuit element by utilizing the layout information, wherein the layout is generated by post-processing the layout information.
9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the method for restoring structural representation of structural features of an analog circuit layout as claimed in any one of claims 1 to 7 when the program is executed by the processor.
10. A non-transitory computer readable storage medium having stored thereon a computer program, which when executed by a processor implements the analogue circuit layout structural feature representation restoration method according to any one of claims 1 to 7.
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