CN113222162B - Method and system for judging mobility of quantum logic gate - Google Patents
Method and system for judging mobility of quantum logic gate Download PDFInfo
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Abstract
The invention discloses a method and a system for judging the mobility of a quantum logic gate, and belongs to the technical field of quantum computing. The invention acquires a target quantum logic gate and a moving mode in a quantum circuit, constructs the moving quantum circuit on the basis, determines a related quantum logic gate, respectively determines a first quantum circuit and a second quantum circuit according to the sequence of the related quantum logic gate in the quantum circuit and the sequence of the moving quantum circuit, and determines the movability of the target quantum logic gate by judging whether the first quantum circuit and the second quantum circuit are equivalent or not.
Description
Technical Field
The invention belongs to the technical field of quantum computing, and particularly relates to a method and a system for judging the mobility of a quantum logic gate.
Background
Quantum program is a series of instruction sequences for operating quantum logic gates according to a certain time sequence, and is a program for representing quantum bits and evolution thereof written by classical languages, wherein the quantum bits, the quantum logic gates and the like related to quantum computing are all represented by corresponding classical codes. The execution process of the quantum program, that is, the process of executing the quantum circuit, more specifically, the process of executing all quantum logic gates according to a certain time sequence, and finally, the result is often required to be read out through quantum measurement operation. The timing of each quantum logic gate in the quantum circuit corresponds to the time sequence in which each quantum logic gate is executed.
In the related art, in order to simplify quantum computation, it is generally necessary to optimize a quantum circuit, and optimize a quantum circuit with high computation complexity into a quantum circuit with low computation complexity, which requires determining whether a quantum logic gate in the quantum circuit can be moved or whether the relative order of the quantum logic gate can be changed, and there is no technology for determining the mobility of the quantum logic gate at present.
Disclosure of Invention
Aiming at the problem that the mobility of a quantum logic gate in a quantum circuit cannot be judged at present, the invention provides a method and a system for judging the mobility of the quantum logic gate.
A judging method for the mobility of a quantum logic gate comprises the following steps:
acquiring a target quantum logic gate and a moving mode in a quantum circuit;
constructing a quantum circuit after moving according to the quantum circuit, the target quantum logic gate and the moving mode;
determining a quantum logic gate associated with a qubit of a target quantum logic gate as a relevant quantum logic gate, wherein the associated quantum logic gate refers to a quantum logic gate in which the quantum bit has an intersection with a qubit of the target quantum logic gate;
determining a first quantum circuit and a second quantum circuit constructed by the related quantum logic gates respectively, wherein the sequence of the related quantum logic gates in the first quantum circuit is the same as that in the quantum circuit, and the sequence of the related quantum logic gates in the second quantum circuit is the same as that in the quantum circuit after movement;
Judging whether the first quantum circuit is equivalent to the second quantum circuit or not;
if so, determining that the target quantum logic gate is movable.
Further, wherein:
the target quantum logic gate comprises a first target quantum logic gate and a second target quantum logic gate;
the moving mode comprises one of the following steps:
the first and second target quantum logic gates exchange positions, the first target quantum logic gate moves to insert into a position adjacent to the second target quantum logic gate, and the first target quantum logic gate moves to replace the second target quantum logic gate.
Further, according to the quantum circuit, the target quantum logic gate and the moving mode, constructing a moved quantum circuit, including:
generating the quantum circuit copy and the target quantum logic gate copy;
determining a target position for placing the target quantum logic gate copy in the quantum circuit copy according to the moving mode;
adding the target quantum logic gate replica to the quantum wire replica at the target location;
deleting the target quantum logic gate in the quantum circuit replica;
The new quantum wire replica is determined as a shifted quantum wire.
Further, the determining the quantum logic gate associated with the qubit of the target quantum logic gate as the relevant quantum logic gate includes:
according to the target quantum logic gate, a first position in the quantum circuit and a second position in the moved quantum circuit are respectively determined, wherein the first position refers to the position of the target quantum logic gate in the quantum circuit, and the second position refers to the position of the target quantum logic gate in the moved quantum circuit;
determining a third position corresponding to the second position in the quantum circuit;
acquiring all quantum logic gates corresponding to the first position to the third position in the quantum circuit;
and determining quantum logic gates in which the quantum bits in all the quantum logic gates and the quantum bits in the target quantum logic gate are intersected as relevant quantum logic gates.
Further, the determining whether the first quantum wire is equivalent to the second quantum wire includes:
judging whether the related quantum logic gate only comprises one quantum logic gate or not, wherein the quantum logic gate is the target quantum logic gate;
If yes, the first quantum circuit is equivalent to the second quantum circuit.
Further, the determining whether the first quantum wire is equivalent to the second quantum wire includes:
executing the first quantum circuit to obtain a calculation result mat1;
executing the second quantum circuit to obtain a calculation result mat2;
determining whether mat1 and mat2 match mat1=e iα mat2, where e iα ＝cosα+isinα，i 2 -1, alpha is any angle value in 0-2 pi;
if it is matched with mat1=e iα mat2, the first quantum wire is equivalent to the second quantum wire.
Further, the executing the second quantum circuit to obtain a calculation result mat2 includes:
determining a simplified quantum logic gate group in the second quantum circuit, wherein the simplified quantum logic gate group is at least two quantum logic gates in the second quantum circuit;
determining a quantum logic gate equivalent to the simplified quantum logic gate set as a substitute quantum logic gate;
determining a third quantum circuit corresponding to the second quantum circuit according to the simplified quantum logic gate group and the alternative quantum logic gate;
and executing the third quantum circuit to obtain a calculation result mat2.
Further, the determining a simplified quantum logic gate set in the second quantum circuit includes:
performing execution time sequence division on the quantum logic gates in the second quantum circuit to obtain quantum logic gates positioned in each execution time sequence;
and determining a simplified quantum logic gate group according to the quantum logic gates positioned in each execution time sequence.
Further, wherein the simplified set of quantum logic gates is at least two quantum logic gates in the second quantum circuit that are located within different execution timings.
The invention provides a judging system for the mobility of a quantum logic gate, which comprises the following components:
the acquisition module is used for acquiring a target quantum logic gate and a moving mode in the quantum circuit;
the first determining module is used for constructing a quantum circuit after moving according to the quantum circuit, the target quantum logic gate and the moving mode;
a second determining module, configured to determine a quantum logic gate associated with a qubit of the target quantum logic gate as a relevant quantum logic gate, where the associated quantum logic gate refers to a quantum logic gate in which the qubit intersects with the qubit of the target quantum logic gate;
A third determining module, configured to determine a first quantum circuit and a second quantum circuit respectively, where the first quantum circuit is configured with related quantum logic gates in the same order as the first quantum circuit, and the second quantum circuit is configured with related quantum logic gates in the same order as the moved quantum circuit;
the judging module is used for judging whether the first quantum circuit is equivalent to the second quantum circuit or not;
and the fourth determining module is used for determining that the target quantum logic gate is movable under the condition that the judging result of the judging module is yes.
The invention also provides a storage medium having a computer program stored therein, wherein the computer program is arranged to perform the method when run.
The invention also provides an electronic device comprising a memory having a computer program stored therein and a processor arranged to run the computer program to perform the method.
In addition, the invention also provides an optimizing method of the quantum circuit, which comprises the following steps:
Judging the mobility of a target quantum logic gate in the quantum circuit according to the judging method;
if the target quantum logic gate is movable, replacing the quantum circuit by using the moved quantum circuit;
determining a simplified quantum logic gate group in the moved quantum circuit, wherein the simplified quantum logic gate group is at least two quantum logic gates in the moved quantum circuit;
determining a quantum logic gate equivalent to the simplified quantum logic gate set as a substitute quantum logic gate;
and determining an optimized quantum circuit corresponding to the moved quantum circuit according to the simplified quantum logic gate group and the alternative quantum logic gate.
Compared with the prior art, the method and the device for obtaining the target quantum logic gate and the moving mode in the quantum circuit are used for obtaining the target quantum logic gate and the moving mode in the quantum circuit, constructing the moving quantum circuit on the basis, determining the related quantum logic gate, respectively determining the first quantum circuit and the second quantum circuit according to the sequence of the related quantum logic gate in the quantum circuit and the sequence of the moving quantum circuit, and determining the movability of the target quantum logic gate by judging whether the first quantum circuit is equivalent to the second quantum circuit or not.
Drawings
Fig. 1 is a schematic flow chart of a method for judging mobility of a quantum logic gate according to an embodiment of the present invention;
fig. 2 (a) is a schematic diagram of a second quantum circuit after performing timing division in example 2 according to an embodiment of the present invention;
FIG. 2 (b) is a schematic diagram of a second quantum circuit in example 2 according to an embodiment of the present invention after performing timing division and simplifying the quantum logic gate group;
fig. 3 is a schematic structural diagram of a quantum logic gate mobility judgment system according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a first determining module in a quantum logic gate mobility judging system according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a second determining module in the quantum logic gate mobility judging system according to the embodiment of the present invention;
fig. 6 is a schematic structural diagram of a judging module in a judging system for the mobility of a quantum logic gate according to an embodiment of the present invention.
Detailed Description
The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention.
It should be noted that the terms "first," "second," and the like in the description and in the claims are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
The embodiment of the invention provides a judging method for the mobility of a quantum logic gate, which is applied to electronic equipment such as a mobile terminal, such as a mobile phone and a tablet personal computer, and is preferably applied to a computer such as a common computer, a quantum computer and the like. This will be described in detail below.
It should be noted that a real quantum computer is a hybrid structure, which includes two major parts: part of the computers are classical computers and are responsible for performing classical computation and control; the other part is a quantum device, responsible for performing quantum computation. In practice, a real quantum program is a series of instruction sequences written in a quantum language, such as the qrun language, that can run on a quantum computer, implementing support for quantum logic gate operations, and ultimately enabling simulation of quantum computation. Specifically, the quantum program is a series of instruction sequences for operating the quantum logic gate according to a certain time sequence.
In practical applications, in order to simulate quantum computing to verify quantum applications and the like, it may be implemented by a quantum virtual machine running on a general computer. The quantum program related to the embodiment of the invention is a program for representing quantum bits and evolution thereof written by classical language and running on a quantum operation platform, wherein the quantum bits, quantum logic gates and the like related to quantum computation are respectively represented by corresponding codes.
The whole target quantum program corresponds to a total quantum circuit, the quantum circuit is a set formed by quantum logic gates, the process of executing the quantum circuit (the process of weighing the quantum calculation) is to use the quantum logic gates to make the quantum state evolve, and as each quantum logic gate corresponds to a unitary matrix, the process of making the quantum state evolve by the quantum logic gates can also be represented by multiplying the unitary matrix corresponding to the quantum logic gate by the right vector of the quantum state. For example, there is a quantum state |ψ0>, which is obtained after passing through a quantum logic gate (corresponding unitary matrix is denoted by U):
|ψ>＝U|ψ0>
it will be appreciated that quantum logic gates are the basis for quantum algorithms, in which each quantum logic gate is connected by a timeline, i.e. the state of the qubit evolves over time. Quantum logic gates include single quantum logic gates, double quantum logic gates, and multiple quantum logic gates, wherein:
the single quantum logic gate (e.g., adam Ma Men, brix-X gate, brix-Y gate, brix-Z gate, etc.) is a 2X 2 matrix, with one single quantum logic gate acting on one qubit in the quantum circuit; a two-quantum logic gate (e.g., control not gate, switch gate, etc.) is a 4 x 4 matrix, with one two-quantum logic gate acting on two qubits in a quantum circuit.
It should be noted that, the bits of the quantum bits acted by the double quantum logic gate include two bits, namely a control bit and an operation bit, the common double quantum logic gate is a CNOT gate (i.e. a control NOT gate), q1 in CNOT (q [1], q [2 ]) is the control bit, and q2 is the operation bit, and the actions are as follows: when the control bit is in the state of |0>, the quantum state of the operation bit q2 is unchanged, and when the control bit is in the state of |1>, the quantum state of the operation bit q2 is inverted. It should be noted that the control bit and the operation bit are not allowed to be the same qubit when the quantum wire is constructed.
In addition, for a controlled quantum logic gate, it means that when the quantum state of the controlled quantum bit is |1>, the controlled quantum logic gate is effective, i.e., can act on the corresponding quantum bit, evolve the quantum state, and when the quantum state of the controlled quantum bit is |0>, the controlled quantum logic gate is ineffective, e.g., for the quantum logic gate CNOT (q [0], q [1 ]) controlled (q [2 ]), in a quantum circuit, CNOT (q [0], q [1 ]) is effective, and can act on q0, q1, when the quantum state of the equivalent quantum bit q2 is |1 >.
In addition, the transposed conjugate matrix of the unitary matrix is also a unitary matrix, and the matrix corresponding to the quantum logic gate after the transposed conjugate processing is the transposed conjugate matrix of the unitary matrix corresponding to the quantum logic gate. For example, a quantum logic gate, whose corresponding unitary matrix is expressed using U, Representing the transpose conjugate matrix of the unitary matrix, the matrix corresponding to the transpose conjugate processed by the quantum logic gate is +.>And satisfy the arithmetic relation->(identity matrix). In the quantum wire, H (q 1]) Dagger () represents H (q 1]) Is a transposed conjugate of (a).
In addition, it should be noted that, in the classical program, there are a sequential structure (which is executed sentence by sentence from top to bottom in the order in which the sentences are written), a selection structure (for example, if selection structure—when the conditional sentence is true, the action is executed; when the conditional sentence is false, skip is not executed), and a loop structure (for example, while structure loop), and there are similar structures in the quantum program, which directly reflect whether the quantum wire is a sequential structure, a selection structure, or a loop structure; furthermore, there may be nested lines in the quantum program, i.e. a total number of sub-lines are nested with several sub-lines, for example:
QProg prog；
QProg prog3；
QCircuit circuit1；
circuit1<<X(q[2])<<S(q[0])<<H(q[1])
prog<<CNOT(q[0],q[1])<<RZ(q[2],PI/2)<<H(q[1])<<S(q[1])<<circuit1<<Z(q[0])
then for the total quantum circuit prog, circuit1 is a sub quantum circuit nested in prog, and the sequential expansion of the quantum logic gates in the total quantum circuit prog is:
CNOT(q[0],q[1])、RZ(q[2],PI/2)、H(q[1])、S(q[1])、X(q[2])、S(q[0])、H(q[1])、Z(q[0])。
it should be noted that, similar to the transpose conjugation of the quantum logic gate, the transpose conjugation of a sub-quantum circuit may also be performed in the quantum circuit, for example, in a transpose conjugation mode, if the above-mentioned quantum program code further includes a circulant 1.Setdagger (true), it indicates that the sub-quantum circuit is subjected to the transpose conjugation, and the quantum logic gate in the prog is sequentially unfolded to be:
CNOT(q[0],q[1])、RZ(q[2],PI/2)、H(q[1])、S(q[1])、H(q[1]).dagger()、S(q[0]).dagger()、X(q[2]).dagger()、Z(q[0])。
The judgment of the mobility of the quantum logic gate according to the invention refers to the judgment of whether the designated quantum logic gate can move according to a designated moving mode (including but not limited to target position information to be moved) in a section of quantum circuit.
Referring to the flow chart shown in fig. 1, the method for judging the mobility of the quantum logic gate provided in this embodiment includes:
s100, acquiring a target quantum logic gate and a moving mode in the quantum circuit.
The method includes that a target quantum logic gate and a moving mode in a quantum circuit are required to be acquired, wherein the target quantum logic gate is a quantum logic gate which needs to be judged whether to move according to the moving mode, the moving mode refers to a mode of adding the target quantum logic gate or a copy of the target quantum logic gate to a designated target position, the specific designated target position can be a position where another quantum logic gate is located, or a position between two other adjacent quantum logic gates, namely, the moving mode specifically refers to a mode of removing the target quantum logic gate to a position where the other quantum logic gate is located so as to replace the other quantum logic gate, or a copy of the target quantum logic gate which is copied and generated is inserted between the other two adjacent quantum logic gates, and the like, and the method is not limited.
In step S100, the target quantum logic gate may include a first target quantum logic gate and a second target quantum logic gate; the moving mode comprises one of the following steps: the first and second target quantum logic gates exchange positions, the first target quantum logic gate moves to insert into a position adjacent to the second target quantum logic gate, and the first target quantum logic gate moves to replace the second target quantum logic gate.
That is, the quantum wires after the movement are three kinds of:
a quantum circuit formed at the exchange position of the first target quantum logic gate and the second target quantum logic gate in the quantum circuit;
the first target quantum logic gate in the quantum circuit is inserted into the quantum circuit formed at the position adjacent to the second target quantum logic gate in a moving way, namely the first target quantum logic gate is inserted into the position between the second target quantum logic gate and one quantum logic gate adjacent to the second target quantum logic gate in a moving way;
the first target quantum logic gate in the quantum circuit moves to a quantum circuit formed in place of the second target quantum logic gate.
For ease of understanding, the moving manner of the switching positions of the first target quantum logic gate and the second target quantum logic gate is described in conjunction with example 1, and the other two moving manners are not described again.
For example, in example 1, the determination is made as to the mobility of a given number of sub-logic gates in the following 1# quantum line:
TEST(JudgeTwoNodeIterIsSwappable,doubleGateTest2)
QProg prog；
prog<<CNOT(q[0],q[3])<<RZ(q[1],PI/2)<<RZ(q[2],PI/2)<<CNOT(q[4],q[2])<<H(q[1])<<S(q[1])<<circuit3<<Z(q[0])<<H(q[1]).dagger()<<RZ(q[1],PI/2).dagger()<<gate2
NodeIter itr1＝prog.getFirstNodeIter()；
NodeIter itr2＝prog.getLastNodeIter()；
wherein:
QVec control_vec；
control_vec.push_back(q[1])；
auto gate2＝CNOT(q[0],q[3]).dagger()；
gate2.setControl(control_vec)；
QCircuit circuit3；
circuit3<<X(q[2])<<S(q[1])<<H(q[2])<<S(q[2])<<Z(q[0])；
circuit3.setDagger(true)；
it should be noted that, those skilled in the art should know the meaning and operation rules of different code representations in the quantum circuit, for example:
h represents an Hadamard gate, X represents a brix-X gate (the corresponding matrix of which is a brix matrix σx), Y represents a brix-Y gate (the corresponding matrix of which is a brix matrix σy), Z represents a brix-Z gate (the corresponding matrix of which is a brix matrix σz), RX represents an arbitrary rotating brix-gate, RY represents an arbitrary rotating brix-Y gate, RZ represents an arbitrary rotating brix-Z gate, and CNOT represents a Control NOT gate (Control-NOT); gate2 is CNOT (q [0], q [3 ]) dagger (). Controlled (q [1 ]).
q 0, q 1, q 2, q 3 are qubits with bits from 0 to 3;
CNOT (q 2, q 3) indicates that there is a control NOT gate operation on both q 2 and q 3, and q 2 is the control bit and q 3 is the operation bit; h (q 0) represents a Hadamard gate operation on q 0; RY (q 2, PI/2) indicates that there is an arbitrary rotation of the Brix-Y gate at q 2, the rotation angle being PI/2.
In this example, the movable target quantum logic gate needs to be determined to be a first target quantum logic gate CNOT (q [0], q [3 ]) and a second target quantum logic gate2, which are marked by noditer1=prog.getfirstnoditer (), noditer2=prog.getlastnoditer (), respectively.
S200, constructing a quantum circuit after moving according to the quantum circuit, the target quantum logic gate and the moving mode.
For the 1# quantum circuit, the moved quantum circuit is a new quantum circuit formed after the first target quantum logic gate CNOT (q [0], q [3 ]) and the second target quantum logic gate2 exchange positions, namely the moved quantum circuit is:
prog<<gate2<<RZ(q[1],PI/2)<<RZ(q[2],PI/2)<<CNOT(q[4],q[2])<<H(q[1])<<S(q[1])<<circuit3<<Z(q[0])<<H(q[1]).dagger()<<RZ(q[1],PI/2).dagger()<<CNOT(q[0],q[3])
in specific implementation, step S200 may include:
s210, generating the quantum circuit copy and the target quantum logic gate copy;
s220, determining a target position for placing the target quantum logic gate copy in the quantum circuit copy according to the moving mode;
s230, adding the target quantum logic gate copy to the quantum circuit copy at the target position;
s240, deleting the target quantum logic gate in the quantum circuit copy;
S250, determining the new quantum wire copy as the moved quantum wire.
Combining the 1# quantum circuit of example 1, determining a first target position and a second target position in the quantum circuit copy for respectively placing the first target quantum logic gate copy and the second target quantum logic gate copy according to a moving mode (namely, the first target quantum logic gate and the second target quantum logic gate exchange position), wherein the moving mode in example 1 is that the first target quantum logic gate and the second target quantum logic gate exchange, the first target position is the position of the second quantum logic gate in the quantum circuit copy, the second target position is the position of the first quantum logic gate in the quantum circuit copy, and on the basis, the first target quantum logic gate copy and the second quantum logic gate copy are added into the quantum circuit copy, and then deleting the first target quantum logic gate and the second quantum logic gate in the quantum circuit copy (note that the first target quantum logic gate and the second quantum logic gate copy are different from each other), so as to obtain an updated quantum circuit copy, namely, the updated quantum circuit is the quantum circuit after the updating.
S300, determining a quantum logic gate associated with a quantum bit of a target quantum logic gate as a relevant quantum logic gate, wherein the associated quantum logic gate refers to a quantum logic gate in which the quantum bit and the quantum bit of the target quantum logic gate have an intersection.
For the 1# quantum wire, there is an intersection of quantum logic gates acting with the first target quantum logic gate CNOT (q [0], q [3 ]) and the second target quantum logic gate 2:
CNOT(q[0],q[3])；RZ(q[1],PI/2)；H(q[1])；S(q[1])；Z(q[0]).dagger()；S(q[1]).dagger()；Z(q[0])；H(q[1]).dagger()；RZ(q[1],PI/2).dagger()；CNOT(q[0],q[3]).dagger().controled(q[1])
it should be noted that, the qubit of the target quantum logic gate may be determined, and we refer to the target qubit as a control bit qubit, an operation bit qubit, a controlled qubit of the target quantum logic gate, etc., so that the qubit of at least one quantum logic gate (i.e., the target quantum logic gate) in one quantum circuit is intersected with the determined target qubit.
Wherein, in the implementation, the determining that the quantum logic gate associated with the qubit of the target quantum logic gate is a relevant quantum logic gate may include:
s310, respectively determining a first position in the quantum circuit and a second position in the moved quantum circuit according to the target quantum logic gate, wherein the first position refers to the position of the target quantum logic gate in the quantum circuit, and the second position refers to the position of the target quantum logic gate in the moved quantum circuit;
S320, determining a third position corresponding to the second position in the quantum circuit;
s330, acquiring all quantum logic gates corresponding to the first position to the third position in the quantum circuit;
s340, determining quantum logic gates with intersections of the quantum bits in all the quantum logic gates and the quantum bits in the target quantum logic gate as relevant quantum logic gates.
Through steps S310 to S340, a first position in the quantum line (i.e., a position marked by nodetiter itr1=prog.getfirstnodetiter () in the 1# quantum line of example 1) and a second position in the moved quantum line (i.e., a position marked by nodetiter itr2=prog.getlastnodetiter () in the 1# quantum line of example 1) are determined, a third position in the quantum line (the quantum line in example 1, the second position is the same as the third position) is determined through the second position, all quantum logic gates corresponding to each position from the first position to the third position in the quantum line are directly obtained, and then a quantum logic gate in which an intersection exists with a quantum bit of a target quantum logic gate is determined as a relevant quantum logic gate, so that efficiency can be greatly improved relative to determining the quantum logic gate in the whole quantum line from head to tail.
S400, respectively determining a first quantum circuit and a second quantum circuit constructed by the related quantum logic gates, wherein the sequence of the related quantum logic gates in the first quantum circuit is the same as that in the quantum circuit, and the sequence of the related quantum logic gates in the second quantum circuit is the same as that in the quantum circuit after movement.
Specifically, a first quantum circuit is determined according to the sequence of the relevant quantum logic gates in the quantum circuit, and a second quantum circuit is determined according to the sequence of the relevant quantum logic gates in the moved quantum circuit.
For example 1, the first quantum wire determined by the order of the relevant quantum logic gates in the quantum wire at this step is:
CNOT(q[0],q[3])<<RZ(q[1],PI/2)<<H(q[1])<<S(q[1])<<Z(q[0]).dagger()<<S(q[1]).dagger()<<Z(q[0])<<H(q[1]).dagger()<<RZ(q[1],PI/2).dagger()<<CNOT(q[0],q[3]).dagger().controled(q[1])
the second quantum circuit determined according to the sequence of the relevant quantum logic gate in the moved quantum circuit is as follows:
CNOT(q[0],q[3]).dagger().controled(q[1])<<RZ(q[1],PI/2)<<H(q[1])<<S(q[1])<<Z(q[0]).dagger()<<S(q[1]).dagger()<<Z(q[0])<<H(q[1]).dagger()<<RZ(q[1],PI/2).dagger()<<CNOT(q[0],q[3])
s500, judging whether the first quantum circuit is equivalent to the second quantum circuit.
Each quantum logic gate corresponds to a unitary matrix, so that the quantum circuit corresponds to a series of unitary transformations, and the process of quantum computation can be understood as the process of sequentially performing left-hand multiplication operations on the initial quantum states, and the operation formula is as |ψ > Last state ＝U n U n-1 ....U 2 U 1 |ψ> Initial initiation . It will be appreciated that since each of the quantum logic gates making up the quantum wire is a unitary matrix, the entire quantum wire as a whole is also a large unitary matrix.
Therefore, it is not difficult to derive that the target quantum logic gate is movable as a mutual sufficient requirement that the quantum wires and the quantum wires after the movement are equivalent. After the target quantum logic gate moves, only the relative time sequence between quantum logic gates intersected with the quantum bit of the target quantum logic gate is changed, so that only whether the first quantum circuit and the second quantum circuit are equivalent or not is determined by the relative sequence of the related quantum logic gates in the quantum circuits before and after the movement.
Specifically, this step determines whether the calculation result of executing the first quantum circuit is equivalent to the calculation result of executing the second quantum circuit, and what needs to be described here is: determining whether the result of the computation performed on the first quantum wire is equivalent to the result of the computation performed on the second quantum wire may be performed by determining whether e exists between the result of the computation performed on the first quantum wire and the result of the computation performed on the second quantum wire iα A relationship of times, where e iα ＝cosα+isinα，i 2 -1, alpha is any angle value in the range of 0 to 2 pi.
The demonstration derivation for this step is specifically as follows:
assuming an initial quantum state of M 0 The large unitary matrix corresponding to the first quantum circuit is U 1 The large unitary matrix corresponding to the second quantum circuit is U 2 Wherein U is 1 ＝e iα U 2 ，e iα ＝cosα+isinα；
Then mat1=u 1 M 0 ，mat2＝U 2 M 0 ；
And due to U 1 ＝e iα U 2 So mat1=u 1 M 0 ＝e iα U 2 M 0 ＝e iα mat2。
The logical state in which 3 qubits are located is 2 3 (i.e., an superposition of 8) quantum states, wherein the 8 quantum states |ψ i >Respectively |000>、|001>、|010>、|011>、|100>、|101>、|110>Sum |111>At this time, any logic state |ψ where the 3 qubits are located>Can be expressed as:
|ψ>＝c 0 |000>+c 1 |001>+c 2 |010>+c 3 |011>+c 4 |100>+c 5 |101>+c 6 |110>+c 7 |111>
and the matrix corresponding to |ψ > is expressed as:
wherein each quantum state |ψ of 8 quantum states i >The corresponding amplitude of (or weighing sub-state component) is c i I.e. c 0 To c 7 One of these plural numbers, c 0 To c 7 The subscript of (2) is the quantum state |ψ to which the amplitude belongs i >Decimal value corresponding to binary of (c), we will c 0 To c 7 Each of these complex numbers is referred to as a single amplitude. c 0 To c 7 These complex representations are of the form c i ＝a+bi。
Based on this, after calculation is performed on the first quantum wire, any one of the quantum states |ψ i >The probability of it is |c i | 2 And (2) and
the amplitude of the corresponding quantum state after the execution of the second quantum circuit is e iα c i The die is
Therefore, after quantum computation is performed on the first quantum wire and the second quantum wire, the amplitudes of any one of the corresponding quantum states are equal, that is, the first quantum wire and the second quantum wire are equivalent.
The demonstration concludes.
In step S500, the first quantum circuit may be specifically executed to obtain a calculation result mat1; executing the second quantum circuit to obtain a calculation result mat2; determining whether mat1 and mat2 match mat1=λmat2, where λ=e iα The method comprises the steps of carrying out a first treatment on the surface of the The first quantum wire is equivalent to the second quantum wire if mat1=λmat2 is satisfied, and the first quantum wire is not equivalent to the second quantum wire if mat1=λmat2 is not satisfied.
It should be noted here that, as will be understood by those skilled in the art, the matrix form corresponding to each quantum logic gate in the quantum computing field is as follows:
matrix form corresponding to each quantum logic gate
For example 1, the calculation result mat1 of the first quantum wire is:
the calculation result mat2 of the second quantum circuit is:
and α takes 0, mat1=e iα mat2, so that the first quantum wire is equivalent to the second quantum wire.
Here, it should be noted that when the quantum circuit performs the calculation, one skilled in the art should understand the following operation rules:
(1) If two adjacent quantum logic gates act on the same quantum bit, matrix multiplication is directly performed, for example:
h (q [1 ]) < S (q [1 ]) is performed, and the result is:
(2) If two adjacent quantum logic gates act on different quantum bits, the tensor product operation is directly performed, for example:
CNOT (q [0], q [3 ]) < RZ (q [1], PI/2) is performed, and the result is that:
in a specific implementation, to reduce the computational complexity, the obtaining, according to the second quantum circuit, the calculation result mat2 includes the following steps:
s500-1, determining a simplified quantum logic gate group in the second quantum circuit, wherein the simplified quantum logic gate group is at least two quantum logic gates in the second quantum circuit. As a specific implementation manner of the step, execution time sequence division may be performed on the quantum logic gates in the second quantum circuit to obtain quantum logic gates located in each execution time sequence; and then determining a simplified quantum logic gate group according to the quantum logic gates positioned in each execution time sequence, wherein the simplified quantum logic gate group can be at least two quantum logic gates positioned in different execution time sequences in the second quantum circuit. The purpose of this embodiment in this step is to replace and optimize at least two quantum logic gates located in different execution timings, shortening the number of execution timings, i.e. reducing the number of times to be executed, providing quantum computing efficiency.
S500-2, determining a quantum logic gate equivalent to the simplified quantum logic gate group as a substitute quantum logic gate.
S500-3, determining a third quantum circuit corresponding to the second quantum circuit according to the simplified quantum logic gate group and the alternative quantum logic gate;
s500-4, executing the third quantum circuit to obtain a calculation result mat2.
In particular, there may be multiple quantum logic gate groups with specific structures in the quantum circuit, and these quantum logic gate groups may be optimized alternatively, for example, the SWAP gate may replace the quantum logic gate group formed by the following multiple single gates and CNOT gates, where the specific substitution relationship is:
SWAP(q[i],q[j])
＝CNOT(q[i]，q[j])+H(q[i])+H(q[j])+CNOT(q[i]，q[j])+H(q[i])+H(q[j])+CNOT(q[i]，q[j])；
the SWAP gate can be used for replacing a quantum logic gate group formed by a plurality of CNOT gates, and the specific replacement relationship is as follows: SWAP (q [ i ], q [ j ])=cnot (q [ i ], q [ j ])+cnot (q [ j ], q [ i ])+cnot (q [ i ], q [ j ]).
By the substitution optimization of the equivalent quantum logic gates, the number of the quantum logic gates can be reduced, so that the program running efficiency is improved, and the quantum computing effect is optimized, for example: a quantum logic gate such as SWAP is used to replace the quantum circuit consisting of multiple CNOT gates.
Meanwhile, through the mutual replacement of the quantum logic gates or the sub-quantum circuits, the technical barriers among different platforms can be overcome to a certain extent, for example, company A defines the SWAP gate, company B does not define the SWAP gate, and the functions of the SWAP gate are equivalent only by a plurality of single gates and CNOT gates in a quantum program.
Assume that in yet another example (example 2), the determined second quantum wire is:
CNOT(q[0],q[1])<<H(q[1])<<H(q[2])<<H(q[0])<<CNOT(q[1],q[2])<<RZ(q[0],PI/2)<<H(q[1])<<H(q[2])<<CNOT(q[2],q[0])
after the execution timing is divided, quantum logic gates located in different execution timings are obtained, as shown in fig. 2 (a), specifically as follows:
first time sequence: CNOT (q [0], q [1 ]), H (q [2 ]);
second timing: h (q 1), H (q 0);
third timing: CNOT (q 1, q 2), RZ (q 0, PI/2);
fourth timing: h (q 1), H (q 2);
fifth timing: CNOT (q 2, q 0).
Wherein, the quantum logic gate group consisting of H (q 2) at the first time, H (q 1) at the second time, CNOT (q 1, q 2) at the third time, and H (q 1) and H (q 2) at the fourth time can be simplified, and the substitute quantum logic gate is CNOT (q 2, q 1), and the simplified quantum circuit diagram is shown with reference to FIG. 2 (b), namely, the third quantum circuit is:
CNOT(q[0],q[1])<<H(q[0])<<CNOT(q[2],q[1])<<RZ(q[0],PI/2)<<CNOT(q[2],q[0])
and executing a third quantum circuit to obtain a calculation result mat2.
The performing time sequence division on the quantum circuit performs time sequence division on a quantum logic gate in the second quantum circuit, including:
obtaining information of the second quantum circuit;
dividing the execution time sequence of a single quantum logic gate in a first bit quantum logic gate executed by each quantum bit into the same time sequence according to the current information of the second quantum circuit;
Dividing the execution time sequence of the two quantum logic gates into the same time sequence when two digits corresponding to the two quantum logic gates in the first bit quantum logic gate are the first bit; otherwise, dividing the execution time sequence of the two quantum logic gates into the next time sequence of the same time sequence;
dividing the execution time sequence of the multiple quantum logic gate into the same time sequence when a plurality of bits corresponding to the multiple quantum logic gate in the first bit quantum logic gate are all the first bits;
deleting the quantum logic gate information which is contained in the information of the coded quantum circuit and is subjected to the same time sequence division, continuing to execute the information according to the current second quantum circuit, and dividing the execution time sequence of the single quantum logic gate in the first bit quantum logic gate which is executed by each quantum bit into the same time sequence.
The plurality of bits corresponding to the multiple quantum logic gate means that one bit is corresponding to each quantum bit of the multiple quantum logic gate operation, and indicates the number of quantum logic gates to which the multiple quantum logic gate belongs.
It should be noted that, deleting the quantum logic gate information after the time sequence division is completed refers to deleting the quantum logic gate information in the coded quantum circuit information, so that for the convenience of time sequence division, the quantum logic gate in the coded quantum circuit is not deleted, and the coded quantum circuit structure after combination is unchanged.
In another preferred embodiment, if the relevant quantum logic gate is determined according to S310 to S340, then a specific embodiment of determining whether the first quantum wire is equivalent to the second quantum wire may include:
judging whether the related quantum logic gate only comprises one quantum logic gate or not, wherein the quantum logic gate is the target quantum logic gate;
if yes, the first quantum circuit is equivalent to the second quantum circuit.
Firstly, judging whether the determined related quantum logic gate only comprises one quantum logic gate, wherein the logic gate is the target quantum logic gate, if so, directly determining that the first quantum circuit is equivalent to the second quantum circuit, and the mode saves tedious calculation and is more efficient.
And S600, if the quantum logic gate is equivalent, determining that the target quantum logic gate is movable.
According to the judging result, determining that the target quantum logic gate is movable, specifically, if the judging result is yes, namely the first quantum circuit is equivalent to the second quantum circuit, the target quantum logic gate is movable; if the judgment result is NO, namely the first quantum circuit is not equivalent to the second quantum circuit, the target quantum logic gate is not movable.
Compared with the prior art, the method and the device for achieving the quantum logic gate movement of the quantum circuit acquire a target quantum logic gate and a movement mode in the quantum circuit, construct the moved quantum circuit on the basis, determine relevant quantum logic gates, respectively determine a first quantum circuit and a second quantum circuit according to the sequence of the relevant quantum logic gates in the quantum circuit and the sequence of the relevant quantum logic gates in the moved quantum circuit, and determine the mobility of the target quantum logic gate by judging whether the first quantum circuit is equivalent to the second quantum circuit or not.
As shown in fig. 3, the present embodiment further provides a system for determining mobility of a quantum logic gate, which includes an acquisition module 701, a first determination module 702, a second determination module 703, a third determination module 704, a determination module 705, and a fourth determination module 706, where:
the obtaining module 701 is configured to obtain a target quantum logic gate and a movement mode in the quantum circuit.
The target quantum logic gate comprises a first target quantum logic gate and a second target quantum logic gate;
the moving mode comprises one of the following steps: the first and second target quantum logic gates exchange positions, the first target quantum logic gate moves to insert into a position adjacent to the second target quantum logic gate, and the first target quantum logic gate moves to replace the second target quantum logic gate.
The first determining module 702 is configured to construct a quantum circuit after moving according to the quantum circuit, the target quantum logic gate, and the moving mode.
Specifically, referring to the schematic structural diagram of the first determining module 702 shown in fig. 4, the first determining module 702 may include:
a quantum wire replica generation unit 7021 for generating the quantum wire replica and the target quantum logic gate replica;
a target position determining unit 7022, configured to determine, according to the movement manner, a target position in the quantum wire replica for placing the target quantum logic gate replica;
an adding unit 7023 for adding the target quantum logic gate replica to the target location of the quantum wire replica;
a deleting unit 7024, configured to delete the target quantum logic gate in the quantum wire replica;
a first determining unit 7025 is configured to determine a new quantum wire replica as a moved quantum wire.
A second determining module 703 is configured to determine a quantum logic gate associated with the qubit of the target quantum logic gate as an associated quantum logic gate, where the associated quantum logic gate refers to a quantum logic gate where the qubit intersects with the qubit of the target quantum logic gate.
Specifically, referring to the schematic structural diagram of the second determining module 703 shown in fig. 5, the second determining module 703 may include:
a quantum logic gate position determining unit 7031 configured to determine, according to the target quantum logic gate, a first position in the quantum circuit and a second position in the moved quantum circuit, where the first position refers to a position of the target quantum logic gate in the quantum circuit, and the second position refers to a position of the target quantum logic gate in the moved quantum circuit;
a third position determining unit 7032 configured to determine a third position corresponding to the second position in the quantum wire;
a quantum logic gate obtaining unit 7033, configured to obtain all quantum logic gates corresponding to the first position to the third position in the quantum circuit;
and a relevant quantum logic gate determining unit 7034, configured to determine that a quantum logic gate in which the quantum bit in the all quantum logic gates intersects with the quantum bit in the target quantum logic gate is a relevant quantum logic gate.
A third determining module 704, configured to determine a first quantum circuit and a second quantum circuit respectively, where the order of the relevant quantum logic gates in the first quantum circuit is the same as the order of the relevant quantum logic gates in the quantum circuit, and the order of the relevant quantum logic gates in the second quantum circuit is the same as the order of the relevant quantum logic gates in the moved quantum circuit.
The judging module 705 is configured to judge whether the first quantum wire is equivalent to the second quantum wire.
Specifically, referring to the schematic structural diagram of the judging module 705 shown in fig. 6, the judging module 705 may include:
a first calculating unit 7051, configured to execute the first quantum wire to obtain a calculation result mat1;
a second calculating unit 7052, configured to execute the second quantum circuit to obtain a calculation result mat2;
a determining unit 7053 for determining whether mat1 and mat2 match mat1=e iα mat2, where e iα ＝cosα+isinα，i 2 -1, alpha is any angle value in 0-2 pi;
a second determining unit 7054 configured to determine that the first quantum wire is equivalent to the second quantum wire if the determination result of the determining unit 7053 is in accordance; and determining that the first quantum wire is not equivalent to the second quantum wire if the determination result of the determination unit 7053 is not coincident.
The second calculating unit 7052 is specifically configured to perform timing division on the quantum logic gates in the second quantum circuit, so as to obtain quantum logic gates located in each execution timing; determining a simplified quantum logic gate group according to the quantum logic gates in each execution time sequence, wherein the simplified quantum logic gate group is at least two quantum logic gates in the second quantum circuit in different execution time sequences; determining a quantum logic gate equivalent to the simplified quantum logic gate set as a substitute quantum logic gate; determining a third quantum circuit corresponding to the second quantum circuit according to the simplified quantum logic gate group and the alternative quantum logic gate; and executing the third quantum circuit to obtain a calculation result mat2.
And a fourth determining module 706, configured to determine the mobility of the target quantum logic gate according to the determination result.
Compared with the prior art, the system for judging the mobility of the quantum logic gate can acquire the target quantum logic gate and the moving mode in the quantum circuit, constructs the moving quantum circuit on the basis, determines the related quantum logic gate, respectively determines the first quantum circuit and the second quantum circuit according to the sequence of the related quantum logic gate in the quantum circuit and the sequence of the related quantum logic gate in the moving quantum circuit, and determines the mobility of the target quantum logic gate by judging whether the first quantum circuit and the second quantum circuit are equivalent.
The embodiment of the invention also provides a storage medium in which a computer program is stored, wherein the computer program is arranged to perform the steps of any of the method embodiments described above when run.
Specifically, in the present embodiment, the above-described storage medium may be configured to store a computer program for executing the steps of:
s100, acquiring a target quantum logic gate and a moving mode in a quantum circuit;
s200, constructing a moved quantum circuit according to the quantum circuit, the target quantum logic gate and the moving mode;
S300, determining a quantum logic gate associated with a quantum bit of a target quantum logic gate as a relevant quantum logic gate, wherein the associated quantum logic gate refers to a quantum logic gate in which the quantum bit and the quantum bit of the target quantum logic gate have an intersection;
s400, respectively determining a first quantum circuit and a second quantum circuit constructed by the related quantum logic gates, wherein the sequence of the related quantum logic gates in the first quantum circuit is the same as that in the quantum circuit, and the sequence of the related quantum logic gates in the second quantum circuit is the same as that in the quantum circuit after movement;
s500, judging whether the first quantum circuit is equivalent to the second quantum circuit or not;
and S600, if the quantum logic gate is equivalent, determining that the target quantum logic gate is movable.
Specifically, in the present embodiment, the storage medium may include, but is not limited to: a usb disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing a computer program.
The present invention also provides an electronic device comprising a memory having a computer program stored therein and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.
Specifically, the electronic apparatus may further include a transmission device and an input/output device, where the transmission device is connected to the processor, and the input/output device is connected to the processor.
Specifically, in the present embodiment, the above-described processor may be configured to execute the following steps by a computer program:
s100, acquiring a target quantum logic gate and a moving mode in a quantum circuit;
s200, constructing a moved quantum circuit according to the quantum circuit, the target quantum logic gate and the moving mode;
s300, determining a quantum logic gate associated with a quantum bit of a target quantum logic gate as a relevant quantum logic gate, wherein the associated quantum logic gate refers to a quantum logic gate in which the quantum bit and the quantum bit of the target quantum logic gate have an intersection;
s400, respectively determining a first quantum circuit and a second quantum circuit constructed by the related quantum logic gates, wherein the sequence of the related quantum logic gates in the first quantum circuit is the same as that in the quantum circuit, and the sequence of the related quantum logic gates in the second quantum circuit is the same as that in the quantum circuit after movement;
S500, judging whether the first quantum circuit is equivalent to the second quantum circuit or not;
and S600, if the quantum logic gate is equivalent, determining that the target quantum logic gate is movable.
Compared with the prior art, the method and the device for achieving the quantum logic gate movement of the quantum circuit acquire a target quantum logic gate and a movement mode in the quantum circuit, construct the moved quantum circuit on the basis, determine relevant quantum logic gates, respectively determine a first quantum circuit and a second quantum circuit according to the sequence of the relevant quantum logic gates in the quantum circuit and the sequence of the relevant quantum logic gates in the moved quantum circuit, and determine the mobility of the target quantum logic gate by judging whether the first quantum circuit is equivalent to the second quantum circuit or not.
It should be noted that, the quantum logic gate mobility judgment method provided in this embodiment is beneficial to optimizing a quantum circuit, so as to optimize a quantum circuit with high computational complexity into a quantum circuit with low computational complexity, and specifically, the embodiment also provides an optimizing method of a quantum circuit, which includes:
judging the mobility of a target quantum logic gate in the quantum circuit according to the judging method;
if the target quantum logic gate is movable, using the moved quantum circuit to replace the quantum circuit;
Determining a simplified quantum logic gate group in the moved quantum circuit, wherein the simplified quantum logic gate group is at least two quantum logic gates in the moved quantum circuit;
determining a quantum logic gate equivalent to the simplified quantum logic gate set as a substitute quantum logic gate;
and determining an optimized quantum circuit corresponding to the moved quantum circuit according to the simplified quantum logic gate group and the alternative quantum logic gate.
According to the optimizing method, whether the quantum logic gate in the quantum circuit can move is judged, so that the target quantum logic gate can be moved to form a quantum logic gate group which can be simplified and replaced with other quantum logic gates under the condition that the execution effect of the quantum circuit is not changed, and the quantum logic gate group is replaced by the replacing quantum logic gate to optimize the quantum circuit, so that the quantum circuit with high calculation complexity is optimized into the quantum circuit with low calculation complexity.
In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the modules or units is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection via interfaces, devices or units, which may be in electrical, mechanical or other forms.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiment.
Claims (13)
1. A judging method for the mobility of a quantum logic gate comprises the following steps:
acquiring a target quantum logic gate and a moving mode in a quantum circuit;
constructing a quantum circuit after moving according to the quantum circuit, the target quantum logic gate and the moving mode;
determining a quantum logic gate associated with a qubit of a target quantum logic gate as a relevant quantum logic gate, wherein the associated quantum logic gate refers to a quantum logic gate in which the quantum bit has an intersection with a qubit of the target quantum logic gate;
determining a first quantum circuit and a second quantum circuit constructed by the related quantum logic gates respectively, wherein the sequence of the related quantum logic gates in the first quantum circuit is the same as that in the quantum circuit, and the sequence of the related quantum logic gates in the second quantum circuit is the same as that in the quantum circuit after movement;
Executing the first quantum circuit to obtain a calculation result mat1; executing the second quantum circuit to obtain a calculation result mat2; based on whether mat1 and mat2 match mat1=e or not iα mat2, or, if the related quantum logic gate only comprises one quantum logic gate, and the logic gate is the target quantum logic gate, determining whether the first quantum circuit and the second quantum circuit are equivalent, wherein e iα =cosα+isinα，i 2 -1, alpha is any angle value in 0-2 pi;
if so, determining that the target quantum logic gate is movable.
2. The quantum logic gate mobility judgment method according to claim 1, wherein:
the target quantum logic gate comprises a first target quantum logic gate and a second target quantum logic gate;
the moving mode comprises one of the following steps:
the first and second target quantum logic gates exchange positions, the first target quantum logic gate moves to insert into a position adjacent to the second target quantum logic gate, and the first target quantum logic gate moves to replace the second target quantum logic gate.
3. The quantum logic gate mobility judgment method according to claim 1, wherein constructing a moved quantum circuit according to the quantum circuit, the target quantum logic gate, and the movement pattern, comprises:
Generating the quantum circuit copy and the target quantum logic gate copy;
determining a target position for placing the target quantum logic gate copy in the quantum circuit copy according to the moving mode;
adding the target quantum logic gate replica to the quantum wire replica at the target location;
deleting the target quantum logic gate in the quantum circuit replica;
the new quantum wire replica is determined as a shifted quantum wire.
4. The quantum logic gate mobility judgment method according to claim 1, wherein the determining that the quantum logic gate associated with the qubit of the target quantum logic gate is the relevant quantum logic gate comprises:
according to the target quantum logic gate, a first position in the quantum circuit and a second position in the moved quantum circuit are respectively determined, wherein the first position refers to the position of the target quantum logic gate in the quantum circuit, and the second position refers to the position of the target quantum logic gate in the moved quantum circuit;
determining a third position corresponding to the second position in the quantum circuit;
acquiring all quantum logic gates corresponding to the first position to the third position in the quantum circuit;
And determining quantum logic gates in which the quantum bits in all the quantum logic gates and the quantum bits in the target quantum logic gate are intersected as relevant quantum logic gates.
5. The method according to claim 4, wherein the determining whether the first quantum wire is equivalent to the second quantum wire based on whether the relevant quantum logic gate includes only one quantum logic gate, which is the target quantum logic gate, includes:
if yes, the first quantum circuit is equivalent to the second quantum circuit.
6. The quantum logic gate mobility determination method of claim 1, wherein the determination is based on whether mat1 and mat2 are met with mat1=e iα mat2, judging whether the first quantum wire is equivalent to the second quantum wire, comprising:
if it is matched with mat1=e iα mat2, the first quantum wire is equivalent to the second quantum wire.
7. The quantum logic gate mobility determination method of claim 6, wherein the executing the second quantum wire to obtain a calculation result mat2 comprises:
determining a simplified quantum logic gate group in the second quantum circuit, wherein the simplified quantum logic gate group is at least two quantum logic gates in the second quantum circuit;
Determining a quantum logic gate equivalent to the simplified quantum logic gate set as a substitute quantum logic gate;
determining a third quantum circuit corresponding to the second quantum circuit according to the simplified quantum logic gate group and the alternative quantum logic gate;
and executing the third quantum circuit to obtain a calculation result mat2.
8. The quantum logic gate mobility determination method of claim 7, wherein the determining the simplified quantum logic gate set in the second quantum circuit comprises:
performing execution time sequence division on the quantum logic gates in the second quantum circuit to obtain quantum logic gates positioned in each execution time sequence;
and determining a simplified quantum logic gate group according to the quantum logic gates positioned in each execution time sequence.
9. The quantum logic gate mobility determination method of claim 8, wherein the simplified group of quantum logic gates is at least two quantum logic gates in the second quantum circuit that are located within different execution timings.
10. A quantum logic gate mobility determination system comprising:
the acquisition module is used for acquiring a target quantum logic gate and a moving mode in the quantum circuit;
The first determining module is used for constructing a quantum circuit after moving according to the quantum circuit, the target quantum logic gate and the moving mode;
a second determining module, configured to determine a quantum logic gate associated with a qubit of the target quantum logic gate as a relevant quantum logic gate, where the associated quantum logic gate refers to a quantum logic gate in which the qubit intersects with the qubit of the target quantum logic gate;
a third determining module, configured to determine a first quantum circuit and a second quantum circuit respectively, where the first quantum circuit is configured with related quantum logic gates in the same order as the first quantum circuit, and the second quantum circuit is configured with related quantum logic gates in the same order as the moved quantum circuit;
the judging module is used for executing the first quantum circuit to obtain a calculation result mat1; executing the second quantum circuit to obtain a calculation result mat2; based on whether mat1 and mat2 match mat1=e or not iα mat2, or, if the related quantum logic gate only comprises one quantum logic gate, and the logic gate is the target quantum logic gate, determining whether the first quantum circuit and the second quantum circuit are equivalent, wherein e iα =cosα+isinα，i 2 -1, alpha is any angle value in 0-2 pi;
and the fourth determining module is used for determining that the target quantum logic gate is movable under the condition that the judging result of the judging module is yes.
11. A storage medium having a computer program stored therein, wherein the computer program is arranged to perform the method of any of claims 1 to 9 when run.
12. An electronic device comprising a memory and a processor, characterized in that the memory has stored therein a computer program, the processor being arranged to run the computer program to perform the method of any of the claims 1 to 9.
13. A method of optimizing a quantum wire, comprising:
the judgment method according to any one of claims 1 to 9, judging the mobility of a target quantum logic gate in the quantum wire;
if the target quantum logic gate is movable, replacing the quantum circuit by using the moved quantum circuit;
determining a simplified quantum logic gate group in the moved quantum circuit, wherein the simplified quantum logic gate group is at least two quantum logic gates in the moved quantum circuit;
Determining a quantum logic gate equivalent to the simplified quantum logic gate set as a substitute quantum logic gate;
and determining an optimized quantum circuit corresponding to the moved quantum circuit according to the simplified quantum logic gate group and the alternative quantum logic gate.
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