CN116107409A - Reset control method of multi-board card control system - Google Patents
Reset control method of multi-board card control system Download PDFInfo
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- CN116107409A CN116107409A CN202211743457.2A CN202211743457A CN116107409A CN 116107409 A CN116107409 A CN 116107409A CN 202211743457 A CN202211743457 A CN 202211743457A CN 116107409 A CN116107409 A CN 116107409A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
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Abstract
The invention relates to a reset control method for a multi-board card control system, which belongs to the technical field of control circuits, and in the prior art, the reset control method is complex or a main board card does not have the capability of resetting a slave board card; the control system provided by the invention comprises a main board card and one or more slave board cards, wherein the main board card comprises an FPGA module, a power-on reset circuit, an external reset circuit, one or more interface circuits, a logic gate circuit, a monitoring circuit and a microprocessor, and can realize orderly and reliable reset of the multi-board card control system.
Description
Technical Field
The invention belongs to the technical field of control circuits, and particularly relates to a reset control method for a multi-board card control system, which is more typical and suitable for control systems formed by various multi-board cards.
Background
In a control system composed of multiple boards, there are often the following problems: (1) The main board card and the slave board card have the functions of bus communication, control and the like, and because the design and the composition of each main board card and each slave board card are complex, the reset loading time of each board card is different after the power-on, and before the reset loading of the main board card is finished, if the slave board card is finished to reset, false triggering, false state and false action can be caused; (2) The main board card does not have the capability of resetting the slave board card, and after the work of the slave board card is abnormal, the main board card and other normal slave board cards can be interrupted to cause other losses by resetting and initializing the board card only through the power-off and power-on operation of the slave board card and even the whole system, so that the complex design and control of the power supply system are required for independently powering off and power-on the slave board card, and the power-off and power-on operation of the whole system is interrupted.
Disclosure of Invention
In response to one or more of the above-identified deficiencies or improvements in the prior art, the present invention provides a reset control method for a multi-board control system, the reset control method comprising a power-on reset control method and an external reset control method, the power-on reset control method comprising the steps of,
step S11: when the system is powered on, a power-on reset circuit of the main board card outputs a signal to the FPGA module to enable the FPGA module to enter power-on loading; the method comprises the steps that in the power-on loading process of an FPGA module, the FPGA module outputs a state signal and an external reset output signal to a logic gate circuit, wherein the state signal is of a low level, the external reset output signal is kept to be of a high level, and the output signal of the logic gate circuit is of a low level;
step S12: the monitoring circuit receives the output signal of the logic gate as an input signal, when the input signal is in a low level, the output signal of the monitoring circuit is a reset signal, after the output signal of the logic gate circuit is in a high level and is delayed for a plurality of times, the output signal of the monitoring circuit is a non-reset signal, and a microprocessor and other circuits of the main board card receive the output signal of the monitoring circuit;
step S13: after the FPGA module is powered on and loaded, the state signal of the FPGA module becomes high level, the output signal of the logic gate circuit becomes high level, and the output signal of the monitoring circuit is a non-reset signal, so that the reset of a microprocessor and other circuits of the mainboard card is completed;
step S14: the output signal of the monitoring circuit is connected to the FPGA module to realize the reset of the FPGA of the main board card;
step S15: the FPGA module outputs a reset signal to the slave board card through the interface circuit, and after the power-on reset of the main board card is finished, the reset control of the slave board card is released;
step S16: if the power-on loading time of the slave board card is longer than that of the main board card, on the basis of grasping the specific power-on loading time of the slave board card, the microprocessor can send out a reset control signal to enable the reset signal corresponding to the slave board card to keep in a slave board card reset state, and the FPGA module can also directly control the reset signal of the slave board card to keep until the reset time of the slave board card meets the requirement;
the external reset control method includes the steps of,
step S21: after the external reset signal is processed by the external reset circuit, an external reset input signal is output to the FPGA module, the external reset locking signal is kept in an invalid state under the condition that external reset is allowed, the external reset output signal is output to be low level by the FPGA module, the logic gate output signal is enabled to be low level through the logic gate circuit, then the monitoring circuit output signal is a reset signal, and the microprocessor, other circuits and the FPGA module of the main board card receive the output signal of the monitoring circuit; according to the application scene requirement, the state of a reset signal of the slave board card is controlled by the main board card, and the slave board card is controlled to reset or not reset;
step S22: after the external reset signal is withdrawn, the FPGA module outputs an external reset output signal to become high level, then the output signal of the logic gate circuit becomes high level, and after a plurality of time delays, the output signal of the monitoring circuit is a non-reset signal;
step S23: and under the condition that external reset is not allowed, the microprocessor outputs an external reset locking signal, and the external reset output signal output by the FPGA module is kept to be high level.
Preferably, the monitoring circuit has a voltage monitoring function, and keeps the output signal of the monitoring circuit in a reset state before the power supply voltage VCC of the monitoring circuit is not established to an effective level, and after the power supply voltage VCC is established to the effective level, the output signal of the monitoring circuit is controlled by the input port state of the monitoring circuit;
preferably, the input port of the monitoring circuit is a manual reset input port;
preferably, according to the difference of the reset effective levels of the microprocessor, the other circuits and the FPGA module, the output signal of the monitoring circuit may be accessed to the microprocessor, the other circuits and the FPGA module after passing through a logic non-circuit to realize the reset.
In general, the above technical solutions conceived by the present invention have the beneficial effects compared with the prior art including:
(1) The invention provides a reset control method of a multi-board card control system, which can realize orderly and reliable reset of the multi-board card control system.
Drawings
Fig. 1 is an application diagram of a reset control method of a multi-board card control system provided by the invention.
Like reference numerals denote like technical features throughout the drawings, in particular:
1. motherboard 2, slave boards 1,3, slave boards n,4, logic gate circuits, 5 and monitoring circuits.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention. In addition, the technical features of the embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
The multi-board card control system comprises a main board card 1, a first slave board card 2 and an Nth slave board card 3, wherein the main board card 1 comprises an FPGA module, a power-on reset circuit, an external reset circuit, a plurality of interface circuits, a logic gate circuit 4, a monitoring circuit 5, a microprocessor and other circuits;
the first slave board card 2 comprises a controller, a power-on reset circuit and an interface circuit, and the Nth slave board card 3 and the first slave board card 2 have the same structure and/or composition; the interface circuits of the main board card 1 are in one-to-one butt joint with the interface circuits of the slave board cards.
When the system is powered on:
(1) The power-on reset circuit of the mainboard card outputs signals to the FPGA to enable the FPGA to enter power-on loading, the FPGA state signal is low level in the power-on loading process of the FPGA, the external reset output signal is high level, the FPGA state signal and the external reset output signal pass through the logic gate circuit, and the output signal of the logic gate circuit is low level;
(2) The monitoring circuit has a voltage monitoring function, and keeps an output signal of the monitoring circuit in a reset state before the power supply voltage VCC of the monitoring circuit is not established to an effective level, and the output signal of the monitoring circuit is controlled by an input port state of the monitoring circuit after the power supply voltage VCC is not established to the effective level;
(3) The input port of the monitoring circuit is a manual reset input port, when the output signal of the accessed logic gate circuit is at a low level, the output signal is kept at a reset state, and after the output signal of the logic gate circuit is at a high level and is delayed for a plurality of times, the output signal is at a non-reset state;
(4) After the power-on loading of the mainboard card FPGA is finished, the FPGA state signal is changed into a high level, then the output signal of the logic gate circuit is changed into a high level, and then the output signal of the monitoring circuit is in a non-reset state, so that the reset of the mainboard card microprocessor and other circuits is finished;
(5) The output signal of the monitoring circuit is connected to the FPGA to realize the reset of the FPGA of the main board card;
(6) The method comprises the steps that a plurality of reset signals for the slave board cards are kept in a reset state during the power-on loading process of the FPGA, and reset control for the slave board cards is released after the power-on reset of the master board cards is completed;
(7) If the power-on loading time of the slave board card is longer than that of the main board card, on the basis of grasping the specific power-on loading time of the slave board card, the main board card can send out a reset control signal through a microprocessor, so that the reset signal corresponding to the slave board card can be kept in a reset state of the slave board card, and the reset signal of the slave board card can be directly controlled by an FPGA to be kept until the reset time of the slave board card meets the requirement;
when external reset:
(1) When the external reset signal is effective, the external reset signal is processed by the external reset circuit of the main board card and then is output to the FPGA, the external reset locking signal is kept in an invalid state in the scene of allowing external reset, the FPGA outputs an external reset output signal to be in a low level, the logic gate circuit enables the logic gate output signal to be in a low level, and then the monitoring circuit outputs the signal to be in a reset state;
(2) After the external reset signal is withdrawn, the FPGA outputs an external reset output signal to be changed into a high level, then the output signal of the logic gate circuit is changed into a high level, and after a plurality of time delays, the reset state of the output signal of the monitoring circuit is withdrawn;
(3) When the external reset is performed, the state of a reset signal of the slave board card can be controlled by the main board card according to the application scene requirement, and the slave board card is controlled to reset or not reset;
(4) In the scene of not allowing external reset, the external reset locking signal is kept in an active state, the external reset output signal output by the FPGA is kept at a high level, and the external reset input signal of external reset is not responded.
After power-on, when the slave board card needs to be reset:
after power-on work, when the slave board card works abnormally or needs to be reset due to other reasons, a corresponding reset control signal is sent to the FPGA by the main board card microprocessor, and the corresponding slave board card reset signal is controlled to be in a slave board card reset state by the FPGA, so that the reset of the slave board card is realized.
According to the difference of reset effective levels of all chips of the main board card, the output signals of the monitoring circuit can be accessed to the specific chip to realize reset after passing through the logic non-circuit.
According to the difference of reset effective levels of chips of the slave board card, the slave board card reset signal output by the main board card can be processed by the interface circuit and then is connected to a specific chip to realize reset.
The reset control signal sent by the mainboard card microprocessor to the FPGA can be in a single path or multiple paths, can be an IO signal, and can also be in other control modes such as instruction control;
the reset signals of the main board card to the slave board card can be in a single way or in multiple ways; the interface circuit is used for converting the signals into single-ended signals such as IO signals or differential signals with stronger anti-interference performance;
the external reset locking signal sent by the mainboard card microprocessor to the FPGA can be an IO signal or other control modes such as instruction control;
the FPGA shown here is an example of a programmable logic control device, and it may also be other controllers with corresponding functions;
it will be readily appreciated by those skilled in the art that the foregoing description is merely a preferred embodiment of the invention and is not intended to limit the invention, but any modifications, equivalents, improvements or alternatives falling within the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (6)
1. The reset control method of the multi-board card control system is characterized in that the system comprises a main board card and one or more slave board cards, wherein the main board card comprises an FPGA module, a power-on reset circuit, an external reset circuit, one or more interface circuits, a logic gate circuit, a monitoring circuit and a microprocessor;
the reset control method comprises a power-on reset control method and an external reset control method, the power-on reset control method comprises the following steps,
step S11: when the system is powered on, the power-on reset circuit outputs a signal to the FPGA module to enable the FPGA module to enter power-on loading; the FPGA module outputs a state signal and an external reset output signal to the logic gate circuit in the power-on loading process of the FPGA module, the state signal is low level, the external reset output signal is kept high level, and the output signal of the logic gate circuit is low level;
step S12: the monitoring circuit receives the output signal of the logic gate as an input signal, when the input signal is in a low level, the output signal of the monitoring circuit is a reset signal, after the output signal of the logic gate circuit is in a high level and is delayed for a plurality of times, the output signal of the monitoring circuit is a non-reset signal, and the microprocessor receives the output signal of the monitoring circuit;
step S13: after the FPGA module is powered on and loaded, the state signal of the FPGA module becomes high level, the output signal of the logic gate circuit becomes high level, and the output signal of the monitoring circuit is a non-reset signal, so that the reset of the microprocessor is completed;
step S14: the output signal of the monitoring circuit is connected to the FPGA module to realize the resetting of the FPGA;
step S15: the FPGA module outputs a reset signal to the slave board card through the interface circuit, and after the power-on reset of the main board card is completed, the reset control of the slave board card is released;
step S16: if the power-on loading time of the slave board card is longer than that of the main board card, on the basis of grasping the specific power-on loading time of the slave board card, the microprocessor can send out a reset control signal to enable the reset signal corresponding to the slave board card to keep in the reset state of the slave board card, or the FPGA module can directly control the reset signal of the slave board card to keep until the reset time of the slave board card meets the requirement;
the external reset control method includes the steps of,
step S21: after the external reset signal is processed by the external reset circuit, an external reset input signal is output to the FPGA module, the external reset locking signal is kept in an invalid state under the condition of allowing external reset, the FPGA module outputs an external reset output signal to be in a low level, the logic gate circuit enables a logic gate output signal to be in a low level, then the monitoring circuit output signal is a reset signal, and the microprocessor and the FPGA module receive the output signal of the monitoring circuit; according to the application scene requirement, the state of the reset signal of the slave board card is controlled by the main board card, and the slave board card is controlled to reset or not reset;
step S22: after the external reset signal is withdrawn, the FPGA module outputs an external reset output signal to become high level, then the output signal of the logic gate circuit becomes high level, and after a plurality of time delays, the output signal of the monitoring circuit is a non-reset signal;
step S23: and under the condition that external reset is not allowed, the microprocessor outputs an external reset locking signal, and the external reset output signal output by the FPGA module is kept to be high level.
2. The method according to claim 1, characterized in that: the monitoring circuit has a voltage monitoring function, and keeps the output signal of the monitoring circuit in a reset state before the power supply voltage VCC of the monitoring circuit is not established to an effective level, and the output signal of the monitoring circuit is controlled by the state of the input port of the monitoring circuit after the power supply voltage VCC is established to the effective level.
3. The method according to claim 1, characterized in that: the input port of the monitoring circuit is a manual reset input port.
4. The method according to claim 1, characterized in that: according to the difference of reset effective levels of the microprocessor and the FPGA module, the output signal of the monitoring circuit can be accessed into the microprocessor and the FPGA module to realize reset after passing through a logic non-circuit.
5. The method according to claim 1, characterized in that: the main board card comprises other circuits; in the step S12, after a delay for a plurality of times, the output signal of the monitoring circuit is a non-reset signal, and the microprocessor and the other circuits receive the output signal of the monitoring circuit.
6. The method according to claim 5, wherein: in step S13, the monitor circuit outputs a non-reset signal to complete the reset of the microprocessor and other circuits of the motherboard card.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202211743457.2A CN116107409A (en) | 2022-12-30 | 2022-12-30 | Reset control method of multi-board card control system |
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| CN202211743457.2A CN116107409A (en) | 2022-12-30 | 2022-12-30 | Reset control method of multi-board card control system |
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| CN202211743457.2A Pending CN116107409A (en) | 2022-12-30 | 2022-12-30 | Reset control method of multi-board card control system |
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