CN116097233A8 - Memory chip, memory device and access method thereof - Google Patents

Memory chip, memory device and access method thereof Download PDF

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Publication number
CN116097233A8
CN116097233A8 CN202080104318.8A CN202080104318A CN116097233A8 CN 116097233 A8 CN116097233 A8 CN 116097233A8 CN 202080104318 A CN202080104318 A CN 202080104318A CN 116097233 A8 CN116097233 A8 CN 116097233A8
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CN
China
Prior art keywords
memory
flash memory
access
storage
memory medium
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202080104318.8A
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Chinese (zh)
Other versions
CN116097233A (en
Inventor
王祥林
鲁傚禹
刘光辉
金颀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Publication of CN116097233A publication Critical patent/CN116097233A/en
Publication of CN116097233A8 publication Critical patent/CN116097233A8/en
Pending legal-status Critical Current

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

The application provides a memory chip, a memory device and an access method thereof, which can solve the problem that the access performance of a memory is reduced when the capacity of single media particles is increased under the condition that the total capacity of the memory device is unchanged, thereby improving the access rate of the memory. The controller of the memory chip may determine an access mode for accessing the flash memory medium based on a number relationship of the memory channels and the flash memory medium. If the access mode of accessing the flash memory medium is a wide-mouth mode, if the number of storage channels is greater than that of the flash memory medium, the controller can combine part or all of the storage channels, so that the combined first channel comprises at least one associated storage channel, and the flash memory medium is accessed through the combined first channel, and the data line width of the storage channel which can be used by the corresponding flash memory medium can be increased through the combination of the storage channels, thereby improving the read-write performance of the storage chip and further improving the access efficiency of the memory.
CN202080104318.8A 2020-11-27 2020-11-27 Memory chip, memory device and access method thereof Pending CN116097233A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/132076 WO2022109975A1 (en) 2020-11-27 2020-11-27 Storage chip, and storage device and access method therefor

Publications (2)

Publication Number Publication Date
CN116097233A CN116097233A (en) 2023-05-09
CN116097233A8 true CN116097233A8 (en) 2023-06-16

Family

ID=81755104

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202080104318.8A Pending CN116097233A (en) 2020-11-27 2020-11-27 Memory chip, memory device and access method thereof

Country Status (2)

Country Link
CN (1) CN116097233A (en)
WO (1) WO2022109975A1 (en)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10474599B1 (en) * 2017-01-31 2019-11-12 Xilinx, Inc. Striped direct memory access circuit
CN107133011B (en) * 2017-04-25 2020-06-12 电子科技大学 Multichannel data storage method of oscillograph
CN110134366B (en) * 2019-05-21 2022-10-11 合肥工业大学 Method and device for parallel writing in multi-channel FIFO
CN111045963A (en) * 2019-12-15 2020-04-21 苏州浪潮智能科技有限公司 Method and device for reading and writing high-bit-width bus
CN111158600B (en) * 2019-12-30 2023-10-27 中国人民解放军国防科技大学 Device and method for improving access efficiency of High Bandwidth Memory (HBM)

Also Published As

Publication number Publication date
CN116097233A (en) 2023-05-09
WO2022109975A1 (en) 2022-06-02

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Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CI02 Correction of invention patent application
CI02 Correction of invention patent application

Correction item: PCT international application to national stage day

Correct: 2023.02.03

False: 2023.02.01

Number: 19-01

Page: The title page

Volume: 39

Correction item: PCT international application to national stage day

Correct: 2023.02.03

False: 2023.02.01

Number: 19-01

Volume: 39