CN116093227A - Vertical structure deep ultraviolet LED chip and manufacturing method thereof - Google Patents
Vertical structure deep ultraviolet LED chip and manufacturing method thereof Download PDFInfo
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- CN116093227A CN116093227A CN202111316647.1A CN202111316647A CN116093227A CN 116093227 A CN116093227 A CN 116093227A CN 202111316647 A CN202111316647 A CN 202111316647A CN 116093227 A CN116093227 A CN 116093227A
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Abstract
The invention discloses a deep ultraviolet LED structure with a vertical structure and a manufacturing method thereof. The vertical structure deep ultraviolet LED structure comprises an epitaxial layer, wherein the epitaxial layer comprises a first conductive semiconductor layer, an active layer, a second conductive semiconductor layer and the like; the epitaxial layer is provided with a first surface and a second surface which are opposite to each other, the second surface is far away from the first conductive semiconductor layer, at least one second groove is further formed in the second surface, the bottom surface of the second groove is distributed on the first surface of the epitaxial layer, the bottom surface of the second groove is covered with a protective layer, and meanwhile, the second groove is filled with a stress matching material. The invention can effectively prevent or eliminate the problems of epitaxial layer falling and the like caused by overlarge epitaxial layer stress when removing the epitaxial substrate, can obviously improve the light emitting of the deep ultraviolet LED device in the horizontal direction, improves the light extraction efficiency, is also beneficial to effectively reducing the risk of leakage of the side wall of the device, greatly improves the production yield of the device and improves the reliability of the device.
Description
Technical Field
The invention relates to a manufacturing method of an LED chip, in particular to a deep ultraviolet LED chip with a vertical structure and a manufacturing method thereof, and belongs to the field of semiconductor photoelectric devices.
Background
The III-V nitride semiconductor is called a third generation semiconductor material, has the advantages of large forbidden bandwidth, good chemical stability, strong radiation resistance and the like, and the forbidden bandwidth covers the range from deep ultraviolet, whole visible light to near infrared, and can be used for manufacturing semiconductor light-emitting devices such as light-emitting diodes, lasers, superluminescent light-emitting diodes and the like. The deep ultraviolet light-emitting diode based on III-V nitride has the advantages of energy conservation, environmental protection, simple manufacture, small volume, light weight, long service life and the like, and has wide market application prospect in the aspects of sterilization and disinfection, water purification, ultraviolet light curing, plant illumination, jewelry identification and the like.
The deep ultraviolet LED has a problem of low light extraction efficiency, and one of the important reasons is that the epitaxial structure of the deep ultraviolet LED is generally formed by growing sapphire or silicon material as a substrate and AlN as a buffer layer, and the internal materials, especially the silicon substrate and the AlN buffer layer, have serious light absorption in the deep ultraviolet band. The substrate and the buffer layer can be removed from the deep ultraviolet LED with the vertical structure, so that the light absorption of the substrate and the buffer layer is greatly reduced, and the light extraction efficiency is improved. However, because of the very large lattice mismatch and thermal mismatch among the substrate, the buffer layer and the materials of the deep ultraviolet LED epitaxial structure, very large stress can be accumulated in the epitaxial growth, and in the process of removing the substrate, the stress accumulated in the epitaxial growth can be released, and the stress in the release process can cause the epitaxial film to be not supported and further fall off. In addition, for the AlGaN-based deep ultraviolet LED, as the Al component increases, the light-emitting wave band is shorter and shorter, the light-emitting duty ratio in the horizontal direction is greatly improved, and the problem that the light emitted in the horizontal direction is difficult to take light is also caused.
Disclosure of Invention
The invention mainly aims to provide a deep ultraviolet LED chip with a vertical structure and a manufacturing method thereof, so as to overcome the defects of the prior art.
In order to achieve the purpose of the invention, the technical scheme adopted by the invention comprises the following steps:
one aspect of the invention provides a vertical structure deep ultraviolet LED chip, which comprises an epitaxial layer, wherein the epitaxial layer comprises a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer which are sequentially stacked, the first conductive semiconductor layer is electrically connected with a first electrode, and the second conductive semiconductor layer is electrically connected with a second electrode;
further, the epitaxial layer is provided with a first surface and a second surface which are opposite, the second surface is far away from the first conductive semiconductor layer, at least one second groove is further formed in the second surface, the bottom surface of the second groove is distributed in the epitaxial layer or on the first surface, at least the bottom surface of the second groove is covered with a protective layer, and meanwhile, the second groove is filled with a stress matching material.
Further, a second insulating layer, a second reflecting layer, and the like are further formed on the inner wall of the second trench, the second insulating layer continuously covers the second trench inner wall, the protective layer, and the second conductive semiconductor layer, the second reflecting layer continuously covers the second insulating layer, and the second reflecting layer is connected with the bonding substrate via the bonding barrier layer, the bonding layer, and the like.
Another aspect of the present invention provides a method for manufacturing a vertical structure deep ultraviolet LED chip, including: the method comprises the steps of growing an epitaxial layer on an epitaxial substrate and manufacturing a first electrode and a second electrode which are matched with the epitaxial layer, wherein the epitaxial layer comprises a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer which are sequentially stacked, the first conductive semiconductor layer is electrically connected with the first electrode, and the second conductive semiconductor layer is electrically connected with the second electrode;
further, the manufacturing method further comprises the following steps:
at least one second groove is formed on the second surface of the epitaxial layer, the bottom surface of the second groove is distributed in the epitaxial layer or on the first surface of the epitaxial layer, the second surface is far away from the first conductive semiconductor layer, and the first surface is opposite to the second surface; and
and covering a protective layer on at least the bottom surface of the second groove, and filling a stress matching material in the second groove.
Further, the manufacturing method further comprises the following steps: and after the bottom surface of the second groove is covered with the protective layer, forming a second insulating layer, a second reflecting layer and the like on the inner wall of the second groove, filling a stress matching material in the second groove, bonding the second reflecting layer with a bonding substrate, removing the epitaxial substrate, and at least partially removing a buffer layer distributed between the epitaxial substrate and the first conductive semiconductor layer.
Compared with the prior art, the method has the advantages that the grooves are formed in the epitaxial layer of the deep ultraviolet LED, the protective layer and the filling stress matching material are arranged in the grooves, and then the epitaxial layer is bonded with the bonding layer, so that the stress balance of the whole epitaxial layer can be achieved under the combined action of the bonding layer and the stress matching material, the problem that the epitaxial layer falls off due to overlarge stress of the epitaxial layer when a substrate is removed is solved, meanwhile, the light emergent effect of the deep ultraviolet LED device in the horizontal direction can be remarkably improved, the light extraction efficiency is improved, the risk of leakage of the side wall of the device is effectively reduced, the production yield of the device is greatly improved, and the reliability of the device is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present invention, and other drawings may be obtained according to the drawings without inventive effort to those skilled in the art.
FIG. 1 is a cross-sectional view of a deep ultraviolet LED epitaxial structure bonded to a bonding substrate prior to removal of the epitaxial substrate in an embodiment of the present invention;
FIG. 2 is an enlarged schematic view of a region selected from the dashed box in FIG. 1;
FIG. 3 is a cross-sectional view of a deep ultraviolet LED epitaxial structure bonded to a bonding substrate after removal of the epitaxial substrate in an embodiment of the present invention;
FIG. 4 is a cross-sectional view of the deep ultraviolet LED epitaxial structure of FIG. 3 after further processing;
FIG. 5 is an enlarged schematic view of a region selected from the dashed box in FIG. 4;
FIG. 6 is a top view of a deep ultraviolet LED device in accordance with one embodiment of the present invention;
reference numerals illustrate: 110 epitaxial substrate, 111 buffer layer, 112 first conductive semiconductor layer (n-type layer), 113 active layer, 114 second conductive semiconductor layer (p-type layer), 115 first insulating layer, 116 first electrode (n-electrode), first trench 117, second trench 118, 120 second electrode, first reflective layer (p-electrode), 121 second electrode connection layer (p-first pad connection layer), 130 protective layer, 131 second insulating layer, 132 second reflective layer, 133 stress matching fill layer, 140 bonding barrier layer and bonding layer, 150 bonding substrate, 160 first pad.
Detailed Description
As described above, in the conventional vertical structure deep ultraviolet LED, the problem of epitaxial layer falling off due to excessive residual stress in the material is often encountered in the process of removing the epitaxial substrate, and therefore, the present inventors have long studied and practiced a lot, and have proposed the technical scheme of the present application, as described below.
Some embodiments of the present invention provide a vertical structure deep ultraviolet LED structure, including an epitaxial layer, where the epitaxial layer includes a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer that are sequentially stacked, the first conductive semiconductor layer is electrically connected to a first electrode, and the second conductive semiconductor layer is electrically connected to a second electrode; the epitaxial layer is provided with a first surface and a second surface which are opposite, the second surface is far away from the first conductive semiconductor layer, at least one second groove is further formed in the second surface, the bottom surface of the second groove is distributed in the epitaxial layer or on the first surface, at least the bottom surface of the second groove is covered with a protective layer, and meanwhile, the second groove is filled with a stress matching material.
Wherein, by processing the second groove on the epitaxial layer before bonding the epitaxial layer with the bonding substrate, the effect of releasing the stress of the epitaxial layer in advance can be achieved to a certain extent, but the effect of releasing the stress is limited only by the second groove. In this application through processing out after the second slot, set up the protective layer at the second slot tank bottom again and fill stress matching material in the second slot, on the one hand can prevent that the second slot from being destroyed in the removal epitaxial substrate in-process, and the other party can also make second slot, protective layer and stress matching material and bonding layer combined action reach the stress balance, reduces even eliminates the epitaxial layer drop problem that leads to because of epitaxial layer stress is too big when getting rid of epitaxial substrate.
In some embodiments, a second insulating layer is further formed on the inner wall of the second trench, the second insulating layer continuously covers the second trench inner wall, the protective layer, and the second conductive semiconductor layer, and the second insulating layer is connected to the bonding substrate via the bonding layer. By arranging the second insulating layer, the problems of leakage of the side wall of the device and the like can be reduced or even eliminated.
Preferably, the groove wall of the second groove is obliquely arranged and forms an included angle of 30-60 degrees with the first surface or the second surface of the epitaxial layer, so that light emitted by the device can be more effectively reflected back to the interior of the device or the light-emitting surface of the device, and the light extraction efficiency of the device is improved.
In some embodiments, the second trenches are a plurality of and are spaced apart on the epitaxial layer.
In some embodiments, the bottom surface of the second groove is distributed on the first surface.
In some embodiments, the epitaxial layer further includes a buffer layer, the first conductive semiconductor layer is formed on one side surface of the buffer layer, and the other side surface of the buffer layer is the first side.
In some embodiments, a side surface of the first conductive semiconductor layer remote from the active layer is the first face.
In some embodiments, the second insulating layer is further continuously covered with a second reflective layer, and the stress matching material is distributed between the second reflective layer and the bonding layer. By using the second reflecting layer, the light of the side wall of the device can be further reflected back to the surface, and the light extraction efficiency is increased. The second reflective layer may be formed of a highly reflective material such as Al.
In some embodiments, a bonding barrier layer is further distributed between the bonding layer and the second reflective layer, so as to prevent diffusion of metal elements in the bonding layer to the epitaxial layer.
In some embodiments, the second electrode is distributed between the second insulating layer and the second conductive semiconductor layer, and the second electrode is electrically coupled with the second conductive semiconductor layer. Preferably, the second electrode forms an ohmic contact with the second conductive semiconductor layer.
In some embodiments, the second electrode is further used to form a first reflective layer.
In some embodiments, the second conductive semiconductor layer is further covered with a first insulating layer.
In some embodiments, the second surface of the epitaxial layer is further provided with at least one first trench, the bottom surface of the first trench is distributed inside the first conductive semiconductor layer or on the surface of the first conductive semiconductor layer, and the first electrode is at least partially disposed in the first trench and is in electrical contact with the first conductive semiconductor layer, for example, forms an ohmic contact.
In some embodiments, the first trenches are a plurality and are spaced apart on the epitaxial layer.
In some embodiments, the first electrode is integrally disposed within the first trench and directly bonded to the second reflective layer.
In some embodiments, the inner wall of the first trench is further covered with a first insulating layer, and the first insulating layer extends continuously to the surface of the second conductive semiconductor layer.
In some embodiments, the first electrode is disposed within the first trench and in contact with the second reflective layer.
In some embodiments, the second electrode is further in electrical contact with a second electrode connection layer disposed between the second electrode and a second insulating layer.
In some embodiments, the first surface of the epitaxial layer has a surface roughening structure, so as to further improve the light extraction efficiency of the device.
In some embodiments, a third trench is further formed on the first surface of the epitaxial layer, a bottom surface of the third trench reaches the surface of the second electrode connection layer, and a first bonding pad is disposed in the third trench and is in electrical contact with the second electrode connection layer.
In some embodiments, the third trenches are a plurality of and are spaced apart on the epitaxial layer.
In some embodiments, the first conductive semiconductor layer is formed on an epitaxial substrate, and a buffer layer is further distributed between the first conductive semiconductor layer and the epitaxial substrate.
Some embodiments of the present invention further provide a method for manufacturing a deep ultraviolet LED structure with a vertical structure, including a step of forming an epitaxial layer by growing on an epitaxial substrate, and a step of manufacturing a first electrode and a second electrode that are matched with the epitaxial layer, where the epitaxial layer includes a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer that are sequentially stacked, and the first conductive semiconductor layer is electrically connected to the first electrode, and the second conductive semiconductor layer is electrically connected to the second electrode;
the manufacturing method further comprises the following steps:
at least one second groove is formed on the second surface of the epitaxial layer, the bottom surface of the second groove is distributed in the epitaxial layer or on the first surface of the epitaxial layer, the second surface is far away from the first conductive semiconductor layer, and the first surface is opposite to the second surface; and
and covering a protective layer on at least the bottom surface of the second groove, and filling a stress matching material in the second groove.
In some embodiments, the method of making further comprises: and the groove wall of the second groove is obliquely arranged and forms an included angle of 30-60 degrees with the first surface or the second surface of the epitaxial layer.
In some embodiments, the manufacturing method specifically includes:
covering a protective layer on the bottom surface of the second groove;
forming a second insulating layer on the inner wall of the second trench, and continuously covering the second trench inner wall, the protective layer and the second conductive semiconductor layer by the second insulating layer;
forming a second reflective layer on the second insulating layer;
filling a stress matching material in the second groove;
bonding the second reflecting layer with a bonding substrate through a bonding layer;
the epitaxial substrate is removed and a buffer layer distributed between the epitaxial substrate and the first conductive semiconductor layer is at least partially removed.
In some embodiments, the buffer layer may be partially removed, and a side surface of the buffer layer away from the first conductive semiconductor layer may be used as the first surface of the epitaxial layer.
In some embodiments, the buffer layer may be completely removed, and a side surface of the first conductive semiconductor layer remote from the active layer may be used as the first surface of the epitaxial layer.
In some embodiments, the epitaxial substrate and buffer layer may also be completely removed.
In some embodiments, a buffer layer, a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer may be sequentially grown on an epitaxial substrate.
In some embodiments, the manufacturing method specifically includes:
at least one first groove is formed on the second surface of the epitaxial layer, and the bottom surface of the first groove is distributed in the first conductive semiconductor layer or on the surface of the first conductive semiconductor layer;
disposing a first electrode on the first conductive semiconductor layer, and disposing the first electrode at least partially within the first trench and in electrical contact with the first conductive semiconductor layer;
forming a continuous first insulating layer on the inner wall of the first groove, and enabling the first insulating layer to extend to the surface of the second conductive semiconductor layer;
forming a window on the first insulating layer to expose the area corresponding to the second electrode on the surface of the second conductive semiconductor layer, and then manufacturing and forming the second electrode in the window;
and forming the second groove on the second surface of the epitaxial layer.
In some embodiments, the method of making further comprises: and a second electrode connecting layer is arranged on the second electrode, the second electrode connecting layer is electrically contacted with the second electrode, and then a second insulating layer and a second reflecting layer are covered on the second electrode connecting layer.
In some embodiments, the method of making further comprises: and coarsening the first surface of the epitaxial layer.
In some embodiments, the method of making further comprises: and a bonding barrier layer is arranged between the bonding layer and the second reflecting layer.
In some embodiments, the method of making further comprises: and a third groove is formed on the first surface of the epitaxial layer, the bottom surface of the third groove reaches the surface of the second electrode connecting layer, a first bonding pad is formed in the third groove, and the first bonding pad is electrically contacted with the second electrode connecting layer.
In the above embodiment of the present invention, the first conductive semiconductor layer may be an n-type layer, the second conductive semiconductor layer may be a p-type layer, the active layer may be a multiple quantum well or the like, and accordingly, the first electrode may be an n-electrode and the second electrode may be a p-electrode.
In the above embodiments of the present invention, the epitaxial layer may be formed of a III-V compound, such as GaN, alGaN, inGaN, alInGaN, etc., and is not limited thereto.
In the above embodiments of the present invention, the first and second electrodes may be formed of a metal material such as Cu, ag, au, ni, cr, al, rh, V, ti, pt, mo, in, sn or the like or an alloy thereof and any one or more combinations of metal oxides such as ITO or the like, and are not limited thereto.
In the above embodiments of the present invention, the first insulating layer and the second insulating layer may be formed of an insulating material such as aluminum nitride, silicon oxide, or the like, and are not limited thereto.
In the above embodiment of the present invention, the material of the protective layer is a corrosion-resistant material, such as Cr, pt, au, or an alloy thereof, and the thickness thereof is preferably 100nm to 500nm.
In the above embodiments of the present invention, the material of the epitaxial substrate includes silicon, sapphire, silicon carbide, gallium nitride, aluminum nitride, etc., or a combination thereof, and the material of the buffer layer may be selected from aluminum nitride, etc., but is not limited thereto.
In the above embodiments of the present invention, the bonding layer may be made of AuSn, niSn, cuSn, agSn, auln, auAu, etc., and is not limited thereto.
In the above embodiments of the present invention, the material of the bonding substrate may be selected from conductive materials such as silicon, copper, molybdenum-copper alloy, and the like, and is not limited thereto.
The technical scheme of the present invention is further described in detail below with reference to several preferred embodiments and the accompanying drawings, and the embodiments are implemented on the premise of the technical scheme of the present invention, and detailed implementation manners and specific operation processes are given, but the protection scope of the present invention is not limited to the following embodiments.
Embodiment 1 the method for manufacturing a deep ultraviolet LED device with a vertical structure provided in this embodiment mainly includes the following steps:
s1, growing a deep ultraviolet LED epitaxial structure, which comprises the steps of sequentially epitaxially growing a buffer layer 111, a first conductive semiconductor layer 112 (n-type layer), an active layer 113 (multiple quantum well) and a second conductive semiconductor layer 114 (p-type layer) on an epitaxial substrate 110 to obtain an epitaxial wafer. Wherein the material of the epitaxial substrate is sapphire (Al 2 O 3 ) The deposition method may be Metal Organic Chemical Vapor Deposition (MOCVD), molecular Beam Epitaxy (MBE), hydride Vapor Phase Epitaxy (HVPE), or the like, and is not limited thereto. Optionally, an electron blocking layer (EBL, not shown in fig. 1-5) may also be grown between the active layer 113 and the second conductive semiconductor layer 114 to reduce electron injection of the first conductive semiconductor layer 112 into the second conductive semiconductor layer 114. The material of the buffer layer is preferably AlN, and the thickness is preferably 1-4 μm, but is not limited thereto. The material of the first conductive semiconductor layer 112 is preferably Si-doped n-type Al x1 Ga 1-x1 N(0≤X 1 And 1. Ltoreq.1), the thickness is preferably 1 to 4. Mu.m. The active layer may emit deep ultraviolet light of 200-340nm, which may include a well layer and a barrier layer, or may also have any one of a single well structure, a multi-well structure, a single quantum well structure, a multi-quantum well (MQW) structure, a quantum dot structure, or a quantum wire structure. The material of the second conductive semiconductor layer 114 is preferably Mg-doped p-type Al x2 Ga 1-x2 N(0≤X 2 And.ltoreq.1), the thickness is preferably 0.05 to 0.2. Mu.m, but is not limited thereto.
S2, cleaning the epitaxial wafer, namely organic cleaning and inorganic cleaning, wherein the organic cleaning can be propanol and ethanol, and the inorganic cleaning can be sulfuric acid and hydrogen peroxide mixed solution and hydrochloric acid to remove impurities and dirt on the surface of the epitaxial wafer.
And S3, annealing the epitaxial wafer, and effectively activating Mg for the p-type layer.
And S4, photoetching is carried out on the surface (the surface can be defined as a second surface) of the epitaxial wafer, and then a first groove is formed by etching through a dry etching process or a wet etching process, wherein the preferred etching process is ICP (inductively coupled plasma) and the like, and the etching position penetrates through the second conductive semiconductor layer 114, the active layer 113 and part of the first conductive semiconductor layer 112 to form a first groove 117. The location and structure of the first trench may be as shown in fig. 1 and fig. 2.
And S5, photoetching is carried out on the second surface of the epitaxial wafer again, then metal is deposited, the preferred deposition process is electron beam evaporation, magnetron sputtering and the like, the preferred metal is one or a combination of a plurality of metals of Cr, al, ti, ni, au, pt, V and the like, photoresist is stripped and removed, a first electrode 116 (n electrode) is formed, and then annealing is carried out, so that good ohmic contact is formed. The location and structure of the first electrode 116 can also be shown with reference to fig. 1 and 2.
S6, depositing a first insulating layer 115 on the second surface of the epitaxial wafer, wherein the preferred deposition process is PECVD, ICPCVD, LPCVD, ALD, and the preferred deposition material is SiO 2 、SiN、Al 2 O 3 And the like. The first insulating layer 115 continuously covers the first trench walls and other areas of the second side of the epitaxial wafer. The location and structure of the first insulating layer 115 can also be shown with reference to fig. 1 and 2.
And S7, photoetching is carried out again, and windows are formed on the first insulating layer 115, wherein a preferable window forming process is wet etching and the like, and a preferable etching solution is BOE, so that the region corresponding to the second electrode 120 (p electrode) on the second surface of the epitaxial wafer is exposed.
S8, depositing the second electrode 120 (i.e. the first reflecting layer), preferably performing electron beam evaporation, magnetron sputtering and the like, wherein the preferred metal is one or more metal combinations such as Cr, al, ti, ni, au, pt, V, rh, ITO, stripping photoresist, forming the second electrode 120, and then annealing to form good ohmic contact. The position and structure of the second electrode 120 can also be shown with reference to fig. 1 and 2.
And S9, photoetching again, and then depositing a second electrode connecting layer 121, wherein the preferred deposition process is electron beam evaporation, magnetron sputtering and the like, the preferred metal is Cr, al, ti, ni, au, pt, V, or one or more metal combinations, stripping photoresist and forming the second electrode connecting layer 121. The location and structure of the second electrode connection layer 121 may also be as shown in fig. 1 and 2.
And S10, photoetching again, and then etching the second surface of the epitaxial wafer by adopting a dry etching process or a wet etching process to form a second groove 118, wherein the preferred etching process is ICP, and the etching position penetrates through the second conductive semiconductor layer 114, the active layer 113, the first conductive semiconductor layer 112 and the buffer layer 111 until the epitaxial substrate 110 is stopped. The location and structure of the second trench may also be as shown in fig. 1 and 2.
And S11, after etching, filling corrosion-resistant materials (preferably Cr, pt, au and the like) at the exposed substrate position (namely the bottom surface of the second groove) to form a protective layer 130, wherein the filling height is not higher than that of the buffer layer, and the thickness is preferably 100-500 nm, so as to prevent damage to the second groove in the epitaxial substrate removing process. The location and structure of the protective layer can also be shown with reference to fig. 1 and 2.
S12, depositing an insulating material on the second surface of the epitaxial wafer to form a second insulating layer 131, wherein the preferred deposition process is PECVD, ICPCVD, LPCVD, ALD, and the preferred deposition material is SiO 2 、SiN、Al 2 O 3 Combinations of one or more of the following; preferably 600-1000nm. The second insulating layer 131 continuously covers the walls of the second trench and the remaining regions of the second surface of the epitaxial wafer. The location and structure of the second insulating layer may also be as shown in fig. 1 and 2.
And S13, photoetching again, and carrying out windowing on the second insulating layer 131, wherein the preferable windowing process is RIE etching, BOE etching and the like, the windowing region corresponds to the first electrode and the like, the second reflecting layer is deposited after windowing, and the preferable deposition process is electron beam evaporation and magnetron sputtering, and the preferable material of the second reflecting layer is Al. The position and structure of the second reflective layer can also be shown with reference to fig. 1 and 2.
And S14, filling a stress matching material 133 in the second groove, wherein the preferable material is SOG, PSG, various resin materials and the like so as to further match the stress of the epitaxial layer and reduce the problems of epitaxial warping and the like.
S15, depositing a bonding barrier layer and a bonding layer 140 on the second surface of the epitaxial wafer, and bonding the epitaxial wafer with a bonding substrate 150 by a bonding process, wherein the bonding substrate is preferably made of other conductive materials such as silicon, metal and the like, and the obtained device structure can also be shown in fig. 1-2.
S16, removing the epitaxial substrate after bonding, wherein the removing process can be thinning, laser stripping, dry etching or wet etching and the like which are known in the art. Preferably, a majority (e.g., 90%) of the epitaxial substrate may be removed by mechanical polishing, and the remaining portion may be removed by dry etching (e.g., RIE) or wet etching to expose a portion of the buffer layer.
And S17, defining the surface of one side of the buffer layer away from the first conductive semiconductor layer as a first surface of the epitaxial wafer. Alternatively, preferably, the buffer layer may be partially removed by a dry etching process or the like, and the surface of the remaining buffer layer may be defined as the first surface of the epitaxial wafer. The corresponding device structure is shown in fig. 3.
And S18, performing surface roughening treatment on the first conductive semiconductor layer, wherein the preferred process can be KOH corrosion, ICP etching and the like, so as to further improve light emission and increase the light extraction efficiency of the device.
And S19, performing photoetching again to form a window corresponding to the first bonding pad on the first surface of the epitaxial wafer, wherein the preferential windowing process is phosphoric acid corrosion, ICP etching and the like, and exposing the first insulating layer after the treatment.
S20, depositing a passivation layer on the first surface of the epitaxial wafer, wherein the preferable deposition process is PECVD (plasma enhanced chemical vapor deposition) and ICPCVD, LPCVD, ALD, etc., the preferred deposition material is SiO 2 、SiN、Al 2 O 3 And the like.
And S21, photoetching again, and forming a window (also can be defined as a third groove) on the passivation layer, wherein the preferred windowing process is RIE etching, BOE etching and the like so as to expose the second electrode connecting layer.
S22, depositing a first bonding pad 160 in a window on the passivation layer, wherein a preferred deposition process is electron beam evaporation, magnetron sputtering, and a preferred material is Ti, pt, au, cr, ni, or one or more metal combinations, stripping photoresist, and forming the first bonding pad 160 combined with the second electrode connection layer for wire bonding. The resulting device structure is shown in fig. 4-5.
A top view of a vertical structure deep ultraviolet LED device finally obtained in this embodiment is shown in fig. 6.
Example 2: the manufacturing method of the deep ultraviolet LED device with the vertical structure and the formed device structure are basically the same as those of embodiment 1, and the difference is that:
in step S10, the depth of the second trench formed by etching penetrates the second conductive semiconductor layer, the active layer, and the first conductive semiconductor layer until the buffer layer is terminated.
In step S11, a protective layer is formed by filling the exposed buffer layer (i.e., the bottom surface of the second trench) with a corrosion-resistant material, wherein the filling height is not higher than the first conductive semiconductor layer, so as to prevent the second trench from being damaged during the epitaxial substrate removal process.
In step S17, the buffer layer is completely removed, and one side surface of the exposed first conductive semiconductor layer is defined as a first surface of the epitaxial wafer.
Comparative example 1: the manufacturing method of the vertical structure deep ultraviolet LED device and the formed device structure are basically the same as those of the embodiment 1, and the difference is that: the operation of forming the second trench on the second surface of the epitaxial wafer is omitted.
Comparative example 2: the manufacturing method of the vertical structure deep ultraviolet LED device and the formed device structure are basically the same as those of the embodiment 1, and the difference is that: the operation of forming the protective layer at the bottom of the second trench in step S11 is omitted.
Comparative example 3: the manufacturing method of the vertical structure deep ultraviolet LED device and the formed device structure are basically the same as those of the embodiment 1, and the difference is that: the operation of filling the stress matching material in the second trench in step S14 is omitted.
Comparing example 1 with comparative example 1, comparative example 2 and comparative example 3, it is evident that the yield of the vertical structure deep ultraviolet LED device manufactured by the process of example 1 is greatly improved, and the light extraction efficiency and reliability of the product are also remarkably improved. Whereas the yield of the product of comparative example 1 was very low (less than 30%), and the light extraction efficiency of the product was low. In addition, in the products of comparative examples 2 and 3, the epitaxial wafer has a certain probability of falling off, cracking and other problems during the process of removing the epitaxial substrate, and the final device has a certain probability of sidewall leakage and other phenomena, while example 1 completely overcomes the defects of comparative examples 1-3.
It should be understood that the technical solution of the present invention is not limited to the above specific embodiments, and all technical modifications made according to the technical solution of the present invention without departing from the spirit of the present invention and the scope of the claims are within the scope of the present invention.
Claims (10)
1. The deep ultraviolet LED structure with the vertical structure comprises an epitaxial layer, wherein the epitaxial layer comprises a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer which are sequentially stacked, the first conductive semiconductor layer is electrically connected with a first electrode, and the second conductive semiconductor layer is electrically connected with a second electrode;
the method is characterized in that: the epitaxial layer is provided with a first surface and a second surface which are opposite, the second surface is far away from the first conductive semiconductor layer, at least one second groove is further formed in the second surface, the bottom surface of the second groove is distributed in the epitaxial layer or on the first surface, at least the bottom surface of the second groove is covered with a protective layer, and meanwhile, the second groove is filled with a stress matching material.
2. The vertical structure deep ultraviolet LED structure of claim 1, wherein: and a second insulating layer is further formed on the inner wall of the second groove, the second insulating layer continuously covers the inner wall of the second groove, the protective layer and the second conductive semiconductor layer, and the second insulating layer is connected with the bonding substrate through the bonding layer.
3. The vertical structure deep ultraviolet LED structure of claim 2, wherein: the second insulating layer is further continuously covered with a second reflecting layer, and the stress matching material is distributed between the second reflecting layer and the bonding layer;
and/or the groove wall of the second groove is obliquely arranged and forms an included angle of 30-60 degrees with the first surface or the second surface of the epitaxial layer;
and/or the second electrode is distributed between the second insulating layer and the second conductive semiconductor layer, and the second electrode is electrically combined with the second conductive semiconductor layer;
and/or the second electrode is further used for forming a first reflecting layer;
and/or the second conductive semiconductor layer is further covered with a first insulating layer;
and/or, at least one first groove is further formed on the second surface of the epitaxial layer, the bottom surface of the first groove is distributed inside the first conductive semiconductor layer or on the surface of the first conductive semiconductor layer, and the first electrode is at least partially arranged in the first groove and is electrically contacted with the first conductive semiconductor layer;
and/or, the epitaxial layer further comprises a buffer layer, the first conductive semiconductor layer is formed on one side surface of the buffer layer, and the other side surface of the buffer layer is the first surface.
4. The vertical structure deep ultraviolet LED structure of claim 3, wherein: the inner wall of the first groove is also covered with a first insulating layer, and the first insulating layer continuously extends to the surface of the second conductive semiconductor layer.
And/or the first electrode is arranged in the first groove and is in contact with the second reflecting layer;
and/or, the second electrode is further in electrical contact with a second electrode connection layer, and the second electrode connection layer is arranged between the second electrode and the second insulating layer.
5. The vertical structure deep ultraviolet LED structure of claim 4, wherein:
the first surface of the epitaxial layer is provided with a surface roughening structure;
and/or a third groove is further formed in the first surface of the epitaxial layer, the bottom surface of the third groove reaches the surface of the second electrode connecting layer, a first bonding pad is arranged in the third groove, and the first bonding pad is in electrical contact with the second electrode connecting layer;
and/or a bonding barrier layer is also distributed between the bonding layer and the second insulating layer.
6. The vertical structure deep ultraviolet LED structure of claim 1, wherein: the first conductive semiconductor layer is formed on an epitaxial substrate, and a buffer layer is distributed between the first conductive semiconductor layer and the epitaxial substrate.
7. The manufacturing method of the deep ultraviolet LED structure with the vertical structure comprises the steps of growing an epitaxial layer on an epitaxial substrate and manufacturing a first electrode and a second electrode matched with the epitaxial layer, wherein the epitaxial layer comprises a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer which are sequentially stacked, the first conductive semiconductor layer is electrically connected with the first electrode, and the second conductive semiconductor layer is electrically connected with the second electrode;
the manufacturing method is characterized by further comprising the following steps:
at least one second groove is formed on the second surface of the epitaxial layer, the bottom surface of the second groove is distributed in the epitaxial layer or on the first surface of the epitaxial layer, the second surface is far away from the first conductive semiconductor layer, and the first surface is opposite to the second surface; and
and covering a protective layer on at least the bottom surface of the second groove, and filling a stress matching material in the second groove.
8. The manufacturing method according to claim 7, characterized by comprising the following steps:
covering a protective layer on the bottom surface of the second groove;
forming a second insulating layer on the inner wall of the second trench, and continuously covering the second trench inner wall, the protective layer and the second conductive semiconductor layer by the second insulating layer;
forming a second reflective layer on the second insulating layer;
filling a stress matching material in the second groove;
bonding the second reflecting layer with a bonding substrate through a bonding layer;
the epitaxial substrate is removed and a buffer layer distributed between the epitaxial substrate and the first conductive semiconductor layer is at least partially removed.
9. The manufacturing method according to claim 8, characterized by comprising the following steps:
at least one first groove is formed on the second surface of the epitaxial layer, and the bottom surface of the first groove is distributed in the first conductive semiconductor layer or on the surface of the first conductive semiconductor layer;
disposing a first electrode on the first conductive semiconductor layer, and disposing the first electrode at least partially within the first trench and in electrical contact with the first conductive semiconductor layer;
forming a continuous first insulating layer on the inner wall of the first groove, and enabling the first insulating layer to extend to the surface of the second conductive semiconductor layer;
forming a window on the first insulating layer to expose the area corresponding to the second electrode on the surface of the second conductive semiconductor layer, and then manufacturing and forming the second electrode in the window;
and forming the second groove on the second surface of the epitaxial layer.
10. The method of manufacturing of claim 9, further comprising:
a second electrode connecting layer is arranged on the second electrode, the second electrode connecting layer is electrically contacted with the second electrode, and then a second insulating layer and a second reflecting layer are covered on the second electrode connecting layer;
and/or coarsening the first surface of the epitaxial layer;
and/or providing a bonding barrier layer between the bonding layer and the second reflective layer;
and/or a third groove is formed on the first surface of the epitaxial layer, the bottom surface of the third groove reaches the surface of the second electrode connecting layer, a first bonding pad is formed in the third groove, and the first bonding pad is electrically contacted with the second electrode connecting layer;
and/or the groove wall of the second groove is obliquely arranged and forms an included angle of 30-60 degrees with the first surface or the second surface of the epitaxial layer.
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| CN116469907A (en) * | 2023-06-20 | 2023-07-21 | 季华实验室 | Light-emitting panel and manufacturing method thereof |
| CN116469907B (en) * | 2023-06-20 | 2023-08-29 | 季华实验室 | Light-emitting panel and manufacturing method thereof |
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