CN116093085A - MOM capacitor structure, preparation method thereof and memory - Google Patents
MOM capacitor structure, preparation method thereof and memory Download PDFInfo
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- CN116093085A CN116093085A CN202310182628.7A CN202310182628A CN116093085A CN 116093085 A CN116093085 A CN 116093085A CN 202310182628 A CN202310182628 A CN 202310182628A CN 116093085 A CN116093085 A CN 116093085A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
Abstract
The invention provides a MOM capacitor structure, a preparation method thereof and a memory. The MOM capacitor structure includes: the first electrode layer comprises two interdigital structure electrode plates which are oppositely arranged along a first direction; the second electrode layer can generate parasitic capacitance with the first electrode layer, and the second electrode layer comprises two electrode plates with an interdigital structure, wherein the electrode plates are oppositely arranged along a second direction, and the second direction is perpendicular to the first direction. The first electrode layer and the second electrode layer are arranged to be mutually perpendicular, so that the influence of capacitance caused by overlapping degree drift of metal wires in the metal layer process is reduced, the capacitance is more stable, and the process yield is improved.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a MOM capacitor structure, a preparation method thereof and a memory.
Background
With the continuous progress of semiconductor integrated circuit manufacturing technology, the performance of semiconductor devices is continuously improved. The capacitor structure is an important component of an integrated circuit, such as a Metal-oxide-Metal (MOM) capacitor, which is a common capacitor structure in integrated capacitors. The MOM capacitor structure is parasitic capacitance generated by taking the rear metal layer as a polar plate, and the source of the capacitance mainly comprises a space between the horizontal identical layers and a space between the vertical adjacent two layers. MOM capacitors are often used by chip designers because of their high withstand voltage, low cost (no additional masks and processes are required), small footprint (stackable), etc.
Referring to fig. 1-2, fig. 1 is a schematic structural diagram of a MOM capacitor structure in the prior art, and fig. 2 is a cross-sectional view along AA' direction in fig. 1. As shown in fig. 1-2, the MOM capacitor includes a two-layer finger structure of a lower electrode layer 11 and an upper electrode layer 12. Because the upper electrode layer and the lower electrode layer are overlapped, the capacitance value is greatly influenced by the coverage (Overlay) overlapping degree in the process, so that the capacitance value of the MOM capacitor is unstable, and the performance of the device is influenced.
Therefore, reducing the influence of the process on the capacitance value and improving the stability of the capacitance value is a problem to be solved at present.
Disclosure of Invention
The invention aims to solve the technical problems of reducing the influence of a process on a capacitance value and improving the stability of the capacitance value, and provides a MOM capacitance structure, a preparation method thereof and a memory.
In order to solve the above problems, the present invention provides a MOM capacitor structure, comprising: the first electrode layer comprises two interdigital structure electrode plates which are oppositely arranged along a first direction; the second electrode layer can generate parasitic capacitance with the first electrode layer, and the second electrode layer comprises two electrode plates with an interdigital structure, wherein the electrode plates are oppositely arranged along a second direction, and the second direction is perpendicular to the first direction.
In some embodiments, the first electrode layer is a plurality of layers, the second electrode layer is a plurality of layers, and the first electrode layer and the second electrode layer are alternately arranged.
In some embodiments, the potentials of the two interdigital electrode plates in the first electrode layer are different; and the electrode plates with two interdigital structures in the second electrode layer have different potentials.
In some embodiments, each of the finger structure electrode plates includes a plurality of finger strips and a summary strip connecting the plurality of finger strips.
In some embodiments, the MOM capacitor structure further comprises: a first insulating layer, the first electrode layer being located in the first insulating layer; and the second electrode layer is positioned in the second insulating layer, and is insulated from the first electrode layer through the second insulating layer or the first insulating layer.
In some embodiments, the materials of the first electrode layer and the second electrode layer are metals.
In order to solve the above problems, the present invention provides a memory including the MOM capacitor structure of the present invention.
In order to solve the above problems, the present invention provides a method for manufacturing a MOM capacitor structure, comprising the following steps: providing a substrate; forming a first electrode layer on the substrate, wherein the first electrode layer comprises two interdigital electrode plates which are oppositely arranged along a first direction; and forming a second electrode layer on the substrate, wherein the second electrode layer can generate parasitic capacitance with the first electrode layer, and the second electrode layer comprises two interdigital electrode plates oppositely arranged along a second direction, and the second direction is perpendicular to the first direction.
In some embodiments, the first electrode layer is a plurality of layers, the second electrode layer is a plurality of layers, and the first electrode layer and the second electrode layer are alternately arranged.
In some embodiments, the method further comprises: forming a first insulating layer on the substrate, wherein the first electrode layer is formed in the first insulating layer; and forming a second insulating layer on the first insulating layer, wherein the second electrode layer is formed in the second insulating layer, and the second electrode layer is insulated from the first electrode layer through the second insulating layer or the first insulating layer.
According to the technical scheme, the first electrode layer and the second electrode layer are arranged to be of mutually perpendicular structures, so that the influence of capacitance caused by overlapping degree drift of metal wires in a metal layer process is reduced, the capacitance is more stable, and the process yield is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but should be considered part of the specification where appropriate.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that are required to be used in the description of the embodiments will be briefly described. It is apparent that the drawings in the following description are only some specific embodiments of the present invention, and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic structural diagram of a MOM capacitor structure in the prior art.
Fig. 2 shows a cross-section along the AA' direction in fig. 1.
Fig. 3 is a schematic structural diagram of a MOM capacitor structure according to an embodiment of the invention.
Fig. 4 is a cross-sectional view taken along the direction BB' in fig. 3.
Fig. 5A to 5B are graphs showing the comparison of capacitance values between the MOM capacitor structure according to the present invention and the conventional MOM capacitor structure.
Fig. 5C is a chart showing the standard deviation of capacitance values of the MOM capacitor structure according to the present invention and the conventional MOM capacitor structure.
Fig. 6 is a schematic diagram of a memory according to an embodiment of the invention.
Fig. 7 is a flowchart illustrating steps of a method for fabricating a MOM capacitor structure according to an embodiment of the present invention.
Fig. 8A to 8C are process flow diagrams illustrating a method for manufacturing a MOM capacitor structure according to an embodiment of the invention.
Detailed Description
The technical solutions in the specific embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. It will be apparent that the embodiments described are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art without the exercise of inventive faculty, are intended to be within the scope of the invention, based on the embodiments herein.
Referring to fig. 3 to 4, fig. 3 is a schematic structural diagram of a MOM capacitor structure according to an embodiment of the invention, and fig. 4 is a cross-sectional view along the BB' direction in fig. 3. The MOM capacitor structure includes a first electrode layer 31 and a second electrode layer 32. The first electrode layer 31 includes two electrode plates 311 and 312 of an interdigital structure disposed opposite to each other along a first direction D1. The second electrode layer 32 can generate parasitic capacitance with the first electrode layer 31, and the second electrode layer 32 includes two electrode plates 321 and 322 with an interdigital structure disposed opposite to each other along a second direction D2, where the second direction D2 is perpendicular to the first direction D1.
According to the technical scheme, the first electrode layer 31 and the second electrode layer 32 are arranged to be of mutually perpendicular structures, so that the influence of capacitance caused by overlapping degree drift of metal wires in the metal layer process is reduced, the capacitance is more stable, and the process yield is improved.
In some embodiments, the first electrode layer 31 is a multilayer, the second electrode layer 32 is a multilayer, and the first electrode layer 31 and the second electrode layer 32 are alternately arranged. The first electrode layers 31 and the second electrode layers 32 are alternately arranged, and a larger capacitance value is realized by stacking multiple layers while the capacitance value influence caused by overlapping degree drift of metal wires in the metal layer process is reduced to make the capacitance value more stable.
In some embodiments, the two inter-digitated electrode plates 311, 312 in the first electrode layer 31 have different potentials; the two inter-digitated electrode plates 321, 322 in the second electrode layer 32 have different potentials. As a specific embodiment, one of the electrode plates 311 of the first electrode layer 31 is at a high potential, and the other electrode plate 312 is at a low potential. Similarly, one of the electrode plates 321 of the second electrode layer 32 is at a high potential, and the other electrode plate 322 is at a low potential.
In some embodiments, the two electrode plates 311, 312 of the first electrode layer 31 have the same structure; the two interdigital electrode plates 321 and 322 in the second electrode layer 32 have the same structure.
In some embodiments, each of the finger structure electrode plates includes a plurality of finger strips and a summary strip connecting the plurality of finger strips. In the first electrode layer 31, the electrode plate 311 of an interdigital structure includes a plurality of finger strips 3111 and a summary strip 3112 for connecting the plurality of finger strips 3111. Finger bars 3111 and 3121 are arranged in an interdigitated configuration, and for plates formed of the same layer of metal, the same layer of adjacent finger bars 3111 and 3121 form a partial capacitance structure. Also, another inter-digitated structure electrode plate 312 includes a plurality of finger strips 3121 and a summary strip 3122 for connecting the plurality of finger strips 3121. In the second electrode layer, one finger electrode plate 321 includes a plurality of finger strips 3211 and a summary strip 3212 for connecting the plurality of finger strips 3211, and similarly, the other finger electrode plate 322 includes a plurality of finger strips 3221 and a summary strip 3222 for connecting the plurality of finger strips 3221.
For plates formed by adjacent layers of metals, adjacent layers of crossed finger 3111 and finger 3211 form a partial capacitance structure, and similarly, the partial capacitance structure can be formed between adjacent layers of crossed finger 3111 and finger 3221, between finger 3121 and finger 3211, and between finger 3121 and finger 3221, and the total capacitance is equal to the sum of the capacitances of the partial capacitances.
In some embodiments, the MOM capacitor structure further comprises: a first insulating layer 33, the first electrode layer 31 being located in the first insulating layer 33; a second insulating layer 34, the second electrode layer 32 is located in the second insulating layer 34, and the second electrode layer 32 is insulated from the first electrode layer 31 by the second insulating layer 34, as shown in fig. 4. In other embodiments, the second electrode layer 32 may also be insulated from the first electrode layer 31 by the first insulating layer 33.
In some embodiments, the materials of the first electrode layer 31 and the second electrode layer 32 are metals. That is, the overall capacitance formed between the upper and lower metal wires and the same metal layer can be utilized, so that the conventional interconnection manufacturing process can be used for realizing the interconnection, and the wide application is facilitated.
Referring to fig. 5A to 5C, fig. 5A to 5B are graphs showing comparison of capacitance values of the MOM capacitor structure and the conventional MOM capacitor structure according to the present invention, and fig. 5C is a graph showing comparison of standard deviation of capacitance values of the MOM capacitor structure and the conventional MOM capacitor structure according to the present invention.
Fig. 5A is a graph comparing capacitance values when a gap (Space) specification between adjacent fingers of the same electrode layer is 0.28 μm, wherein an abscissa is a sample size of the capacitance structure, an ordinate is a capacitance value of the capacitance structure, a reference numeral 51 is a capacitance value of the existing MOM capacitance structure, and a reference numeral 52 is a capacitance value of the MOM capacitance structure. Fig. 5B is a graph comparing capacitance values when a gap (Space) specification between adjacent fingers of an electrode plate of the same finger structure is 0.56 μm, the abscissa is a sample size of the capacitance structure, the ordinate is a capacitance value of the capacitance structure, reference numeral 53 is a capacitance value of the existing MOM capacitance structure, and reference numeral 54 is a capacitance value of the MOM capacitance structure according to the present invention. Fig. 5C is a graph comparing standard deviations of capacitance values of the MOM capacitor structure and the existing MOM capacitor structure according to the present invention, wherein an abscissa is a type of the capacitor structure, an ordinate is a standard deviation of capacitance values of the capacitor structure, reference numeral 55 is a standard deviation of capacitance values when a gap specification between adjacent fingers of the electrode plate of the same finger structure is 0.28 micron, reference numeral 56 is a standard deviation of capacitance values when a gap specification between adjacent fingers of the electrode plate of the same finger structure is 0.28 micron, reference numeral 57 is a standard deviation of capacitance values when a gap specification between adjacent fingers of the electrode plate of the same finger structure is 0.56 micron, and reference numeral 58 is a standard deviation of capacitance values when a gap specification between adjacent fingers of the electrode plate of the same finger structure is 0.56 micron. As can be seen from fig. 5A to fig. 5C, compared with the existing MOM capacitor structure, the capacitance value of the MOM capacitor structure is only 0.71 to 3.5 percent lower, but the phase difference is very small, but the capacitance value of the MOM capacitor structure is very stable, and compared with the standard deviation of the existing MOM capacitor structure, the standard deviation of the MOM capacitor structure is reduced by 3 to 4 times, and the stability of the capacitance value of the MOM capacitor structure is obviously improved.
Based on the same inventive concept, the invention also provides a memory.
Please refer to fig. 6, which is a diagram illustrating a memory according to an embodiment of the present invention. The memory 100 according to this embodiment includes: MOM capacitor structure 101; the MOM capacitor structure 101 adopts the chip detection circuit layout structure shown in fig. 3 to 4 of the present invention, and is described in detail in the foregoing, and will not be repeated here.
Based on the same inventive concept, the invention also provides a preparation method of the MOM capacitor structure.
Referring to fig. 7 to fig. 8C, fig. 7 is a flowchart illustrating steps of a method for manufacturing a MOM capacitor structure according to an embodiment of the present invention, and fig. 8A to fig. 8C are process flowcharts illustrating a method for manufacturing a MOM capacitor structure according to an embodiment of the present invention.
As shown in fig. 7, the preparation method of the MOM capacitor structure of the present invention includes the following steps: step S71, providing a substrate; step S72, forming a first electrode layer on the substrate, wherein the first electrode layer comprises two electrode plates with an interdigital structure, which are oppositely arranged along a first direction; and step S73, forming a second electrode layer on the substrate, wherein the second electrode layer can generate parasitic capacitance with the first electrode layer, and the second electrode layer comprises two electrode plates with interdigital structures which are oppositely arranged along a second direction, and the second direction is perpendicular to the first direction.
Referring to fig. 8A and step S71, a substrate 80 is provided. In one embodiment, the base 80 is a silicon substrate.
Referring to fig. 8B and step S72, a first electrode layer 31 is formed on the substrate 80, and the first electrode layer 31 includes two interdigital electrode plates disposed opposite to each other along a first direction D1. As an embodiment, the step of forming a first electrode layer 31 on the substrate 80 further includes the following steps: a first insulating layer 33 is formed on the substrate 80, and the first electrode layer 31 is formed in the first insulating layer 33.
Referring to fig. 8C and step S73, a second electrode layer 32 is formed on the substrate 80, the second electrode layer 32 is capable of generating parasitic capacitance with the first electrode layer 31, and the second electrode layer 32 includes two finger-structured electrode plates disposed opposite to each other along a second direction D2, wherein the second direction D2 is perpendicular to the first direction D1. As one embodiment, the step of forming a second electrode layer 32 on the substrate 80 further includes the steps of: a second insulating layer 34 is formed on the first insulating layer 33, the second electrode layer 32 is formed in the second insulating layer 34, and the second electrode layer 32 is insulated from the first electrode layer 31 by the second insulating layer 34. In other embodiments, the second electrode layer 32 may also be insulated from the first electrode layer 31 by the first insulating layer 33.
In some embodiments, the first electrode layer 31 is a multilayer, the second electrode layer 32 is a multilayer, and the first electrode layer 31 and the second electrode layer 32 are alternately arranged. The first electrode layers 31 and the second electrode layers 32 are alternately arranged, and a larger capacitance value is realized by stacking multiple layers while the capacitance value influence caused by overlapping degree drift of metal wires in the metal layer process is reduced to make the capacitance value more stable.
In some embodiments, the materials of the first electrode layer 31 and the second electrode layer 32 are metals. That is, the overall capacitance formed between the upper and lower metal wires and the same metal layer can be utilized, so that the conventional interconnection manufacturing process can be used for realizing the interconnection, and the wide application is facilitated.
According to the technical scheme, the first electrode layer 31 and the second electrode layer 32 are arranged to be of mutually perpendicular structures, so that the influence of capacitance caused by overlapping degree drift of metal wires in the metal layer process is reduced, the capacitance is more stable, and the process yield is improved.
It should be noted that references in the specification to "one embodiment," "an example embodiment," "some embodiments," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the relevant art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
Generally, the terms may be understood, at least in part, from the usage in the context. For example, the term "one or more" as used herein, depending at least in part on the context, may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a feature, structure, or combination of features in a plural sense. Similarly, terms such as "a," "an," or "the" may also be construed to express singular usage or plural usage depending at least in part on the context. In addition, the term "based on" may be understood as not necessarily intended to express a set of exclusive factors, but may instead, depending at least in part on the context, allow for other factors that are not necessarily explicitly described. It should also be noted in this specification that "connected/coupled" means not only that one component is directly coupled to another component, but also that one component is indirectly coupled to another component through intervening components.
It should be noted that the terms "comprising" and "having" and their variants are referred to in the document of the present invention and are intended to cover non-exclusive inclusion. The terms "first," "second," and the like are used to distinguish similar objects and not necessarily to describe a particular order or sequence unless otherwise indicated by context, it should be understood that the data so used may be interchanged where appropriate. In addition, the embodiments of the present invention and features of the embodiments may be combined with each other without conflict. In addition, in the above description, descriptions of well-known components and techniques are omitted so as to not unnecessarily obscure the present invention. In the foregoing description, each embodiment is mainly described for the differences from the other embodiments, and the same/similar parts between the embodiments are referred to each other.
The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.
Claims (10)
1. A MOM capacitor structure, comprising:
the first electrode layer comprises two interdigital structure electrode plates which are oppositely arranged along a first direction;
the second electrode layer can generate parasitic capacitance with the first electrode layer, and the second electrode layer comprises two electrode plates with an interdigital structure, wherein the electrode plates are oppositely arranged along a second direction, and the second direction is perpendicular to the first direction.
2. The MOM capacitor structure of claim 1, wherein the first electrode layer is a plurality of layers, the second electrode layer is a plurality of layers, and the first electrode layer and the second electrode layer are alternately arranged.
3. The MOM capacitor structure of claim 1, wherein,
the electric potentials of the two electrode plates with the interdigital structures in the first electrode layer are different;
and the electrode plates with two interdigital structures in the second electrode layer have different potentials.
4. The MOM capacitor structure of claim 1, wherein each of the finger structure electrode plates comprises a plurality of finger strips and a summary strip connecting the plurality of finger strips.
5. The MOM capacitor structure of claim 1, further comprising:
a first insulating layer, the first electrode layer being located in the first insulating layer;
and the second electrode layer is positioned in the second insulating layer, and is insulated from the first electrode layer through the second insulating layer or the first insulating layer.
6. The capacitor structure of claim 1, wherein the material of the first electrode layer and the second electrode layer is metal.
7. A memory comprising the MOM capacitor structure of any one of claims 1-6.
8. The preparation method of the MOM capacitor structure is characterized by comprising the following steps of:
providing a substrate;
forming a first electrode layer on the substrate, wherein the first electrode layer comprises two interdigital electrode plates which are oppositely arranged along a first direction; and
and forming a second electrode layer on the substrate, wherein the second electrode layer can generate parasitic capacitance with the first electrode layer, and the second electrode layer comprises two interdigital structure electrode plates which are oppositely arranged along a second direction, and the second direction is perpendicular to the first direction.
9. The method of claim 7, wherein the first electrode layer is a plurality of layers, the second electrode layer is a plurality of layers, and the first electrode layer and the second electrode layer are alternately disposed.
10. The method of claim 7, wherein the method further comprises:
forming a first insulating layer on the substrate, wherein the first electrode layer is formed in the first insulating layer; and
and forming a second insulating layer on the first insulating layer, wherein the second electrode layer is formed in the second insulating layer, and the second electrode layer is insulated from the first electrode layer through the second insulating layer or the first insulating layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310182628.7A CN116093085A (en) | 2023-02-28 | 2023-02-28 | MOM capacitor structure, preparation method thereof and memory |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310182628.7A CN116093085A (en) | 2023-02-28 | 2023-02-28 | MOM capacitor structure, preparation method thereof and memory |
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| CN116093085A true CN116093085A (en) | 2023-05-09 |
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| CN202310182628.7A Pending CN116093085A (en) | 2023-02-28 | 2023-02-28 | MOM capacitor structure, preparation method thereof and memory |
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