CN116093079B - Semiconductor device and electronic device - Google Patents
Semiconductor device and electronic device Download PDFInfo
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- CN116093079B CN116093079B CN202310195352.6A CN202310195352A CN116093079B CN 116093079 B CN116093079 B CN 116093079B CN 202310195352 A CN202310195352 A CN 202310195352A CN 116093079 B CN116093079 B CN 116093079B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 147
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000010410 layer Substances 0.000 claims description 63
- 238000004891 communication Methods 0.000 claims description 28
- 239000011229 interlayer Substances 0.000 claims description 17
- 230000005669 field effect Effects 0.000 claims description 5
- 238000000034 method Methods 0.000 description 27
- 230000008569 process Effects 0.000 description 24
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000011084 recovery Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000003993 interaction Effects 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/2901—Shape
- H01L2224/29016—Shape in side view
- H01L2224/29018—Shape in side view comprising protrusions or indentations
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The application provides a semiconductor device and an electronic device, and relates to the field of semiconductors. The semiconductor device has a first mounting surface and a second mounting surface opposite to the first mounting surface; the semiconductor device further includes a plurality of pads, a portion of the plurality of pads being disposed on the first mounting surface, another portion of the plurality of pads being disposed on the second mounting surface; the part of the plurality of bonding pads arranged on the first mounting surface is used for connecting the substrate, the part of the plurality of bonding pads arranged on the second mounting surface is provided with a contact pattern, and the contact pattern can be used for identifying specification information of the semiconductor device. The application solves the problems of high difficulty in identifying different types of semiconductor devices and easy occurrence of connection errors of the semiconductor devices.
Description
Technical Field
The present application relates to the field of semiconductors, and more particularly, to a semiconductor device and an electronic apparatus.
Background
Semiconductor devices are a common type of electronic device that can utilize the specific electrical characteristics of semiconductor materials to perform specific functions and are widely used in integrated circuits. In the fabrication process of integrated circuits, it is often necessary to use contact holes of semiconductor devices to achieve connection and signal interaction between a plurality of semiconductor devices. However, when the number of semiconductor devices in an integrated circuit is large, difficulty in identifying different types of semiconductor devices is large, and a problem of wrong selection or connection of semiconductor devices is liable to occur.
Disclosure of Invention
The embodiment of the application provides a semiconductor device and an electronic device, which are used for solving the problems that the identification difficulty of different types of semiconductor devices is high, and the selection or connection of the semiconductor devices is easy to occur.
The semiconductor device provided by the embodiment of the application is provided with a first mounting surface and a second mounting surface opposite to the first mounting surface;
The semiconductor device further includes a plurality of pads, a portion of which is disposed on the first mounting surface side of the semiconductor device, and another portion of which is disposed on the second mounting surface side of the semiconductor device;
The portion of the plurality of bonding pads arranged on the first mounting surface side of the semiconductor device is used for connecting a substrate, and the portion of the plurality of bonding pads arranged on the second mounting surface side of the semiconductor device is provided with a contact pattern which can be used for identifying specification information of the semiconductor device.
By adopting the technical scheme, the contact patterns are arranged on the partial bonding pads arranged on the second mounting surface, so that the semiconductor device can be mounted on the substrate through the first mounting surface of the semiconductor device in the process of mounting and connecting the semiconductor device, and the specification information of the semiconductor device can be identified through the contact patterns arranged on the second mounting surface, so that the identification difficulty of different types of semiconductor devices is reduced, and the possibility of connecting errors of the semiconductor device is reduced.
In some possible embodiments, the semiconductor device is provided as an insulated gate bipolar transistor;
The plurality of pads are disposed on the second mounting surface side, the plurality of pads include a gate pad and an emitter pad, and at least one of the gate pad and the emitter pad is provided with the contact pattern.
In some possible embodiments, the semiconductor device is provided as an insulated gate field effect transistor; the portion of the plurality of pads disposed on the second mounting surface side of the semiconductor device includes a gate pad and a source pad, at least one of the gate pad and the source pad being provided with the contact pattern;
or the semiconductor device is configured as a fast recovery diode; the portion of the plurality of pads disposed on the second mounting surface side of the semiconductor device includes an anode pad provided with the contact pattern.
In some possible embodiments, a drift layer is further included;
A base layer provided on the upper surface side of the drift layer;
An emitter layer and a contact layer provided on the upper surface side of the base layer;
and a gate electrode extending to the drift layer through the emitter electrode and the base layer.
In some of the possible embodiments of the present invention,
The semiconductor device further comprises a gate pad, a gate lead-out part and a gate connecting part, wherein the gates are connected to the gate lead-out part through the gate connecting part, the gate pad is formed on the upper part of the gate lead-out part through an interlayer insulating film, and the gate lead-out part is in contact with and electrically connected with the gate pad through a contact hole which is an opening part of the interlayer insulating film;
The contact holes between the grid lead-out part and the grid bonding pad are arranged in a plurality of rows and a plurality of columns, and the contact hole communication part is used for connecting two adjacent contact holes in the same row or the contact hole communication part is used for connecting two adjacent contact holes in the same column.
In some possible embodiments, the gate pad forms a recess at a corresponding position of the contact hole, and the gate pad forms a recess communication at a corresponding position of the contact hole communication;
Correspondingly, the plurality of concave parts of the gate pad are arranged in a plurality of rows and a plurality of columns, the concave communicating parts of the gate pad are used for connecting two adjacent concave parts in the same row, or the concave communicating parts of the gate pad are used for connecting two adjacent concave parts in the same column; the plurality of recess portions and the recess communication portion together form the contact pattern.
In some of the possible embodiments of the present invention,
The semiconductor device further includes an emitter pad formed on the upper portion of the gate electrode with an interlayer insulating film interposed therebetween, the emitter pad being electrically connected to the emitter pad through a contact hole which is an opening of the interlayer insulating film, the emitter layer and the contact layer being in contact with each other;
The contact holes between the emitter layer and the contact layer and the emitter pad are arranged in a plurality of rows and a plurality of columns, and the contact hole communicating part is used for connecting two adjacent contact holes in the same row or is used for connecting two adjacent contact holes in the same column;
the emitter pad forms a concave part at the corresponding position of the contact hole, and the emitter pad forms a concave communicating part at the corresponding position of the contact hole communicating part;
Correspondingly, the plurality of concave parts of the emitter pad are arranged in a plurality of rows and a plurality of columns, the concave communicating parts of the emitter pad are used for connecting two adjacent concave parts in the same row, or the concave communicating parts of the emitter pad are used for connecting two adjacent concave parts in the same column; the plurality of recess portions and the recess communication portion together form the contact pattern.
In some possible embodiments, the contact pattern at the emitter pad cannot be formed at an area where the emitter pad covers the gate electrode.
In some possible embodiments, the thickness of the pad is less than or equal to 10 microns.
In some possible embodiments, the contact pattern includes a plurality of information units, the information units being operable to indicate a number N, at least one of the numbers N being operable to indicate specification information of the semiconductor device;
the information unit comprises M concave parts and N concave communicating parts used for connecting the M concave parts, wherein N is larger than or equal to 0.
The embodiment of the application also provides an electronic device comprising the semiconductor device.
Since the electronic device includes the semiconductor device, the electronic device includes the advantages of the semiconductor device, and the detailed description thereof will be omitted herein.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
Fig. 1 is a schematic structural diagram of a second mounting surface of a semiconductor device according to an embodiment of the present application;
Fig. 2 is a cross-sectional view of A-A view of a semiconductor device according to an embodiment of the present application;
fig. 3 is a cross-sectional view of a semiconductor device according to an embodiment of the present application at a B-B view angle;
Fig. 4 is a cross-sectional view of a C-C view of a semiconductor device according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a gate according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of a contact pattern according to an embodiment of the present application.
Reference numerals illustrate:
100. A pad layer; 110. a contact pattern; 111. a recessed portion; 112. a recessed communication portion; 120. an emitter pad; 130. a gate pad; 200. a conductive layer; 300. a collector layer; 400. a drift layer; 410. a gate; 411. a gate lead-out portion; 412. a gate connection portion; 420. an emitter layer; 430. a base layer; 440. a second doping section; 500. a field stop layer; 600. an interlayer insulating film; 610. a contact hole; 700. a passivation layer; 800. a substrate.
Specific embodiments of the present application have been shown by way of the above drawings and will be described in more detail below. The drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but rather to illustrate the inventive concepts to those skilled in the art by reference to the specific embodiments.
Detailed Description
As described in the background, in the process of manufacturing an integrated circuit, it is generally required to implement connection and signal interaction between a plurality of semiconductor devices by using contact holes of the semiconductor devices. However, when the number of semiconductor devices in the integrated circuit is large and the integrated circuit includes a plurality of semiconductor devices of different types, the semiconductor devices of different types are difficult to identify due to the relatively close sizes of the semiconductor devices of different types, so that the problem of connection errors of the semiconductor devices due to the selection errors of the semiconductor device types is easy to occur.
In order to solve the above technical problems, embodiments of the present application provide a semiconductor device, a manufacturing method thereof, and an electronic apparatus, in which a contact pattern is provided on a portion of a pad provided on a second mounting surface side, so that a semiconductor device can be mounted on a substrate through a first mounting surface of the semiconductor device during a process of mounting and connecting the semiconductor device, and specification information of the semiconductor device can be identified through the contact pattern provided on the second mounting surface, so that difficulty in identifying different types of semiconductor devices is reduced, and a possibility of a connection error of the semiconductor device is reduced.
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.
The following describes the technical scheme of the present application and how the technical scheme of the present application solves the above technical problems in detail with specific embodiments. The following embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.
Referring to fig. 1 to 6, an embodiment of the present application provides a semiconductor device having a first mounting surface and a second mounting surface opposite to the first mounting surface, at least part of a plurality of pads being disposed on the first mounting surface side of the semiconductor device, and another part of the plurality of pads being disposed on the second mounting surface side of the semiconductor device; the portion of the plurality of pads disposed on the first mounting surface side of the semiconductor device is used to connect the substrate 800, the portion of the plurality of pads disposed on the second mounting surface side of the semiconductor device is used to form the contact pattern 110, and the contact pattern 110 can be used to identify specification information of the semiconductor device.
For example, the semiconductor device may be provided as a power type semiconductor device, a pad area of the power type semiconductor device is large relative to other types of semiconductor devices, and the contact pattern 110 is easily formed at the pad of the power type semiconductor device.
Accordingly, the substrate 800 may be configured as a support for mounting a semiconductor device, such as a ceramic copper-clad plate, where the semiconductor device is mounted on the substrate 800 through the first mounting surface, and the contact pattern 110 is disposed on the second mounting surface of the semiconductor device, so that the contact pattern 110 can always face a direction away from the substrate 800 in a process of connecting the semiconductor device to the substrate 800, and a process of identifying specification information of the semiconductor device through the contact pattern 110 is more convenient.
The semiconductor device may be provided as a transistor or a diode, for example, the semiconductor device may be provided as one of an insulated gate field effect transistor (Metal Oxide Semiconductor FIELD EFFECT Transisto, abbreviated as MOSFET), an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, abbreviated as IGBT), and a fast recovery diode (Fast Recovery Diode, abbreviated as FRD). In addition, the position of the contact pattern 110 can be adjusted according to the type of the semiconductor device, so that the position of the contact pattern 110 is more suitable for the use process of the semiconductor device, and the identification process of the semiconductor device is more convenient.
For example, when the semiconductor device is provided as an insulated gate field effect transistor, a portion of the plurality of pads provided on the second mounting surface side of the semiconductor device includes a gate pad electrically connected to the gate electrode, and a source pad electrically connected to the source electrode, at least one of the gate pad and the source pad may be used to form the contact pattern 110.
When the semiconductor device is provided as an insulated gate bipolar transistor, a portion of the plurality of pads provided on the second mounting surface side of the semiconductor device includes a gate pad 130 electrically connected to the gate 410 through the gate lead 411, and an emitter pad 120 electrically connected to the emitter layer 420, at least one of the gate pad 130 and the emitter pad 120 being multiplexed to form the contact pattern 110.
When the semiconductor device is configured as a fast recovery diode, the portion of the plurality of pads disposed on the second mounting surface side of the semiconductor device includes an anode pad electrically connected to the anode, and the anode pad may be multiplexed to form the contact pattern 110.
Referring to fig. 1 to 4, a structure of a semiconductor device is described below taking an example in which the semiconductor device is provided as an insulated gate bipolar transistor. The insulated gate bipolar transistor includes, for example, a conductive layer 200, a collector layer 300, a field stop layer 500, a drift layer 400, an interlayer insulating film 600, a pad layer 100, and a passivation layer 700. The conductive layer 200 corresponds to a first mounting surface of the insulated gate bipolar transistor, the pad layer 100 includes a gate pad 130 and an emitter pad 120, the gate pad 130 and the emitter pad 120 are correspondingly formed on a second mounting surface side of the insulated gate bipolar transistor, and the passivation layer 700 covers an edge of the pad layer 100.
Referring to fig. 2, in the portion of the insulated gate bipolar transistor corresponding to the emitter pad 120, the second mounting surface side of the semiconductor device is set as the upper surface side of the drift layer 400; a P-type base layer 430 is provided on the upper surface side of the n-type drift layer 400, and an n+ -type emitter layer 420 and a p+ -type contact layer 440 are provided on the upper surface side of the P-type base layer 430. The base layer 430, the emitter layer 420, and the contact layer 440 can all be formed by ion implantation or the like. The plurality of gate electrodes 410 disposed at intervals extend to the drift layer 400 through the emitter layer 420 and the base layer 430.
Referring to fig. 4 and 5, the insulated gate bipolar transistor further includes a gate lead-out portion 411 and a gate connection portion 412, the plurality of gates 410 are all connected to the gate lead-out portion 411 through the gate connection portion 412, and the gate connection portion 412 is disposed outside the plurality of gates 410 and electrically connected to the gates; illustratively, the gate connection portion 412 is provided as a square-frame-type gate connection portion 412, and an edge of the square-frame-type gate connection portion 412 is connected to the gate lead-out portion 411. A gate pad 130 is formed on the upper portion of the gate lead 411 through an interlayer insulating film 600, and the gate lead 411 is in contact with the gate pad 130 via a contact hole 610 which is an opening of the interlayer insulating film 600, and the gate lead 411 is electrically connected to the gate pad 130.
Referring to fig. 1, 5 and 6, exemplary contact patterns 110 may be disposed at the gate pad 130; the contact holes 610 between the gate lead-out portion 411 and the gate pad 130 are arranged in a plurality of rows and a plurality of columns, and the contact hole communication portion is used for connecting two adjacent contact holes 610 in the same row or the contact hole communication portion is used for connecting two adjacent contact holes 610 in the same column. The gate pad 130 forms the recess 111 at the corresponding position of the contact hole 610, and the gate pad 130 forms the recess communication 112 at the corresponding position of the contact hole communication. Each of the concave portions 111 passes through the corresponding contact hole 610 to be in contact with the gate lead-out portion 411, and each of the concave portions 111 is electrically connected to the gate lead-out portion 411. Each of the recess communication portions 112 is in contact with the gate lead-out portion 411 through a corresponding contact hole communication portion, and each of the recess communication portions 112 is electrically connected to the gate lead-out portion 411. Correspondingly, the plurality of concave parts 111 of the gate pad 130 are arranged in a plurality of rows and a plurality of columns, and the concave communicating parts 112 of the gate pad 130 are used for connecting two adjacent concave parts 111 in the same row, or the concave communicating parts 112 of the gate pad 130 are used for connecting two adjacent concave parts 111 in the same column; also, the plurality of recess portions 111 and recess communication portions 112 collectively form a contact pattern 110, and the contact pattern 110 can be used to identify specification information of the semiconductor device.
The recess 111 and the recess communication 112 are formed at the corresponding positions of the gate pad 130 by the contact hole 610 and the contact hole communication formed between the gate lead-out 411 and the gate pad 130, and thus the contact pattern 110 for identifying the specification information of the semiconductor device is formed, and thus, the step of forming the contact pattern 110 can be performed by photolithography and etching processes in the process of forming the interlayer insulating film 600 of the semiconductor device, that is, the contact pattern 110 is formed in the process of manufacturing the semiconductor device itself, without adding additional processes such as a laser processing process, and the like, and the larger and more concentrated area at the gate lead-out 411 is used to form the contact pattern 110, so that the contact pattern 110 is easily formed and the contact pattern 110 is easily identified.
An emitter pad 120 is formed on the upper portion of the gate electrode 410 through an interlayer insulating film 600. The emitter layer 420 and the contact layer 440 are in contact with the emitter pad 120 via the contact hole 610, which is an opening portion of the interlayer insulating film 600, and the emitter layer 420 and the contact layer 440 are electrically connected to the emitter pad 120.
The contact holes 610 between the emitter layer 420 and the contact layer 440 and the emitter pad 120 are arranged in a plurality of rows and columns, and the contact hole communication part is used for connecting two adjacent contact holes 610 in the same row or the contact hole communication part is used for connecting two adjacent contact holes 610 in the same column;
the emitter pad 120 forms a recess 111 at a corresponding position of the contact hole 610, and the emitter pad 120 forms a recess communication 112 at a corresponding position of the contact hole communication.
Correspondingly, the plurality of concave parts 111 of the emitter pad 120 are arranged in a plurality of rows and a plurality of columns, and the concave communicating parts 112 of the emitter pad 120 are used for connecting two adjacent concave parts 111 in the same row, or the concave communicating parts 112 of the emitter pad 120 are used for connecting two adjacent concave parts 111 in the same column; the plurality of recess portions 111 and recess communication portions 112 together form a contact pattern (not shown in the drawing).
Since the recess 111 and the recess communication 112 are formed at the corresponding positions of the emitter pad 120 by the contact hole communication portions 610 and between the emitter layer 420 and the contact layer 440, and the contact pattern (not shown) for identifying the specification information of the semiconductor device is formed, the step of forming the contact pattern (not shown) may be performed by photolithography and etching processes in the process of forming the interlayer insulating film 600 of the semiconductor device, that is, the contact pattern (not shown) is formed in the process of manufacturing the semiconductor device itself, without adding additional processes such as a laser processing process, etc.
The contact pattern (not shown) at the emitter pad 120 cannot be formed at an area of the emitter pad 120 covering the gate 410. Further, since the gate electrode 410 is provided in a partial region under the emitter pad 120, the contact hole 610 cannot be provided at any place on the emitter pad, and the contact hole 610 is provided in a small space, and the manufacturability and recognition of the contact pattern (not shown in the figure) are slightly poor.
Also, the thickness of the gate pad 130 and/or the emitter pad 120 is set to be less than or equal to 10 micrometers, for example, the thickness of the gate pad 130 and/or the emitter pad 120 is set to be 5 micrometers, so that the shape of the contact pattern 110 on the gate pad 130 and/or the emitter pad 120 is more similar to the shape of the contact hole 610 and the contact hole communicating portion formed in the interlayer insulating film 600, to ensure the accuracy of the indication of the contact pattern 110.
Referring to fig. 6, the contact pattern 110 includes a plurality of information units, which may be used to indicate the number N; the information unit includes M recessed portions 111, and N recessed communication portions 112 for connecting the M recessed portions 111, N being greater than or equal to 0.
Illustratively, in the information unit, M concave portions 111 are arranged in the same row, and concave communicating portions 112 connect two adjacent concave portions 111 in the same row; it is easy to understand that when two adjacent concave portions 111 in the same row are connected by one concave connecting portion 112, M-1 concave connecting portions 112 are provided in total in the information unit, then the information unit is used to indicate the number n=m-1, so the information unit is used to indicate that the maximum value of the number N is M-1, that is, the maximum value of N is smaller than M.
Or M concave parts 111 are arranged in the same column, and the concave communicating parts 112 are connected with two adjacent concave parts 111 in the same column; when two adjacent concave portions 111 in the same column are all connected by one concave connecting portion 112, M-1 concave connecting portions 112 are provided in the information unit, then the information unit is used to indicate the number n=m-1, so that the information unit is used to indicate that the maximum value of the number N is M-1, i.e. the maximum value of N is smaller than M.
Or the M concave portions 111 are arranged in a plurality of rows and a plurality of columns, the concave communicating portions 112 connect two adjacent concave portions 111 in the same row, and/or the concave communicating portions 112 connect two adjacent concave portions 111 in the same column. For example, when M is set to 4, the four concave portions 111 are arranged in two rows and two columns, and when two adjacent concave portions 111 in the same row and two adjacent concave portions 111 in the same column are all connected by one concave connecting portion 112, the information unit is provided with 4 concave connecting portions 112 in total, and is used to indicate the number n=4, so that the information unit is used to indicate that the maximum value of the number N is M, that is, the maximum value of N is equal to M.
When the six concave portions 111 are arranged in three rows and two columns, and when two adjacent concave portions 111 in the same row and two adjacent concave portions 111 in the same column are all communicated through one concave communicating portion 112, 7 concave communicating portions 112 are provided in the information unit, the information unit is used for indicating the number n=7 at this time, and therefore the information unit is used for indicating that the maximum value of the number N is m+1, that is, the maximum value of N is greater than M.
It is easy to understand that, in the information unit, when the M concave portions 111 are arranged in the same row or in the same column, the information unit is used to indicate that the maximum value of the number N is M-1, that is, the maximum value of N is smaller than M; when the M concave portions 111 are arranged in a plurality of rows and columns, the information unit is used to indicate that the maximum value of the number N is greater than or equal to M.
In some possible implementations, the contact pattern 110 includes a plurality of information portions configured to: the plurality of information units are coded by M-ary to form an information part. Each of the information parts may correspond to one specification information provided to the semiconductor device, including, but not limited to, a model number, a rated voltage, and a rated current of the semiconductor device. For example, one of the information portions may correspond to a model of the semiconductor device, one of the information portions may correspond to a rated voltage of the semiconductor device, and one of the information portions may correspond to a rated current provided to the semiconductor device, which is not further limited in the embodiment of the present application.
Referring to fig. 6, the information part includes a plurality of information units in a row direction of the recess parts 111, in which M is set to 2, and two recess parts 111 are arranged in the same column; it is easy to understand that the binary codes are correspondingly set to binary values, i.e. each information unit can be correspondingly set to a digital 1 in the binary code and a digital 0 in the binary code by the binary codes, so that the information unit can be converted into a binary number by the binary codes; also, the plurality of information units may form binary values by binary encoding.
Referring to fig. 6, exemplary binary encoding is configured to: referring to the information unit x, two concave parts 111 are spaced apart to form a number 0 in binary coding; referring to the information unit y, two concave portions 111 are connected by a concave connection portion 112 to form a numeral 1 in binary coding.
Or in the information units, M is set to 3, three concave parts 111 are arranged in the same column, and a plurality of information units are coded by ternary system to form an information part; it will be readily appreciated that the ternary code is correspondingly provided to a ternary number, i.e. each information unit can be correspondingly provided with the number 0, the number 0 and the number 2 by the ternary code, so that the information unit can be converted into a ternary number by the ternary code.
Illustratively, the ternary code is configured to: the three concave parts 111 are sequentially arranged at intervals along the column direction to form a number 0 in binary coding; two of the three recessed portions 111 adjacent in the column direction are communicated by a recessed communication portion 112 to form a numeral 1 in binary coding; two adjacent concave portions 111 in the column direction among the three concave portions 111 are each communicated through the concave communicating portion 112 to form a numeral 2 in binary coding.
It is easy to understand that the M-ary code may be set to be a quaternary code or a decimal code, and the specific setting manner may refer to a binary code and a ternary code, which is not repeated in the embodiment of the present application. Also, M depressions 111 may be arranged in the same row or in a plurality of rows and columns in the information unit, so that the information unit can be converted into M-ary numbers by M-ary encoding, and at least one M-ary number can be converted into one M-ary number by M-ary encoding.
Referring to fig. 6, in some possible embodiments, M is set to 2 and two recesses 111 are arranged in the same column in the information section. The number of columns of the recess 111 is equal to the number of binary coded bits so that a plurality of information units can be used to indicate one binary value, which is used to indicate specification information of the semiconductor device.
Illustratively, the binary values indicated by the information portion a, which indicates the model of the semiconductor device, will be described by way of example.
As shown in fig. 6, in the right-to-left direction, the first information element includes two concave portions 111 and one concave communicating portion 112, and is correspondingly set to the numeral 1; the second information unit includes two concave parts 111 and one concave communicating part 112, and is correspondingly set to be 1; the third information element includes two concave portions 111 and zero concave communicating portions 112, and is correspondingly set to the number 0; the fourth information element includes two concave portions 111 and zero concave communicating portions 112, and is correspondingly set to the number 0; the fifth information element includes two concave portions 111 and one concave communicating portion 112, and is correspondingly set to the number 1, so that the value indicated by the information portion a is a binary number 10011, that is, 19 in decimal number, and the information portion a is used to indicate the model 19 of the semiconductor device.
Or in the information part, M is set to 2, and two concave parts 111 are arranged in the same column. In the information section, four columns of information elements are used to form one decimal value; in the row direction of the information unit, at least one decimal digit forms a decimal value for indicating specification information of the semiconductor device.
Illustratively, the numerical value indicated by the information portion b for indicating the rated current of the semiconductor device will be described by taking the information portion b as an example.
As shown, in the right-to-left direction, the first four columns of information elements form a decimal value, and the first information element includes two concave portions 111 and a concave communicating portion 112, and is correspondingly set to the number 1; the second information unit includes two concave parts 111 and one concave communicating part 112, and is correspondingly set to be 1; the third information element includes two concave portions 111 and zero concave communicating portions 112, and is correspondingly set to the number 0; the fourth information element includes two concave portions 111 and zero concave communicating portions 112, and is correspondingly set to the number 0; thus, the binary value formed by the first four columns of depressions 111 is 0011, i.e., 3 in decimal value.
And, the fifth information element includes two concave parts 111 and zero concave communicating parts 112, and is correspondingly set to the number 0; in the above manner, it can be obtained that the information portion b is provided correspondingly and is used to indicate that the rated current of the semiconductor device is 3A.
Illustratively, the numerical value indicated by the information portion c is described taking the information portion c as an example, wherein the information portion c is correspondingly disposed and is used to indicate the rated voltage of the semiconductor device.
If the number of columns of the concave portion 111 is equal to the number of binary digits, so that the information portion can be used to indicate a binary digit, the binary value indicated by the information portion c is a binary value 0000011001010000, that is, 1616 in the decimal value, and the information portion c is used to indicate that the rated voltage of the semiconductor device is 1616V.
If the four-column information unit is used for forming a decimal value, the information part c can be used for indicating the decimal value of a four-digit number at maximum, and the binary value formed by the four-column information unit corresponding to the corresponding digit is 0000, namely 0 in the decimal number; the binary value formed by the four columns of information units corresponding to ten digits is 0101, namely 5 in the decimal numbers; the binary value formed by the four columns of information units corresponding to the hundred digits is 0110, namely 6 in decimal numbers; the binary value formed by the four columns of information units corresponding to the kilobits is 0000, that is, 0 in the decimal number, the information part c is used for indicating that the rated voltage of the semiconductor device is 650V.
When four columns of information units are used for forming a decimal value, so that a plurality of columns of information units can be used for indicating the decimal value, the identification process of the information part can be divided into a plurality of decimal numbers for identification, and the identification process of the information part is more convenient.
It will be readily appreciated that when M is set to 2 and the information element is binary coded to form the information portion, the four columns of recesses 111 form a binary value maximum of 1111, i.e. 15 of the decimal values, and the three columns of recesses 111 form a binary value maximum of 111, i.e. 7 of the decimal values, so that it is necessary to form one decimal value by the four columns of recesses 111 to ensure that the decimal numbers 8 and 9 can be formed.
When M is set to 3 and the information element is ternary encoded to form an information portion, the ternary value formed by the two columns of concave portions 111 has a maximum value of 22, i.e., 8 in decimal values. It is therefore necessary to form a decimal number by means of three columns of recesses 111 to ensure that the decimal number 9 can be formed.
In summary, by providing the contact pattern 110 on the partial pad provided on the second mounting surface, the semiconductor device can be mounted on the substrate through the first mounting surface of the semiconductor device in the process of mounting and connecting the semiconductor device, and the specification information of the semiconductor device can be identified through the contact pattern provided on the second mounting surface, so that the difficulty in identifying the semiconductor device can be reduced, and the possibility of connecting the semiconductor device can be reduced in the manufacturing process of the integrated circuit.
The embodiment of the application also provides an electronic device which comprises the semiconductor device in any one of the embodiments. Since the electronic device includes the semiconductor device, the electronic device includes the advantages of the semiconductor device, and the detailed description thereof will be omitted herein.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the apparatus or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
In the description of the present invention, it should be understood that the terms "comprises" and "comprising," and any variations thereof, as used herein, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements that are expressly listed or inherent to such process, method, article, or apparatus.
Unless specifically stated or limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally formed; can be directly connected or indirectly connected through an intermediate medium, and can lead the connection between the two elements or the interaction relationship between the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (8)
1. A semiconductor device, wherein the semiconductor device has a first mounting surface and a second mounting surface opposite to the first mounting surface;
The semiconductor device further includes a plurality of pads, a portion of which is disposed on the first mounting surface side of the semiconductor device, and another portion of which is disposed on the second mounting surface side of the semiconductor device;
the part of the plurality of bonding pads arranged on the first mounting surface side of the semiconductor device is used for connecting a substrate, and the part of the plurality of bonding pads arranged on the second mounting surface side of the semiconductor device is provided with a contact pattern which is used for identifying specification information of the semiconductor device; the contact pattern includes a plurality of information units for indicating a number N, at least one of which is for indicating specification information of the semiconductor device; the information unit comprises M concave parts and N concave communicating parts used for communicating the M concave parts, wherein N is greater than or equal to 0;
the semiconductor device further comprises a gate, a gate pad, a gate lead-out part and a gate connecting part, wherein a plurality of the gates are connected to the gate lead-out part through the gate connecting part, the gate pad is formed on the upper part of the gate lead-out part through an interlayer insulating film, and the gate lead-out part is in contact with and electrically connected with the gate pad through a contact hole which is an opening part of the interlayer insulating film;
The contact holes between the grid lead-out part and the grid bonding pad are arranged in a plurality of rows and a plurality of columns, and the contact hole communicating part is used for communicating two adjacent contact holes in the same row or the contact hole communicating part is used for communicating two adjacent contact holes in the same column;
The grid electrode pad forms a concave part at the corresponding position of the contact hole, and the grid electrode pad forms a concave communicating part at the corresponding position of the contact hole communicating part;
correspondingly, the plurality of concave parts of the gate pad are arranged in a plurality of rows and a plurality of columns, and the concave communicating parts of the gate pad are used for communicating two adjacent concave parts in the same row, or the concave communicating parts of the gate pad are used for communicating two adjacent concave parts in the same column; the plurality of recess portions and the recess communication portion together form the contact pattern.
2. The semiconductor device according to claim 1, wherein the semiconductor device is provided as an insulated gate bipolar transistor;
The plurality of pads are disposed on the second mounting surface side of the semiconductor device, the plurality of pads including a gate pad and an emitter pad.
3. The semiconductor device of claim 1, wherein the semiconductor device is provided as an insulated gate field effect transistor; the portion of the plurality of pads disposed on the second mounting surface side of the semiconductor device includes a gate pad and a source pad.
4. The semiconductor device according to claim 2, wherein,
Further comprising a drift layer;
A base layer provided on the upper surface side of the drift layer;
An emitter layer and a contact layer provided on the upper surface side of the base layer;
A plurality of spaced apart gates extend through the emitter and base layers to the drift layer.
5. The semiconductor device according to claim 4, wherein,
The semiconductor device further includes an emitter pad formed on the upper portion of the gate electrode with an interlayer insulating film interposed therebetween, the emitter pad being electrically connected to the emitter pad through a contact hole which is an opening of the interlayer insulating film, the emitter layer and the contact layer being in contact with each other;
The contact holes between the emitter layer and the contact layer and the emitter pad are arranged in a plurality of rows and a plurality of columns, and the contact hole communicating part is used for communicating two adjacent contact holes in the same row or the contact hole communicating part is used for communicating two adjacent contact holes in the same column;
the emitter pad forms a concave part at the corresponding position of the contact hole, and the emitter pad forms a concave communicating part at the corresponding position of the contact hole communicating part;
correspondingly, the plurality of concave parts of the emitter pad are arranged in a plurality of rows and a plurality of columns, and the concave communicating parts of the emitter pad are used for communicating two adjacent concave parts in the same row, or the concave communicating parts of the emitter pad are used for communicating two adjacent concave parts in the same column; the plurality of recess portions and the recess communication portion together form the contact pattern.
6. The semiconductor device according to claim 5, wherein,
The contact pattern at the emitter pad cannot be formed in a region where the emitter pad covers the gate electrode.
7. The semiconductor device of claim 2, wherein the pad has a thickness of less than or equal to 10 microns.
8. An electronic device comprising the semiconductor device according to any one of claims 1 to 7.
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| CN202310195352.6A CN116093079B (en) | 2023-03-01 | 2023-03-01 | Semiconductor device and electronic device |
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| CN116093079A (en) | 2023-05-09 |
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