CN116090406A - Random verification method and device for ping-pong configuration circuit, upper computer and storage medium - Google Patents
Random verification method and device for ping-pong configuration circuit, upper computer and storage medium Download PDFInfo
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- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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Abstract
The invention discloses a random verification method, a device, an upper computer and a storage medium of a ping-pong configuration circuit, which relate to the field of random control, and are characterized in that a plurality of random tasks are acquired from a preset task library of an integrated circuit, one of the random tasks is randomly distributed to a first circuit or a second circuit, a circuit receiving the random tasks is controlled to execute the tasks, and meanwhile, the random task which is not executed in the random tasks is written into the other circuit, so that the other circuit is controlled to execute the tasks after the task which is currently executed is finished, the task is alternately executed by the two circuits as a cycle, and the normal function of the integrated circuit is determined after all the random tasks are executed. The random operation of a user at random time in practical application can be simply and accurately represented by a mode of acquiring random tasks with random number, and meanwhile, the integrated circuit in ping-pong configuration can be accurately checked by a mode of alternately executing tasks by two circuits.
Description
Technical Field
The present invention relates to the field of random control, and in particular, to a random verification method and apparatus for a ping-pong configuration circuit, an upper computer, and a storage medium.
Background
The design and optimization thought of the existing integrated circuit is mainly based on PPA (power consumption, performance, area), for performance design and optimization, pipeline design is generally used, specifically, the whole integrated circuit is divided into two logic circuits with the same function to perform ping-pong configuration, when the integrated circuit needs to sequentially execute a plurality of tasks, the two logic circuits in the integrated circuit cross-execute the tasks, so that the performance and efficiency of the integrated circuit are improved; in order to ensure normal use of the integrated circuit, functional verification of the integrated circuit is required when the integrated circuit leaves the factory. In the prior art, when performing function verification on an integrated circuit, a task list is usually set for two logic circuits in the integrated circuit in advance, and when starting verification, the two logic circuits are enabled to execute the tasks sequentially according to a preset sequence, so as to determine whether the function of the integrated circuit is normal. However, in practical applications, the operation of the user is not regular, and the irregular operation of the user may cause the integrated circuit to start executing a random number of random tasks at random time, and the verification manner of executing the tasks according to the preset sequence cannot verify whether the integrated circuit functions normally in the practical application scenario.
Disclosure of Invention
The invention aims to provide a random verification method and device for a ping-pong configuration circuit, an upper computer and a storage medium, which can simply and accurately represent the random operation of a user in random time in practical application, and can also accurately verify an integrated circuit of the ping-pong configuration.
In order to solve the technical problems, the present invention provides a random verification method of a ping-pong configuration circuit, which is applied to a processor in an upper computer, wherein the upper computer is respectively connected with a first circuit and a second circuit in an integrated circuit, and functions of the first circuit and the second circuit are the same, and the verification method comprises:
when a random verification instruction is received, n random tasks are obtained from a preset task library of the integrated circuit, wherein n is a positive integer;
randomly assigning one of n said random tasks to said first circuit or said second circuit;
controlling a circuit which receives the random task to execute the random task, and simultaneously writing a random task which is not executed in the random tasks in n into another circuit so as to control the other circuit to execute the random task after the execution of the random task which is currently being executed is completed;
and after all the random tasks are executed, determining that the integrated circuit is normal in function.
Preferably, before randomly assigning one of the n random tasks to the first circuit or the second circuit, the method further comprises:
taking a random task in n random tasks as a current task, and taking n-1 random tasks as tasks to be executed;
taking x of n-1 tasks to be executed as tasks to be executed of the first circuit, and y as tasks to be executed of the second circuit, wherein x and y are natural numbers and x+y=n-1;
randomly assigning one of n of the random tasks to the first circuit or the second circuit, comprising:
randomly assigning the current task to the first circuit or the second circuit;
writing random tasks, of which random ones are not executed, in another circuit, comprising:
and writing a random task in the tasks to be executed, which correspond to the other circuit, into the other circuit.
Preferably, x of the n-1 tasks to be executed are taken as tasks to be executed of the first circuit, and y are taken as tasks to be executed of the second circuit, including:
determining a first identifier of the first circuit and a second identifier of the second circuit, respectively;
the first identifier is assigned to x of the random tasks and the second identifier is assigned to y of the random tasks.
Preferably, randomly assigning one of n random tasks to the first circuit or the second circuit includes:
one of n random tasks is randomly written into a fifo memory of the first circuit or the second circuit.
Preferably, after controlling the circuit that receives the random task to execute the random task, the method further includes:
judging whether the result of the circuit executing the random task is correct or not;
if not, generating a prompt signal, and sending the prompt signal to a prompt module so that the prompt module sends out prompts.
Preferably, before the circuit that receives the random task is controlled to execute the random task, the method further includes:
setting a semaphore for a circuit that received the random task to a semaphore that indicates write inhibition;
after controlling the circuit that receives the random task to execute the random task, the method further comprises:
setting a semaphore for the circuit that performed the random task to a semaphore indicating write permission.
Preferably, before the circuit that receives the random task is controlled to execute the random task, the method further includes:
judging whether the random task exists in the circuit or not;
if yes, executing the random task in a circuit which receives the random task in an entering control mode;
if not, writing the random task into the circuit, and entering a step of controlling the circuit which receives the random task to execute the random task.
The application also provides a random verification device of a ping-pong configuration circuit, which comprises:
a memory for storing a computer program;
and the controller is used for realizing the steps of the random verification method of the ping-pong configuration circuit when executing the computer program.
The application also provides an upper computer, which comprises an upper computer body and a random verification device of the ping-pong configuration circuit;
the upper computer body is connected with the random verification device of the ping-pong configuration circuit.
The present application also provides a storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of a random verification method for a ping pong configuration circuit as described above.
The application provides a random verification method, a device, an upper computer and a storage medium of a ping-pong configuration circuit, which relate to the field of random control, and are characterized in that a plurality of random tasks are acquired from a preset task library of an integrated circuit, one of the random tasks is randomly distributed to a first circuit or a second circuit, a circuit receiving the random tasks is controlled to execute the random tasks, and meanwhile, one random task which is not executed in the random tasks is written into another circuit, so that the other circuit is controlled to execute the random tasks after the execution of the random task which is currently executed is finished, the two circuits are used as a cycle to alternately execute the tasks, and the random control of the integrated circuit is determined to be finished after the execution of all the random tasks is finished. The random operation of a user at random time in practical application can be simply and accurately represented by a mode of acquiring random tasks with random number, and meanwhile, the integrated circuit in ping-pong configuration can be accurately checked by a mode of alternately executing tasks by two circuits.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required in the prior art and the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flowchart of a random verification method for a ping-pong configuration circuit provided in the present application;
fig. 2 is a schematic structural diagram of a random verification device of a ping-pong configuration circuit provided in the present application.
Detailed Description
The core of the invention is to provide a random verification method, a random verification device, an upper computer and a random verification storage medium for a ping-pong configuration circuit, which can simply and accurately represent the random operation of a user in random time in practical application and can also accurately verify an integrated circuit of the ping-pong configuration.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The present integrated circuit is mainly designed and optimized based on PPA (power consumption, performance, area), in the performance optimization, the optimal mode is pipeline design, and for this point, the whole integrated circuit is generally divided into two parts, and the internal structures of the two parts may be different, but the realized functions are the same, and the purpose of improving the performance of the integrated circuit is realized by designing two sets of circuit logic to perform ping-pong processing. Before the integrated circuits are shipped to be used, the integrated circuits need to be verified in order to ensure the yield and stability of the integrated circuits, and the integrated circuits need to execute random tasks at random time in consideration of the use habits of users, so that the upper computer needs to perform random control when verifying the integrated circuits. However, because of the large number and variety of internal elements of the integrated circuit, the timing control is complex, and the host computer is difficult to generate perfect random timing when verifying the timing, so that the completeness of the timing is difficult to verify.
In order to solve the above technical problems, please refer to fig. 1, fig. 1 is a flowchart of a random verification method of a ping-pong configuration circuit provided in the present application, which is applied to a processor in an upper computer, wherein the upper computer is respectively connected with a first circuit and a second circuit in an integrated circuit, and functions of the first circuit and the second circuit are the same, and the verification method includes:
s1: when a random verification instruction is received, n random tasks are obtained from a preset task library of the integrated circuit, wherein n is a positive integer;
s2: randomly assigning one of n random tasks to the first circuit or the second circuit;
s3: the circuit which receives the random tasks is controlled to execute the random tasks, and meanwhile, random tasks which are not executed in random in the n random tasks are written into the other circuit, so that the other circuit is controlled to execute the random tasks after the execution of the random tasks which are currently executed is finished;
s4: and after all the random tasks are executed, determining that the integrated circuit is normal in function.
In order to realize random control and verification, the random tasks of random number are acquired through random time, and it can be understood that in actual application, due to different requirements, use habits, use time and the like of different users, the integrated circuit may receive any command from the user at any time point, so that in verification before delivery, user operation in actual application needs to be simulated through random control. The integrated circuit has a plurality of functions, tasks corresponding to all the functions of the integrated circuit can be stored in a preset task library in advance, when verification is carried out, the upper computer takes out a random number of tasks from the preset task library at a random time point, and the type of the specifically taken tasks and the corresponding functions are random and non-repeated, so that the action of random operation of a user in the actual use is shown.
After n random tasks are acquired, as the integrated circuit is provided with the first circuit and the second circuit with the same functions, the first circuit and the second circuit can be specifically two circuits with different structures (or the same structure) but the same functions, such as an FPGA (Field Programmable Gate Array ) or a CPLD (Complex Programmable logic device, complex programmable logic device) and the like, and the first circuit and the second circuit are arranged on the same circuit board or are spliced together to form the integrated circuit. Because the two circuits are idle before the task is acquired, on the premise that the user has no requirement on the order of task completion, 1 random task in n random tasks can be distributed to one random circuit so as to be executed after the task is written in the circuit; at this time, in order to verify the ping-pong design of the integrated circuit, while the circuit performs the random task, for the circuit on the other side that is not performing the task, it is necessary to write 1 random task out of the remaining n-1 random tasks into the circuit, and when the above-mentioned circuit finishes performing the random task, the circuit on the other side then performs the next task, thereby improving the efficiency by saving the time of writing the random task. For example, there are a total of 4 random tasks, 1 of which is first assigned to the first circuit, which needs to be written into the first circuit in order to control its execution; meanwhile, 1 random task is selected from the remaining 3 random tasks which are not executed and is distributed to the second circuit, and the random tasks are written into the second circuit, when the first circuit executes the first random task, the second circuit can directly execute the second random task, and the time required by writing is saved; at this time, 1 random task is selected from the remaining 2 random tasks which are not executed and written into the first circuit, and so on.
Through the mode that one circuit is executing tasks and simultaneously writing the next task into the other circuit, pipeline running water design is realized, when the integrated circuit is normal, the random tasks can be normally and smoothly executed, when all the random tasks are executed, the random control on the integrated circuit can be finished, the integrated circuit is judged to be qualified and normal, and if the tasks are found to be incapable of being successfully executed, a prompt signal can be generated to prompt staff, so that the staff can find problems in time.
In summary, when a random verification instruction is received, a plurality of random tasks are acquired from a preset task library of the integrated circuit, one of the random tasks is randomly distributed to the first circuit or the second circuit, the circuit receiving the random tasks is controlled to execute the random tasks, and meanwhile, the random tasks which are not executed in the random tasks are written into the other circuit, so that the other circuit is controlled to execute the random tasks after the execution of the random tasks which are currently executed is finished, the two circuits are used as a cycle to alternately execute the tasks, and the function of the integrated circuit is determined to be normal after all the random tasks are executed. The random operation of a user at random time in practical application can be simply and accurately represented by a mode of acquiring random tasks with random number, and meanwhile, the integrated circuit in ping-pong configuration can be accurately checked by a mode of alternately executing tasks by two circuits.
Based on the above embodiments:
as a preferred embodiment, before randomly assigning one of the n random tasks to the first circuit or the second circuit, further comprising:
taking a random task in n random tasks as a current task, and taking n-1 random tasks as tasks to be executed;
taking x of the n-1 tasks to be executed as tasks to be executed of the first circuit, and y as tasks to be executed of the second circuit, wherein x and y are natural numbers and x+y=n-1;
randomly assigning one of n random tasks to the first circuit or the second circuit, comprising:
randomly distributing the current task to the first circuit or the second circuit;
writing random tasks, of which random ones are not executed, into another circuit, comprising:
and writing random one task of all unexecuted tasks to be executed corresponding to the other circuit into the other circuit.
For simple allocation of random tasks, in this application, these random tasks may be allocated in advance to their corresponding circuits. Specifically, one of the random tasks is first used as a current task to be executed, the other tasks are used as tasks to be executed, the first task to be executed is randomly written into a certain circuit, the other tasks can be randomly allocated, and when allocation is performed, the probability of each task being allocated to which circuit can be set according to the performance between the two circuits in consideration that the performance of the two circuits can be the same but the performance of the two circuits can be divided into high and low values, so that the number of the tasks to be executed allocated to the two circuits can be equal or approximate. After tasks are allocated in advance, when one circuit executes the corresponding random tasks, the other circuit writes the corresponding tasks to be executed, and the task writing is not needed to be selected from the random tasks in real time, so that the time for selecting the tasks is saved. Based on this, a random task can be simply assigned.
As a preferred embodiment, taking x of the n-1 tasks to be performed as tasks to be performed by the first circuit, and y as tasks to be performed by the second circuit, includes:
determining a first identifier of the first circuit and a second identifier of the second circuit, respectively;
a first identifier is assigned to x random tasks and a second identifier is assigned to y random tasks.
For simple allocation of the random tasks, in this application, the allocation may be performed by means of identifiers, first determining the identifiers of the first circuit and the second circuit, and then selecting one of the first identifier and the second identifier for each random task as the identifier of the random task, so as to mark the random tasks, which circuit needs to execute. Further, whether these random tasks are executed or not may also be indicated by an identifier, for example, by marking a random task that is not executed with 0 and a random task that is already executed with 1, so that it is simply indicated whether the random task is executed or not. Based on this, a random task can be simply assigned.
As a preferred embodiment, randomly assigning one of n random tasks to the first circuit or the second circuit comprises:
one of n random tasks is randomly written into fifo memory of the first circuit or the second circuit.
The Fifo (First Input First Output) memory is a Fifo (first in first out) dual-port buffer, i.e. the first task entering the Fifo memory is executed first, each task is output and executed according to the sequence of entering the Fifo, and in this way, the data and tasks written into the circuit are gathered to push and store, so that the parallel bus operation caused by errors can be avoided, and the operation load of the circuit is reduced.
As a preferred embodiment, after controlling the circuit that receives the random task to perform the random task, the method further includes:
judging whether the result of the circuit executing the random task is correct or not;
if not, generating a prompt signal and sending the prompt signal to the prompt module so that the prompt module sends out prompts.
In order to simply prompt the staff, the upper computer can also detect the execution result of the circuit after executing the random task, and can determine whether the random task is normally and successfully executed by comparing the actual execution result of the random task with a pre-stored reference execution result; and when the execution exception and failure are found, prompting a worker through a prompting module. The prompting module can be a sound prompting module or a light prompting module and the like arranged on the upper computer, and also can be a prompting module arranged on the integrated circuit, and the application is not limited to the prompting module. Based on this, the staff can be simply prompted.
As a preferred embodiment, before controlling the circuit that receives the random task to perform the random task, the method further includes:
setting a semaphore for a circuit that receives the random task to a semaphore indicating that writing is prohibited;
after controlling the circuit that received the random task to perform the random task, further comprising:
the semaphore for the circuit that performed the random task is set to the semaphore indicating that writing is allowed.
To avoid the case of multi-tasking, in this application, the semaphore is used to control whether a task can be written to a circuit. Specifically, when a task is written into a circuit, the semaphore sempore_x_reg get is used as an identifier indicating that the circuit cannot write other tasks before executing the task, and when a random task is executed, the semaphore sempore_x_reg put is used as an identifier indicating that the circuit can continue to write other tasks, wherein x is the identifier of the circuit. When one circuit is executing a random task, the upper computer can be ensured not to be wrongly written into the circuit executing the random task when the subsequent random task is written into the other circuit due to the limitation of the semaphore, and the semaphore can be further matched with fifo, so that the situations of multi-task writing and executing can be avoided.
As a preferred embodiment, before controlling the circuit that receives the random task to perform the random task, the method further includes:
judging whether a random task exists in the circuit or not;
if yes, executing the random task in the circuit which receives the random task in the access control mode;
if not, writing the random task into the circuit, and entering a step of controlling the circuit receiving the random task to execute the random task.
In order to improve efficiency, in the present application, before the control circuit executes the random task, it is further required to determine whether the random task allocated to the circuit is written into the circuit before the random task is executed, and if not, the random task is written into the circuit before the random task is executed; if written, the circuit can be directly controlled to perform the random task without the need to write again. Based on the above, considering the long-term use efficiency of the integrated circuit in practical application, when a random task is allocated to a certain circuit, if the random task is executed for the first time by the circuit, the random task can be executed only by writing the random task into the circuit, after the execution is finished, the configuration information of the random task is stored in the circuit, and when the random task is executed again on the circuit, the random task can be directly executed without writing the random task again, so that the time for writing the random task again is saved.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a random verification device of a ping-pong configuration circuit provided in the present application, including:
a memory 21 for storing a computer program;
a controller 22 for implementing the steps of the random verification method of the ping pong configuration circuit as described above when executing a computer program.
For a detailed description of a random verification apparatus for a ping-pong configuration circuit provided in the present application, please refer to an embodiment of a random verification method for a ping-pong configuration circuit, which is not described herein again.
The application also provides an upper computer, which comprises an upper computer body and a random verification device of the ping-pong configuration circuit;
the upper computer body is connected with a random verification device of the ping-pong configuration circuit.
For a detailed description of an upper computer provided in the present application, please refer to an embodiment of a random verification method of a ping-pong configuration circuit, which is not described herein.
The present application also provides a storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of a random verification method for a ping pong configuration circuit as described above.
For a detailed description of a storage medium provided in the present application, please refer to an embodiment of a random verification method of a ping-pong configuration circuit, which is not described herein.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
Claims (10)
1. The random verification method of the ping-pong configuration circuit is characterized by being applied to a processor in an upper computer, wherein the upper computer is respectively connected with a first circuit and a second circuit in an integrated circuit, the functions of the first circuit and the second circuit are the same, and the verification method comprises the following steps:
when a random verification instruction is received, n random tasks are obtained from a preset task library of the integrated circuit, wherein n is a positive integer;
randomly assigning one of n said random tasks to said first circuit or said second circuit;
controlling a circuit which receives the random task to execute the random task, and simultaneously writing a random task which is not executed in the random tasks in n into another circuit so as to control the other circuit to execute the random task after the execution of the random task which is currently being executed is completed;
and after all the random tasks are executed, determining that the integrated circuit is normal in function.
2. The method of random verification of a ping pong configuration circuit of claim 1, further comprising, prior to randomly assigning one of n of the random tasks to the first circuit or the second circuit:
taking a random task in n random tasks as a current task, and taking n-1 random tasks as tasks to be executed;
taking x of n-1 tasks to be executed as tasks to be executed of the first circuit, and y as tasks to be executed of the second circuit, wherein x and y are natural numbers and x+y=n-1;
randomly assigning one of n of the random tasks to the first circuit or the second circuit, comprising:
randomly assigning the current task to the first circuit or the second circuit;
writing random tasks, of which random ones are not executed, in another circuit, comprising:
and writing a random task in the tasks to be executed, which correspond to the other circuit, into the other circuit.
3. The random verification method of a ping-pong configuration circuit according to claim 2, wherein x of n-1 of the tasks to be performed are taken as tasks to be performed by the first circuit, and y are taken as tasks to be performed by the second circuit, comprising:
determining a first identifier of the first circuit and a second identifier of the second circuit, respectively;
the first identifier is assigned to x of the random tasks and the second identifier is assigned to y of the random tasks.
4. The random verification method of a ping-pong configuration circuit of claim 1, wherein randomly assigning one of n of the random tasks to the first circuit or the second circuit comprises:
one of n random tasks is randomly written into a fifo memory of the first circuit or the second circuit.
5. The method of random verification of a ping pong configuration circuit of claim 1, further comprising, after controlling the circuit that received the random task to perform the random task:
judging whether the result of the circuit executing the random task is correct or not;
if not, generating a prompt signal, and sending the prompt signal to a prompt module so that the prompt module sends out prompts.
6. A method of random verification of a ping pong configuration circuit as claimed in any one of claims 1 to 5, further comprising, prior to controlling the circuit receiving the random task to perform the random task:
setting a semaphore for a circuit that received the random task to a semaphore that indicates write inhibition;
after controlling the circuit that receives the random task to execute the random task, the method further comprises:
setting a semaphore for the circuit that performed the random task to a semaphore indicating write permission.
7. The method of random verification of a ping pong configuration circuit of claim 6, further comprising, prior to controlling the circuit that received the random task to perform the random task:
judging whether the random task exists in the circuit or not;
if yes, executing the random task in a circuit which receives the random task in an entering control mode;
if not, writing the random task into the circuit, and entering a step of controlling the circuit which receives the random task to execute the random task.
8. A random verification apparatus for a ping pong configuration circuit, comprising:
a memory for storing a computer program;
a controller for implementing the steps of the random verification method of a ping pong configuration circuit as claimed in any one of claims 1 to 7 when executing said computer program.
9. The upper computer is characterized by comprising an upper computer body and a random verification device of the ping-pong configuration circuit as claimed in claim 8;
the upper computer body is connected with the random verification device of the ping-pong configuration circuit.
10. A storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the random verification method of a ping pong configuration circuit as claimed in any one of claims 1 to 7.
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