CN115085765A - FPGA-based PLC system receiving end equal gain combination realization method - Google Patents

Abstract

The invention relates to a method for realizing equal gain combination of a PLC system receiving end based on an FPGA, and belongs to the technical field of Internet of things. The current data is frame control data, the state machine controls the current state to be a frame control operation state, simultaneously, the input circuit is opened, the merging circuit accumulates the input data after de-interleaving, and the merged primary data is written into the primary frame control RAM; in addition, the current data is load data, the state machine controls the current state to be a load operation state, the input circuit is opened firstly to write the input data into the input storage RAM, then the de-interleaving circuit and the merging circuit are opened, and after de-interleaving and merging are finished, the data is written into the load output RAM. After each state is finished, the state machine enters an output state, and data is read from the output storage RAM. The invention realizes that the equal gain diversity combining digital circuit of the communication receiving end of the Internet of things is controlled by the state machine, effectively shortens the diversity combining time delay and reduces the circuit resource consumption.

Description

FPGA-based PLC system receiving end equal gain combination realization method

Technical Field

The invention belongs to the technical field of Internet of things, and relates to a method for realizing equal gain combination of a PLC system receiving end based on an FPGA.

Background

Power Line Communication (PLC) is a communication method that uses the existing power grid for information transmission. Compared with other communication technologies, the method has the advantages of low cost, wide range, stable operation and the like. The same data is transmitted on a plurality of independent paths by using a diversity technology at a transmitting end of the PLC communication system, and channel fading is resisted at a receiving end by using a diversity combining technology, so that the transmission reliability is improved, and the error rate is reduced; because the channel coding and decoding can correct random errors and is difficult to correct a lot of continuous burst errors, the receiving end firstly de-interleaves to convert the burst errors caused by the channel into random errors, and then the channel decoding corrects the random errors.

In view of the above advantages, the broadband power line communication system needs to implement a diversity combining function at the receiving end. The merging technology comprises the following steps: selective Combining (SC) only has one effective weighting coefficient, and the rest are 0, the selective Combining method is simple and easy to realize, but the anti-fading performance is poor because the unselected branch signals are discarded; maximum Ratio Combining (MRC), the Combining mode weights multiple paths of signals, the weight is determined by the Ratio of signal voltage and noise power corresponding to each path of signal, the noise environment in the power line communication system is complex, the weight is not well determined, and the hardware is difficult to realize due to the need of considering the variable weight of multiple paths; equal Gain Combining (EGC) each branch signal of the Combining mode is multiplied by the same weight and then added, compared with maximum ratio Combining, the hardware is simple to realize, and the performance is close to the maximum ratio Combining.

The parallel characteristic of FPGA (field Programmable Gate array) and the architecture without instructions and shared memory determine that the FPGA has lower time delay; meanwhile, the programmable characteristic of the circuit is that a user can appoint the FPGA to realize a certain digital circuit through a program, and the program can be modified for many times so as to correct errors in algorithm realization; and which has a cheaper cost. Therefore, when the PLC system receives and transmits the ip, an essential link is to realize an algorithm on the FPGA for verification. Similarly, when an asic (application Specific Integrated circuit), i.e., an asic, is made, it is also necessary to implement the algorithm on the FPGA.

The hardware implementation based on the FPGA needs to consider the two problems of resource occupation and clock frequency, and generally, more resources are occupied to replace lower time delay, so the area of the integrated circuit becomes larger and the manufacturing cost becomes higher. There is a need to strike a balance between the requirements of resources and system latency.

Disclosure of Invention

In view of this, the present invention provides a method for implementing gain combining at the receiving end of a PLC system based on an FPGA.

In order to achieve the purpose, the invention provides the following technical scheme:

a PLC system receiving end equal gain combination realization method based on FPGA includes equal gain combination of load data and equal gain combination of frame control number;

the equal gain combination of the load data specifically comprises:

s11: instantiating two single-port RAMs with the depth of 51 and the width of 24 as a load input RAM of a ping-pong structure, instantiating 4 double-port RAMs with the depth of 2500 and the width of 10 as an output RAM of load data: outbuf1, outbuf2, outbuf3, outbuf 4;

s12: setting the initial state of the state machine to be an IDLE state, judging according to a diversity mode when receiving an integral enable signal en and when input load soft information is valid, namely S _ valid is 1, if the diversity mode is once, entering the copy entry state, wherein the state is the input combination state of the load data which is subjected to the diversity once, and jumping to the step S13; if the diversity is multiple times, the state machine enters a PAYLOADPUTDORENTERADD state, the state is the input of the diversity multiple load data, the interleaving is removed, the state is combined, and the step S14 is skipped;

s13: opening an input circuit module, namely en _ input is 1, and opening a merging circuit, namely en _ add is 1; the input circuit calculates an input data write address adrone, the input address is 0-TotalCarrierNum-1, wherein TotalCarrierNum is the number of data subcarriers which are copied once in diversity, the parameter is given by a control module where a state machine is located, the input data and the corresponding input data write address are sent to a merging circuit, and the step S16 is skipped;

s14: opening an input circuit, namely en _ input is 1, opening a merging circuit, namely en _ add is 1, and opening a de-interleaving circuit, namely en _ depth is 1; the input circuit writes input data into load data input RAM of a ping-pong structure, and the de-interleaving circuit gives a de-interleaving address: DeinterInAdddr, DeinterOutAddr, state machine control circuit gives the address DeinterStartAdddr of depacketizing shift;

s15: the load data input RAM reads data pointer _ data according to the DeinterInaddr, beats the data by one beat, delays one clock period and inputs the data to the merging circuit;

s16: the write address OutWriteAddr and the merged read address AddReadAddr of the output storage RAM are given in a merging circuit;

s17: when the diversity number counter is one, namely cnt _ CopyNum is 1, the load output storage RAM writes load data according to OutWriteAddr, and when the diversity number counter is more than one, the load output storage RAM reads the combined data add _ data according to AddReadAddr and adds the combined data add _ data with the load data, and then writes the combined data into the load output storage RAM;

s18: the state machine enters an OUTPUT state; turning off the input circuit and the merging circuit, namely en _ add is 0, en _ input is 0, turning on the output circuit, namely en _ output is 1, sequentially reading out data of a load output storage RAM by the output circuit, and dividing the data by the number of times of copying to output the data as m _ data;

s19: closing the output circuit, namely en _ output is 0, and the state machine control circuit is in an IDLE state and waits for the arrival of the next frame data;

s110: when the next frame data is valid, go back to step S12;

the equal gain combination of the frame control number specifically comprises:

s21: two dual-port RAMs with a depth of 256 and a width of 14 are exemplified as frame-controlled storage RAMs: the width of the frame _ addr _ i and the frame _ addr _ q is 14, so that the frame _ addr _ i and the frame _ addr _ q cannot overflow during combination, and the initial values are all 0;

s22: setting the initial state of a state machine to be an IDLE state, when receiving an integral enable signal en and inputting i paths and q paths of frame control soft information, namely s _ valid is 1, the state machine enters an FCINPUTADD state, an input circuit module is opened, namely en _ input is 1, and a merging circuit is opened, namely en _ add is 1;

s23: the input circuit adds one to each clock period according to the carrier wave offset required by the standard to generate a write address corresponding to each bit of soft information;

s24: the tail of the data of the two paths of the input circuits i and q is supplemented with 1 with the bit width of 4 bits, and the two paths of data frame _ data _ i and frame _ data _ q and the two paths of corresponding addresses of the i and q, namely frame _ addr _ i and frame _ addr _ q, are sent to a merging circuit;

s25: the merging circuit stores the RAM from the frame control according to frame _ addr _ i, frame _ addr _ q: reading two paths of data add _ data _ i and add _ data _ q to be added from fcoutbuf _ i and fcoutbuf _ q, correspondingly adding the two paths of data add _ data _ i and add _ data _ q to the frame _ data _ i and frame _ data _ q, and writing the two paths of data add _ data _ i and add _ data _ q into a frame control RAM according to the addresses of the frame _ addr _ i and frame _ addr _ q; the lower 4 bits of the data generated after the addition are the copying times of each bit of the data of the i path and the q path;

s26: the state machine enters an OUTPUT state; closing the input circuit and the merging circuit, namely en _ add is 0, en _ input is 0, opening the output circuit, namely en _ output is 1, giving two paths of 0-255 reading addresses by the output circuit, namely when the output is effective, the first clock cycle address is 0, the second clock cycle address is 1, and so on, until the 256 clock cycle is 255, and transmitting the address to the frame control storage RAM;

s27: reading out data outdata _ i and outdata _ q by the frame control storage RAM according to the read address of S3;

s28: defining data obtained by adding the outdata _ i and the outdata _ q in the output circuit as frameouttmp, and calculating frameouttmp [13:4]/frameouttmp [3:0] as output m _ data of the partial set combining module;

s29: turning off the output circuit, namely en _ output is 0, finishing the output of the frame control merging data for one time, and waiting for the arrival of the next frame data when the state machine control circuit is in an IDLE state; and (4) frame control storage RAM: fcoutbuf _ i, fcoutbuf _ q write all 0 data again;

s210: when the next frame data is valid, the process returns to step S22.

Optionally, the output RAM as the load data specifically includes:

if the modulation order is 1, only the soft information corresponding to 1bit data is valid in each clock cycle, firstly writing the input data s _ data [5:0] into outbuf1, writing outbuf1 with the full depth 2500, writing the input data s _ data [5:0] into outbuf2, writing outbuf2 with the full depth 2500, writing outbuf3, writing outbuf3 with the full depth 2500, and writing outbuf 4; if the modulation order is 2, since 12-bit soft information corresponding to 2-bit data is valid in each clock cycle, data is written into outbuf1 and outbuf2 at the same time, and input data s _ data [5:0] is written into outbuf1 and s _ data [11:6] write to outbuf2, outbuf1, outbuf2 simultaneously after full depth 2500, write to outbuf3, outbuf4 simultaneously; if the modulation order is 4, every clock cycle, there is 24-bit soft information corresponding to 4-bit data valid, and simultaneously, the write operation is performed for outbuf1, outbuf2, outbuf3 and outbuf 4: s _ data [5:0] writes outbuf1, s _ data [11:6] writes outbuf2, s _ data [17:12] writes outbuf3, and s _ data [13:18] writes outbuf 4.

Optionally, the read-write address of the write operation is given by:

when the modulation mode is BPSK:

diversity is carried out for multiple times: when DeinterOutAddr + DeinterStartAddr <2500, AddReadAddr ═ OutWriteAddr ═ DeinterOutAddr + DeinterStartAddr;

when 2500< DeinterOutAddr + DeinterStartAddr <5000, AddReadAddr ═ OutWriteAddr ═ DeinterOutAddr + DeinterStartAddr-2500;

(ii) AddReadAddr ═ OutWriteAddr ═ DeinterOutAddr + DeinterStartAddr-5000 when 5000< DeinterOutAddr + DeinterStartAddr < 7500;

(ii) when DeinterOutAddr + DeinterStartAddr >7500, AddReadAddr ═ OutWriteAddr ═ DeinterOutAddr + DeinterStartAddr-7500;

standard definition, diversity does not have BPSK modulation mode at one time;

when the modulation mode is QPSK:

diversity is carried out for multiple times: when DeinterOutAddr + DeinterStartAddr <2500, AddReadAddr ═ OutWriteAddr ═ DeinterOutAddr + DeinterStartAddr;

when 2500< DeinterOutAddr + DeinterStartAddr <5000, AddReadAddr ═ OutWriteAddr ═ DeinterOutAddr + DeinterStartAddr-2500;

diversity once: when the addrone is <2500, AddReadAddr ═ addr; AddReadAddr outpr addr-2500 when 2500< addrone < 5000;

when the modulation mode is 16 QAM:

diversity is carried out for multiple times: AddReadAddr ═ OutWriteAddr ═ deinteroutunaddr + DeinterStartAddr;

diversity once: AddReadAddr ═ addr ═ addre.

Optionally, the DeinterStartAddr is: the PLC standard specifies that each diversity of a sending end circularly moves right by taking a group as a unit, how many groups to circularly move right are stored in a register in a state machine control module at a receiving end, the circular right movement of the DeinterStartAddr by taking an interleaving block as a unit is realized by a counter, and a right movement parameter is updated when one diversity is finished so as to facilitate the generation of the DeinterStartAddr of the next diversity.

Optionally, the PLC standard specifies that the subcarrier number address of each interleaving block at the transmitting end is written in 0-carriernum-1 by row according to a step length, read out by column, and then perform circular right shift on the read address; in the de-interleaving implementation at the receiving end, two addresses are generated: DeinterInAdddr uses a counter to realize the left shift of the cycle, DeinterOutAddr uses a row counter and a column counter to realize the writing by the row and the reading by the column.

Optionally, the receiving end reads data from the load input RAM of the load ping-pong structure according to deiterinaddr, and writes the data into the load output RAM according to deiterstartaddr + deiteroutaddr, thereby completing deinterleaving.

Optionally, when equal gain combining of the frame control numbers is performed, for multi-frame data combining, a frame control storage RAM corresponding to the next frame data: fcoutbuf _ i and fcoutbuf _ q are not all 0, and are merging results of previous frame data, when the output of the frame control merging data of the previous frame is finished, and the merging of the load data of the previous frame is started, the frame control storage RAM is subjected to: fcoutbuf _ i, fcoutbuf _ q write all 0 data again, so this operation does not increase the delay;

reading the data to be added and writing the added data from fcoutbuf _ i and fcoutbuf _ q simultaneously, reading the data at the port a and writing the data at the port b in the same clock cycle, wherein the write address is one clock cycle later than the read address, namely the write address beats one beat in the top-level file;

after the merging, the data outdata _ i and outdata _ q to be output are read out from fcoutbuf _ i and fcoutbuf _ q, and the reading and writing operations are not at the same time.

The invention has the beneficial effects that:

1. according to the implementation scheme of the equal-gain diversity combining module, the state of a state machine is set, the diversity combining of a PLC receiving end is achieved, both simulation verification and board level verification show that the equal-gain diversity combining module meets the functional requirements of a PLC standard algorithm, and a speed Grae-2 chip is adopted, so that the clock frequency can reach 134M.

2. The register of the ping-pong structure ensures that data processing can be uninterrupted, and further reduces time delay.

3. The circuit resource consumption of the invention is low, the parameter and the de-interleaving address of the whole module except the fixed parameter defined by the standard are all calculated by the internal circuit, the data are not required to be stored by using the memory, the circuit storage resource is effectively saved, and the chip adopting speed Grae-2 occupies 1 percent of the register, RAM resource, 3 percent of the logic resource and the lookup table.

Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the means of the instrumentalities and combinations particularly pointed out hereinafter.

Drawings

For the purposes of promoting a better understanding of the objects, aspects and advantages of the invention, reference will now be made to the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a block diagram of an equal gain diversity combining architecture;

FIG. 2 is a state transition diagram;

FIG. 3 is a schematic diagram of de-interleaving;

FIG. 4 is a merged schematic.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention in a schematic way, and the features in the following embodiments and examples may be combined with each other without conflict.

Wherein the showings are for the purpose of illustrating the invention only and not for the purpose of limiting the same, and in which there is shown by way of illustration only and not in the drawings in which there is no intention to limit the invention thereto; to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.

The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar components; in the description of the present invention, it should be understood that if there is an orientation or positional relationship indicated by terms such as "upper", "lower", "left", "right", "front", "rear", etc., based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not an indication or suggestion that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes, and are not to be construed as limiting the present invention, and the specific meaning of the terms may be understood by those skilled in the art according to specific situations.

FIG. 1 is a block diagram of an equal gain diversity combining architecture; FIG. 2 is a state transition diagram; FIG. 3 is a schematic diagram of de-interleaving; FIG. 4 is a merged schematic.

The method comprises equal gain combination of load data and equal gain combination of frame control number.

First, it should be noted that: the former stage of the module of the receiving end is a mapping module, and each bit data after the PLC system is mapped is represented by 6-bit 2-system soft information, so that the input data s _ data takes 24 bits as a unit. The input data of each clock period represents 24-bit soft information on one subcarrier, and the output data m _ data of the stage module is 6-bit data after deinterleaving, combining and dividing.

Equal gain combining of payload data:

it should be noted that: the load data is divided into load data with one diversity and load data with multiple diversity, and the load data with one diversity is not interleaved at a transmitting end, so that de-interleaving is not needed at a receiving port. The load data which is divided for a plurality of times is internally interleaved and group-shifted by taking an interleaving block as a unit at a sending end, so that at a receiving end, the interleaving needs to be de-interleaved firstly, and then the combined output can be realized.

Due to the difference of diversity modes, the modulation modes are different (BPSK, QPSK, 16QAM), and the corresponding modulation orders are also different (BPSK is 1, QPSK is 2, 16QAM is 4), that is, 24-bit data and s _ data (representing data soft information on one subcarrier) input in each clock cycle, if the modulation mode is BPSK, only [5:0] is valid soft information data, and the high bits are all 0. If the modulation mode is QPSK, only [5:0] and [11:6] are the effective data of soft information, and the high bits are all 0. If the modulation mode 16QAM, all the [23:0] are valid soft information data.

And (3) equal gain combination of load data:

s1: instantiating two single-port RAMs with the depth of 51 and the width of 24 as load input RAMs of a ping-pong structure, instantiating 4 double-port RAMs with the depth of 2500 and the width of 10 as output RAMs of load data: outbuf1, outbuf2, outbuf3, outbuf 4.

S2: setting the initial state of the state machine to be an IDLE state, judging according to the diversity mode when the integral enable signal en is received and the input load soft information is valid, namely S _ valid is 1, if the diversity mode is one time, the state machine enters a copy one entry state (the state is the input combination state of the load data of the diversity time), and jumping to the step S3; if it is multiple times of diversity, the state machine enters the payloaduputdata state (the state is the state of inputting, deinterleaving, and combining the multiple times of diversity payload data) and jumps to step S4.

S3: the open input circuit block, en _ input, is 1 and the open merge circuit block, en _ add, is 1. The input circuit calculates the input data write address adrone (the input address is 0-TotalCarrierNum-1), wherein TotalCarrierNum is the number of data subcarriers which are copied in a diversity mode, the parameter is given by a control module where a state machine is located, the input data and the corresponding input data write address are sent to a merging circuit, and the step S6 is skipped.

S4: the open input circuit, en _ input, is 1, the open merge circuit, en _ add, is 1, and the open de-interleave circuit, en _ depth, is 1. The input circuit writes input data into load data input RAM of a ping-pong structure, and the de-interleaving circuit gives a de-interleaving address: deiterinaddr, deiteroutaddr, the state machine control circuit gives the depacket shift address deiterstartaddr. How these three addresses are generated and described in detail after the end of the step.

S5: and the load data input RAM reads data pointer _ data according to the DeinterInaddr, beats the data by one beat, delays the data by one clock period and inputs the data to the merging circuit.

S6: the output memory RAM write address OutWriteAddr and the merged read address addr are given in the merge circuit. The generation and specification of these two addresses is described in detail after the end of the steps.

S7: when the diversity number counter is one, namely cnt _ CopyNum is 1, the load output storage RAM writes load data according to OutWriteAddr, when the diversity number counter is more than one, the load output storage RAM reads the combined data add _ data according to AddReadAddr and adds the combined data add _ data with the load data, and then writes the combined data into the load output storage RAM.

S8: the state machine enters the OUTPUT state. And turning off the input circuit and the merging circuit, namely en _ add is 0, en _ input is 0, turning on the output circuit, namely en _ output is 1, sequentially reading out the data of the load output storage RAM by the output circuit, and dividing the data by the copy times to output the data as m _ data.

S9: and turning off the output circuit, namely en _ output is equal to 0, and the state machine control circuit is in an IDLE state and waits for the arrival of the next frame data.

S10: when the next frame data is valid, the process returns to step S2.

And equal gain combination of frame control data:

s1: two dual-port RAMs with a depth of 256 and a width of 14 are exemplified as frame-controlled storage RAMs: frame _ addr _ i, frame _ addr _ q, width 14 to ensure no overflow during merging, and to give an initial value of all 0.

S2: setting the initial state of the state machine to be an IDLE state, when receiving an overall enable signal en and inputting i paths and q paths of frame control soft information, namely s _ valid is 1, the state machine enters an FCINPUTADD state, opening an input circuit module, namely en _ input is 1, and opening a merging circuit, namely en _ add is 1.

S3: the input circuit adds one to each clock cycle according to the carrier offset required by the standard to generate a write address corresponding to each bit of soft information.

S4: the data tail of the two paths of input circuits i and q are supplemented with 1 with 4bit wide, and the two paths of data frame _ data _ i and frame _ data _ q and the two paths of corresponding addresses of i and q, namely frame _ addr _ i and frame _ addr _ q, are sent to a merging circuit.

S5, the merging circuit stores RAM from frame control according to frame _ addr _ i and frame _ addr _ q: and reading two paths of data add _ data _ i and add _ data _ q to be added from fcoutbuf _ i and fcoutbuf _ q, correspondingly adding the two paths of data add _ data _ i and add _ data _ q to the frame _ data _ i and frame _ data _ q, and writing the two paths of data add _ data _ i and add _ data _ q into the frame control RAM according to the addresses of the frame _ addr _ i and frame _ addr _ q. The lower 4 bits of the generated data after the addition are the copy times of each bit of the i path and the q path.

S6: the state machine enters the OUTPUT state. Turning off the input circuit and the merging circuit, namely en _ add is 0, en _ input is 0, turning on the output circuit, namely en _ output is 1, giving two 0-255 reading addresses by the output circuit, namely when the output is effective, the address of the first clock cycle is 0, the address of the second clock cycle is 1, and so on, until the 256 clock cycle is 255, and transmitting the address to the frame control storage RAM.

S7: the frame control memory RAM reads out the data outdata _ i, outdata _ q in accordance with the read address of S3.

S8: the output circuit defines the data obtained by adding the outdata _ i and the outdata _ q as frameouttmp, and calculates frameouttmp [13:4]/frameouttmp [3:0] as the output m _ data of the partial set combining module.

S9: when the output circuit is turned off, that is, en _ output is 0, the state machine control circuit is in an IDLE state after the output of the frame control merging data is finished once, and waits for the arrival of the next frame data. And (4) frame control storage RAM: fcoutbuf _ i, fcoutbuf _ q write all 0 data again.

S10: when the next frame data is valid, the process returns to step S2.

Finally, the above embodiments are only intended to illustrate the technical solutions of the present invention and not to limit the present invention, and although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions, and all of them should be covered by the claims of the present invention.

Claims (7)

1. A realization method for equal gain combination of a PLC system receiving end based on FPGA is characterized in that: the method comprises equal gain combination of load data and equal gain combination of frame control number;

the equal gain combination of the load data specifically comprises:

s11: instantiating two single-port RAMs with the depth of 51 and the width of 24 as load input RAMs of a ping-pong structure, instantiating 4 double-port RAMs with the depth of 2500 and the width of 10 as output RAMs of load data: outbuf1, outbuf2, outbuf3, outbuf 4;

s12: setting the initial state of the state machine to be an IDLE state, judging according to a diversity mode when receiving an integral enabling signal en and the input load soft information is valid, namely S _ valid is 1, if the diversity mode is a single diversity, entering the state of copy entry, wherein the state is the input combination state of the load data of the single diversity, and jumping to a step S13; if the diversity is multiple times, the state machine enters a PAYLOADPUTDORENTERADD state, the state is the input of the diversity multiple load data, the interleaving is removed, the state is combined, and the step S14 is skipped;

s13: opening an input circuit module, namely en _ input is 1, and opening a merging circuit, namely en _ add is 1; the input circuit calculates an input data writing address adrone, the input address is 0-TotalCarrierNum-1, wherein TotalCarrierNum is the number of data subcarriers which are copied in a diversity mode once, the parameter is given by a control module where a state machine is located, input data and the corresponding input data writing address are sent to a merging circuit, and the step S16 is skipped;

s14: opening an input circuit, namely en _ input is 1, opening a merging circuit, namely en _ add is 1, and opening a de-interleaving circuit, namely en _ depth is 1; the input circuit writes input data into load data input RAM of a ping-pong structure, and the de-interleaving circuit gives a de-interleaving address: DeinterInAdddr, DeinterOutAddr, state machine control circuit gives the address DeinterStartAdddr of depacketizing shift;

s15: the load data input RAM reads data pointer _ data according to the DeinterInaddr, beats the data by one beat, delays one clock period and inputs the data to the merging circuit;

s16: the write address OutWriteAddr and the merged read address AddReadAddr of the output storage RAM are given in a merging circuit;

s17: when the diversity number counter is one, namely cnt _ CopyNum is 1, the load output storage RAM writes load data according to OutWriteAddr, and when the diversity number counter is more than one, the load output storage RAM reads the combined data add _ data according to AddReadAddr and adds the combined data add _ data with the load data, and then writes the combined data into the load output storage RAM;

s18: the state machine enters an OUTPUT state; turning off the input circuit and the merging circuit, namely en _ add is 0, en _ input is 0, turning on the output circuit, namely en _ output is 1, sequentially reading out data of a load output storage RAM by the output circuit, and dividing the data by the number of times of copying to output the data as m _ data;

s19: closing the output circuit, namely en _ output is 0, and the state machine control circuit is in an IDLE state and waits for the arrival of the next frame data;

s110: when the next frame data is valid, go back to step S12;

the equal gain combination of the frame control number specifically comprises:

s21: two dual-port RAMs with a depth of 256 and a width of 14 are exemplified as frame-controlled storage RAMs: the width of the frame _ addr _ i and the frame _ addr _ q is 14, so that the frame _ addr _ i and the frame _ addr _ q cannot overflow during combination, and the initial values are all 0;

s22: setting the initial state of a state machine to be an IDLE state, when receiving an integral enable signal en and inputting i paths and q paths of frame control soft information, namely s _ valid is 1, the state machine enters an FCINPUTADD state, an input circuit module is opened, namely en _ input is 1, and a merging circuit is opened, namely en _ add is 1;

s23: the input circuit adds one to each clock period according to the carrier wave offset required by the standard to generate a write address corresponding to each bit of soft information;

s24: the tail of the data of the two paths of the input circuits i and q is supplemented with 1 with the bit width of 4 bits, and the two paths of data frame _ data _ i and frame _ data _ q and the two paths of corresponding addresses of the i and q, namely frame _ addr _ i and frame _ addr _ q, are sent to a merging circuit;

s25: the merging circuit stores the RAM from the frame control according to frame _ addr _ i, frame _ addr _ q: reading two paths of data add _ data _ i and add _ data _ q to be added from fcoutbuf _ i and fcoutbuf _ q, correspondingly adding the two paths of data add _ data _ i and add _ data _ q with frame _ data _ i and frame _ data _ q, and writing the two paths of data add _ data _ i and add _ data _ q into a frame control RAM according to the addresses of frame _ addr _ i and frame _ addr _ q; the lower 4 bits of the data generated after the addition are the copying times of each bit of the data of the i path and the q path;

s26: the state machine enters an OUTPUT state; closing the input circuit and the merging circuit, namely en _ add is 0, en _ input is 0, opening the output circuit, namely en _ output is 1, giving two 0-255 reading addresses by the output circuit, namely when the output is effective, the address of the first clock cycle is 0, the address of the second clock cycle is 1, and so on, until the 256 clock cycle is 255, and transmitting the address to the frame control storage RAM;

s27: reading out data outdata _ i and outdata _ q by the frame control storage RAM according to the read address of S3;

s28: defining data obtained by adding the outdata _ i and the outdata _ q in the output circuit as frameouttmp, and calculating frameouttmp [13:4]/frameouttmp [3:0] as output m _ data of the partial set combining module;

s29: turning off the output circuit, namely en _ output is 0, finishing the output of the frame control merging data for one time, and waiting for the arrival of the next frame data when the state machine control circuit is in an IDLE state; and (4) frame control storage RAM: fcoutbuf _ i, fcoutbuf _ q write all 0 data again;

s210: when the next frame data is valid, the process returns to step S22.

2. The method for realizing equal gain combination of the receiving end of the PLC system based on the FPGA according to claim 1, characterized in that: the output RAM as the load data is specifically:

if the modulation order is 1, only the soft information corresponding to 1bit data is valid in each clock cycle, firstly writing the input data s _ data [5:0] into outbuf1, writing outbuf1 with the full depth 2500, writing the input data s _ data [5:0] into outbuf2, writing outbuf2 with the full depth 2500, writing outbuf3, writing outbuf3 with the full depth 2500, and writing outbuf 4; if the modulation order is 2, since 12-bit soft information corresponding to 2-bit data is valid in each clock cycle, data is written into outbuf1 and outbuf2 at the same time, and input data s _ data [5:0] is written into outbuf1 and s _ data [11:6] write to outbuf2, outbuf1, outbuf2 simultaneously after full depth 2500, write to outbuf3, outbuf4 simultaneously; if the modulation order is 4, every clock cycle, there is 24-bit soft information corresponding to 4-bit data valid, and simultaneously, the write operation is performed for outbuf1, outbuf2, outbuf3 and outbuf 4: s _ data [5:0] writes outbuf1, s _ data [11:6] writes outbuf2, s _ data [17:12] writes outbuf3, and s _ data [13:18] writes outbuf 4.

3. The method for realizing equal gain combination of the FPGA-based PLC system receiving end and the like according to claim 2, is characterized in that: the read-write address of the write operation is given by:

when the modulation mode is BPSK:

diversity is carried out for multiple times: when DeinterOutAddr + DeinterStartAddr <2500, AddReadAddr ═ OutWriteAddr ═ DeinterOutAddr + DeinterStartAddr;

when 2500< DeinterOutAddr + DeinterStartAddr <5000, AddReadAddr ═ OutWriteAddr ═ DeinterOutAddr + DeinterStartAddr-2500;

(ii) AddReadAddr ═ OutWriteAddr ═ DeinterOutAddr + DeinterStartAddr-5000 when 5000< DeinterOutAddr + DeinterStartAddr < 7500;

(ii) when DeinterOutAddr + DeinterStartAddr >7500, AddReadAddr ═ OutWriteAddr ═ DeinterOutAddr + DeinterStartAddr-7500;

standard definition, diversity does not have BPSK modulation mode at one time;

when the modulation mode is QPSK:

diversity is carried out for multiple times: when DeinterOutAddr + DeinterStartAddr <2500, AddReadAddr ═ OutWriteAddr ═ DeinterOutAddr + DeinterStartAddr;

when 2500< DeinterOutAddr + DeinterStartAddr <5000, addreareaddr ═ OutWriteAddr ═ DeinterOutAddr + DeinterStartAddr-2500;

diversity once: when the addrone is <2500, AddReadAddr ═ addr; AddReadAddr outpr addr-2500 when 2500< addrone < 5000;

when the modulation mode is 16 QAM:

diversity is carried out for multiple times: AddReadAddr ═ OutWriteAddr ═ deinteroutunaddr + DeinterStartAddr;

diversity once: AddReadAddr ═ addr ═ addre.

4. The method for realizing equal gain combination of the FPGA-based PLC system receiving end and the like according to claim 3, characterized in that: the DeinterStartAddr is as follows: the PLC standard stipulates that each diversity of a sending end circularly moves right by taking a group as a unit, how many groups to circularly move right are stored in a register in a state machine control module of a receiving end, the circular right movement of the DeinterStartAddr by taking an interleaving block as a unit is realized by a counter, and a right movement parameter is updated when one diversity is finished so as to facilitate the generation of the DeinterStartAddr of the next diversity.

5. The method for realizing equal gain combination of the FPGA-based PLC system receiving end and the like according to claim 4, is characterized in that: the PLC standard stipulates that the subcarrier number address of each interleaving block of a sending end is written in 0-CarrierNum-1 according to a row and read out according to a column according to a step length, and then the read-out address is circularly shifted to the right; in the de-interleaving implementation at the receiving end, two addresses are generated: DeinterInAddr uses a counter to realize circulation left shift, and DeinterOutAddr uses a row counter and a column counter to realize writing in by rows and reading out by columns.

6. The method for realizing equal gain combination of the FPGA-based PLC system receiving end and the like according to claim 5, wherein the method comprises the following steps: and the receiving end reads data from the load input RAM of the load ping-pong structure according to DeinterInAddr, and writes the data into the load output RAM according to DeinterStartAddr + DeinterOutAddr, thus completing de-interleaving.

7. The method for realizing equal gain combination of the FPGA-based PLC system receiving end and the like according to claim 6, is characterized in that: when equal gain combination of the frame control number is performed, aiming at multi-frame data combination, a frame control storage RAM corresponding to the next frame data: fcoutbuf _ i and fcoutbuf _ q are not all 0, and are merging results of previous frame data, when the output of the frame control merging data of the previous frame is finished, and the merging of the load data of the previous frame is started, the frame control storage RAM is subjected to: fcoutbuf _ i, fcoutbuf _ q write all 0 data again, so this operation does not increase the delay;

reading the data to be added and writing the added data from fcoutbuf _ i and fcoutbuf _ q simultaneously, reading the data at the port a and writing the data at the port b in the same clock cycle, wherein the write address is one clock cycle later than the read address, namely the write address beats one beat in the top-level file;

after the merging, the data outdata _ i and outdata _ q to be output are read out from fcoutbuf _ i and fcoutbuf _ q, and the reading and writing operations are not at the same time.

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