CN116087628B - Measurement method, device and storage medium - Google Patents
Measurement method, device and storage medium Download PDFInfo
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- 238000007493 shaping process Methods 0.000 claims abstract description 74
- 238000007781 pre-processing Methods 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 27
- 238000005259 measurement Methods 0.000 claims description 23
- 238000004590 computer program Methods 0.000 claims description 3
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- 101100021996 Arabidopsis thaliana CYP97C1 gene Proteins 0.000 description 21
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
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- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/005—Time-to-digital converters [TDC]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
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Abstract
The invention discloses a measuring method, a measuring device and a storage medium. The method comprises the steps of respectively inputting a start pulse signal and a stop pulse signal into two paths of pulse shaping circuits for preprocessing to obtain a preprocessed start pulse signal and a preprocessed stop pulse signal; respectively inputting the preprocessed start pulse signal and the preprocessed stop pulse signal into a carry chain of a corresponding preset chip, and measuring to obtain the first time of the time interval between the stop pulse signal and the start pulse signal; determining a second time between the stop pulse signal and the start pulse signal; and calculating according to the first time and the second time to obtain the interval time between the stop pulse signal and the start pulse signal. Therefore, when the pulse interval time of two adjacent stop pulse signals in the stop pulse signals is as low as 5ns, the interval time between the stop pulse signals and the start pulse signals can be measured, and the purpose of simultaneously considering high-precision and low-precision pulse interval time is achieved.
Description
Technical Field
The present disclosure relates to the technical field of digital measurement of time, and in particular, to a measurement method, a device thereof, and a storage medium.
Background
A time-to-digital converter (Time to Digital Converter, TDC) is a circuit for measuring time that converts a continuous time signal into a digital signal, thereby achieving digitization of the time measurement. However, it is difficult to combine high accuracy and low pulse interval time with the current method of measuring time, such as direct counting TDC, capacitor-based charge-discharge method, vernier caliper method, multiphase clock sampling method, and general carry chain method based on field programmable gate array chip (Field Programmable Gate Array, FPGA), and it is difficult to combine high accuracy and low pulse interval time with each other.
Disclosure of Invention
In view of this, the present invention aims to solve, at least to some extent, one of the problems in the related art. To this end, the object of the present application is to provide a measuring method, an apparatus and a storage medium therefor.
The embodiment of the application provides a method for measuring pulse interval time. The measuring method comprises the steps of respectively inputting a start pulse signal and a stop pulse signal into two paths of pulse shaping circuits for preprocessing to obtain the preprocessed start pulse signal and the preprocessed stop pulse signal, wherein the interval time of two adjacent pulses of the stop pulse signal is greater than or equal to 5ns, the preprocessed stop pulse signal is of a fixed pulse width, and the fixed pulse width is greater than the clock period of a system working clock; respectively inputting the preprocessed starting pulse signals and the preprocessed stopping pulse signals into carry chains of corresponding preset chips, and measuring to obtain first time of a time interval between the stopping pulse signals and the starting pulse signals; the system working clock is controlled to send a clock signal to count clock cycles between the stop pulse signal and the start pulse signal while the preprocessed stop pulse signal and the preprocessed start pulse signal are input into a carry chain of a preset chip, and second time between the stop pulse signal and the start pulse signal is determined; and calculating the interval time between the stop pulse signal and the start pulse signal according to the first time and the second time.
In this way, before the start pulse signal and the stop pulse signal enter the carry chain, the start pulse signal is input into one pulse shaping circuit and the stop pulse signal is input into the other pulse shaping circuit for preprocessing, so that the stop pulse signal shaped into a fixed pulse width and the preprocessed start pulse signal are obtained, and then the shaped stop pulse signal and the shaped start pulse signal are respectively input into the carry chain of the preset chip to obtain the first time between the stop pulse signal and the start pulse signal, so that the measurement of the interval time between the two pulses of the start pulse signal and the stop pulse signal is realized, and the measurement of the interval time between the stop pulse signal and the start pulse signal can be realized when the pulse interval time between two adjacent stop pulse signals in the stop pulse signal is as low as 5ns, thereby achieving the purpose of simultaneously considering both high precision and low precision pulse interval time.
In some embodiments, the inputting the start pulse signal and the stop pulse signal to two pulse shaping circuits respectively to perform preprocessing, where obtaining the preprocessed start pulse signal and the preprocessed stop pulse signal includes shaping the start pulse signal according to the pulse shaping circuit to obtain the preprocessed start pulse signal; and shaping the stop pulse signal according to the pulse shaping circuit to obtain the stop pulse signal with the fixed pulse width.
In this way, the measurement method of the present application obtains the start pulse signal and the stop pulse signal with a fixed pulse width after preprocessing by inputting the start pulse signal and the stop pulse signal to the pulse shaping circuit to perform pulse shaping.
In some embodiments, the pulse shaping circuit includes a first trigger, a plurality of lookup tables, and a second trigger, where the first trigger and the second trigger are connected through a first path lookup table and a second path lookup table, the first path lookup table includes a plurality of lookup tables in cascade multiple stages, and the second path lookup table includes a plurality of lookup tables in multiple stages.
Therefore, the first trigger of the pulse shaping circuit is connected with the second trigger through the first path lookup table and the second path lookup table, so that the pulse shaping circuit can shape the pulse of the starting pulse signal and the stopping pulse signal.
In some embodiments, the shaping the stop pulse signal according to the pulse shaping circuit, to obtain the stop pulse signal with the fixed pulse width includes inputting the stop pulse signal into the first trigger; and determining the fixed pulse width of the stop pulse signal according to the first trigger, the first path lookup table, the second path lookup table and the second trigger.
In this way, the measuring method of the present application realizes pulse shaping of the stop pulse signal by inputting the stop pulse signal into the first trigger, and then through the first trigger, the first path lookup table, the second path lookup table and the second trigger, thereby realizing the stop pulse signal with a fixed pulse width.
In some embodiments, a first lookup table of the first path lookup table is connected with an output pin of the first trigger, a last lookup table of the first path lookup table is connected with a clock pin of the second trigger, one end of the second path lookup table is connected with the output pin of the first trigger, and the other end of the second path lookup table is connected with a reset pin of the second trigger; the determining the fixed pulse width of the start pulse signal or the stop pulse signal according to the first trigger, the first path lookup table, the second path lookup table and the second trigger comprises adding the input path delay of the clock pin of the second trigger and the path delay from the output pin of the second trigger to the reset pin of the first trigger, and calculating to obtain the fixed pulse width of the start pulse signal or the stop pulse signal.
In this way, the pulse shaping circuit of the measuring method delays the stop pulse signal by cascading a plurality of lookup tables of multiple stages and adds the delay from the output pin of the second trigger to the reset pin of the first trigger, so that the stop pulse signal with fixed pulse width is obtained.
In some embodiments, after the pretreated start pulse signal and the stop pulse signal are respectively input into the carry chains of the corresponding preset chips and the first time of the time interval between the stop pulse signal and the start pulse signal is measured, the measurement method includes generating a first enabling signal while inputting the pretreated stop pulse signal and the start pulse signal into the carry chains of the preset chips, triggering a clock signal to control a third trigger, a fourth trigger and a configurable module in the preset chips to start working, and controlling the configurable module to output the first enabling signal through an and gate; and controlling and outputting first time between the stop pulse signal and the start pulse signal calculated by the carry chain according to the first enabling signal.
In this way, the measurement method controls the output of the first time between the stop pulse signal and the start pulse signal calculated by the carry chain through the first enabling signal, so that the first time is obtained.
In some embodiments, the controlling the system operation clock to send out a clock signal to count clock cycles between the stop pulse signal and the start pulse signal while inputting the pre-processed stop pulse signal and the start pulse signal into a carry chain of a preset chip, determining the second time between the stop pulse signal and the start pulse signal includes controlling to send out a clock signal to control counting of clock cycles between the stop pulse signal and the start pulse signal through a third flip-flop and a fourth flip-flop while inputting the pre-processed stop pulse signal and the start pulse signal into the carry chain of the preset chip, so as to determine the number of clock cycles between the stop pulse signal and the start pulse signal; a second time between the stop pulse signal and the start pulse signal is determined from the number of clock cycles and the clock cycles between the stop pulse signal and the start pulse signal.
In this way, the measurement method of the present application counts the clock periods between the stop pulse signal and the start pulse signal by controlling the third flip-flop and the fourth flip-flop through the clock signal to obtain the number of clock periods between the stop pulse signal and the start pulse signal, and determines the second time by multiplying the number of clock periods by the clock period.
In some embodiments, the measurement method includes generating a second enable signal while inputting the pre-processed stop pulse signal and the start pulse signal into a carry chain of a preset chip, triggering the clock signal to control a third flip-flop, a fourth flip-flop and the configurable module in the preset chip to start working, and controlling the configurable module to output the second enable signal through an and gate; and controlling and outputting a second time between the stop pulse signal and the start pulse signal according to the second enabling signal.
In this way, the measurement method of the present application controls the output of the second time between the stop pulse signal and the start pulse signal through the second enable signal, thereby obtaining the second time.
The application also provides a device for measuring the pulse interval time. The measuring device comprises a preprocessing module, a measuring module, a determining module and a calculating module. The preprocessing module is used for inputting a start pulse signal and a stop pulse signal into the two paths of pulse shaping circuits respectively for preprocessing to obtain the preprocessed start pulse signal and the preprocessed stop pulse signal, wherein the interval time of two adjacent pulses of the stop pulse signal is more than or equal to 5ns, the preprocessed stop pulse signal is of a fixed pulse width, and the fixed pulse width is larger than the clock period of a system working clock; the measurement module is used for respectively inputting the preprocessed starting pulse signals and the preprocessed stopping pulse signals into carry chains of corresponding preset chips, and measuring to obtain first time of a time interval between the stopping pulse signals and the starting pulse signals; the determining module is used for controlling the system working clock to send out a clock signal to count clock cycles between the stop pulse signal and the start pulse signal while inputting the preprocessed stop pulse signal and the preprocessed start pulse signal into a carry chain of a preset chip, and determining second time between the stop pulse signal and the start pulse signal; the calculation module is used for calculating and obtaining the interval time between the stop pulse signal and the start pulse signal according to the first time and the second time.
Therefore, before the start pulse signal and the stop pulse signal enter the carry chain, the measurement device inputs the start pulse signal into one pulse shaping circuit and inputs the stop pulse signal into the other pulse shaping circuit to be preprocessed, so that the stop pulse signal shaped into a fixed pulse width and the preprocessed start pulse signal are obtained, and then the shaped stop pulse signal and the shaped start pulse signal are respectively input into the carry chain of the preset chip to obtain the first time between the stop pulse signal and the start pulse signal, so that the measurement of the interval time between the two pulses of the start pulse signal and the stop pulse signal is realized, the measurement of the interval time between the stop pulse signal and the start pulse signal can be realized when the pulse interval time between two adjacent stop pulse signals in the stop pulse signal is as low as 5ns, and the aim of simultaneously considering the high precision and the low precision pulse interval time is fulfilled.
The present application also provides a computer-readable storage medium. The computer readable storage medium stores a computer program which, when executed by one or more processors, implements the measurement method described in the above embodiments.
In this way, before the start pulse signal and the stop pulse signal enter the carry chain, the start pulse signal is input into one pulse shaping circuit and the stop pulse signal is input into the other pulse shaping circuit for preprocessing, so that the stop pulse signal shaped into a fixed pulse width and the preprocessed start pulse signal are obtained, and then the shaped stop pulse signal and the shaped start pulse signal are respectively input into the carry chain of the preset chip to obtain the first time between the stop pulse signal and the start pulse signal, so that the measurement of the interval time between the two pulses of the start pulse signal and the stop pulse signal is realized, and the measurement of the interval time between the stop pulse signal and the start pulse signal is considered when the pulse interval time between two adjacent stop pulse signals in the stop pulse signal is as low as 5ns, thereby achieving the purpose of simultaneously high-precision and low-precision pulse interval time.
Drawings
The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:
FIG. 1 is one of the flow diagrams of a measurement method in certain embodiments of the present application;
FIG. 2 is a second schematic diagram of a measurement device in some embodiments of the present application;
FIG. 3 is a third flow chart of a measurement method in some embodiments of the present application;
FIG. 4 is a timing diagram of the operation of a pulse shaping circuit of the measurement method in certain embodiments of the present application;
FIG. 5 is a schematic diagram of measurement times of a measurement method in certain embodiments of the present application;
FIG. 6 is a fourth flow chart of a measurement method in some embodiments of the present application;
FIG. 7 is a fifth flow chart of a measurement method in some embodiments of the present application;
FIG. 8 is a flow chart of a measurement method in certain embodiments of the present application;
FIG. 9 is a seventh flow chart of a measurement method in some embodiments of the present application;
FIG. 10 is a flow diagram eighth of a measurement method in some embodiments of the present application;
FIG. 11 is a nine of a flow chart of a measurement method in certain embodiments of the present application;
fig. 12 is a flow diagram of a measurement method in some embodiments of the present application.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.
In the description of the present application, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or an implicit indication of the number of technical features being indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present application, the meaning of "a plurality" is two or more, unless specifically defined otherwise.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; may be mechanically connected, may be electrically connected, or may be in communication with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.
The following disclosure provides many different embodiments or examples for implementing different structures of the present application. In order to simplify the disclosure of the present application, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. Furthermore, the present application may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not in themselves indicate the relationship between the various embodiments and/or arrangements discussed.
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.
Referring to fig. 1 to 5, the present application provides a method for measuring pulse interval time. The measuring method comprises the following steps:
01: the start pulse signal and the stop pulse signal are respectively input into the two paths of pulse shaping circuits 30 for pretreatment, and the start pulse signal and the stop pulse signal after pretreatment are obtained, wherein the interval time of two adjacent pulses of the stop pulse signal is more than or equal to 5ns, the stop pulse signal after pretreatment is of a fixed pulse width, and the fixed pulse width is larger than the clock period of a system working clock.
02: respectively inputting the preprocessed start pulse signal and the preprocessed stop pulse signal into a carry chain MUXCY of a corresponding preset chip 40, and measuring to obtain the first time of the time interval between the stop pulse signal and the start pulse signal;
03: while inputting the preprocessed stop pulse signal and start pulse signal into the carry chain MUXCY of the preset chip 40, controlling the system working clock to send out a clock signal to count the clock period between the stop pulse signal and the start pulse signal, and determining a second time between the stop pulse signal and the start pulse signal;
04: and calculating according to the first time and the second time to obtain the interval time between the stop pulse signal and the start pulse signal.
Referring to fig. 2, the present application also provides a measuring device 10. The measuring device 10 comprises a preprocessing module 11, a measuring module 12, a determining module 13 and a calculating module 14.
It will be appreciated that since the pulse shaping circuit 30 has the same pulse shaping principle for the start pulse signal and the stop pulse signal, only one pulse shaping circuit 30 is drawn for illustration, and the pulse shaping circuit 30 is shown in fig. 3. The start pulse signal may be input to one pulse shaping circuit 30 of the two pulse shaping circuits 30, and the stop pulse signal may be input to the other pulse shaping circuit 30, so as to obtain a preprocessed start pulse signal and a stop pulse signal with a fixed pulse width.
Specifically, referring to fig. 3, sgn in may represent a start pulse signal or a stop pulse signal. Taking Sgn in as an example, the stop pulse signal is first input into the pulse shaping circuit 30 through the clock pin C of the first flip-flop DFF1, and the Sgn is pulse-shaped by the pulse shaping circuit 30 to obtain a stop pulse signal of a fixed pulse width, i.e., a pulse waveform of the plus as shown in fig. 4.
Referring to fig. 4, C0 represents a pulse waveform of a clock pin C of the first flip-flop DFF1, Q0 represents a pulse waveform of an output pin Q of the first flip-flop DFF1, clr0 represents a pulse waveform of a reset pin clr of the first flip-flop DFF1, C1 represents a pulse waveform of a clock pin C of the second flip-flop DFF2, Q1 represents a pulse waveform of an output pin Q of the second flip-flop DFF2, clr1 represents a pulse waveform of a reset pin clr of the second flip-flop DFF2, and pluse represents a pulse waveform of a stop pulse signal of a fixed pulse width obtained after preprocessing.
As can be seen from fig. 4, no matter how wide the pulse width of the input Sgn is, the pulse width of the pluse obtained after preprocessing is fixed, that is, the pulse width of the start pulse signal or the stop pulse signal obtained after preprocessing is fixed. In addition, the time represents the pulse waveform of the clock period of the system operation clock, and as can be seen from fig. 4, the pulse width of the plus is larger than the clock period of the time, i.e., the fixed pulse width of the start pulse signal or the stop pulse signal is larger than the clock period of the system operation clock.
Then, the obtained pre-processed start pulse signal and stop pulse signal with fixed pulse width are respectively input into the carry chain MUXCY of the corresponding preset chip 40, and the system working clock is controlled to send out the clock signal clk (as shown in fig. 3), so that the input start pulse signal and stop pulse signal with fixed pulse width are respectively measured through the carry chain MUXCY, and the first time of the time interval between the stop pulse signal and the start pulse signal is obtained, which may also be called as fine time.
Referring to fig. 5, the first time t1 and the first time t2 are smaller than the clock period Tc of a system operation clock, tc is 2ns, i.e. the ranges of the first time t1 and the first time t2 are [0,2ns ], so that the fixed pulse width of the stop pulse signal is set to be larger than the clock period of the system operation clock, for example, the fixed pulse width is set to be 2.2ns, which can ensure that the first time t1 and the first time t2 of the time interval between the stop pulse signal and the start pulse signal with the adjacent two pulse intervals of 5ns can be accurately calculated.
In addition, while the preprocessed stop pulse signal and start pulse signal are input into the carry chain MUXCY of the preset chip 40, the control system operating clock issues a clock signal to count clock cycles between the stop pulse signal and the start pulse signal, and determines a second time between the stop pulse signal and the start pulse signal. That is, the clock period between the stop pulse signal and the start pulse signal is counted by the system operation clock, thereby determining a second time (NTc shown in fig. 5) between the stop pulse signal and the start pulse signal, which may also be referred to as a coarse time.
Finally, the first time t1 is subtracted from the first time t2 and added to the second time NTc to obtain the interval time (Ti shown in fig. 5) between the stop pulse signal and the start pulse signal.
In this way, before the start pulse signal and the stop pulse signal enter the carry chain MUXCY, the start pulse signal is input to one pulse shaping circuit 30 and the stop pulse signal is input to the other pulse shaping circuit 30 for preprocessing, so that the stop pulse signal shaped into a fixed pulse width and the preprocessed start pulse signal are obtained, and then the shaped stop pulse signal and the shaped start pulse signal are input to the carry chain MUXCY of the preset chip 40 to obtain the first time between the stop pulse signal and the start pulse signal, so that the measurement of the interval time between two pulses of the start pulse signal and the stop pulse signal is realized, and the measurement of the interval time between the stop pulse signal and the start pulse signal can be realized when the pulse interval time between two adjacent stop pulse signals in the stop pulse signal is as low as 5ns, thereby achieving the purpose of simultaneously giving consideration to the pulse interval time with high precision and low precision.
Referring to fig. 6, in some embodiments, step 01 includes:
011: shaping the start pulse signal according to the pulse shaping circuit 30 to obtain a preprocessed start pulse signal;
012: the stop pulse signal is shaped by the pulse shaping circuit 30 to obtain a stop pulse signal having a fixed pulse width.
Referring to fig. 2, steps 011 and 012 may be implemented by the preprocessing module 11. That is, the preprocessing module 11 is configured to perform shaping processing on the start pulse signal according to the pulse shaping circuit 30, so as to obtain a preprocessed start pulse signal; the stop pulse signal is shaped by the pulse shaping circuit 30 to obtain a stop pulse signal having a fixed pulse width.
As shown in fig. 3, the pulse shaping circuit 30 includes a first flip-flop DFF1, a plurality of look-up tables LUT, and a second flip-flop DFF2. It should be noted that the carry chain MUXCY may be hundreds, and is only schematically shown in fig. 3. Each of the plurality of look-up tables LUT may be delayed by 0.3ns. For example, since the delay between adjacent two configurable module CLBs is about 300ps, a separate one of the look-up tables LUT may be provided in a separate one of the configurable module CLBs in the pulse shaping circuit 30.
Specifically, the start pulse signal is input to the clock pin C of the first flip-flop DFF1, then the start pulse signal is input to the plurality of look-up tables LUT through the output pin Q of the first flip-flop DFF1, the start pulse signal is shaped through the plurality of look-up tables LUT and the second flip-flop DFF2, and finally the shaped start pulse signal is output to the reset pin clr of the first flip-flop DFF1 through the output pin Q of the second flip-flop DFF2, thereby obtaining the preprocessed start pulse signal.
The method comprises the steps of inputting a stop pulse signal to a clock pin C of a first trigger DFF1, inputting the stop pulse signal to a plurality of lookup tables LUTs through an output pin Q of the first trigger DFF1, shaping the stop pulse signal through the plurality of lookup tables LUTs and a second trigger DFF2, and finally outputting the shaped stop pulse signal to a reset pin clr of the first trigger DFF1 through an output pin Q of the second trigger DFF2, so that the stop pulse signal with a fixed pulse width is obtained.
In this way, the measurement method of the present application obtains the start pulse signal and the stop pulse signal with a fixed pulse width after the preprocessing by inputting the start pulse signal and the stop pulse signal to the pulse shaping circuit 30, respectively, and performing pulse shaping.
Further, in some embodiments, as shown in fig. 3, the pulse shaping circuit 30 includes a first flip-flop DFF1, a plurality of look-up tables LUT, and a second flip-flop DFF2, where the first flip-flop DFF1 and the second flip-flop DFF2 are respectively connected through a first path look-up table LUT1 and a second path look-up table LUT2, the first path look-up table LUT1 includes a plurality of look-up tables LUT of cascade stages, and the second path look-up table LUT2 includes a plurality of look-up tables LUT of multistage stages.
Wherein, as shown in fig. 3, the first path lookup table LUT1 comprises 7 lookup table LUTs of cascade multilevel, and the second path lookup table LUT2 comprises 4 lookup table LUTs of cascade multilevel. It will be appreciated that since each look-up table LUT may be delayed by about 0.3ns, i.e. when the start pulse signal or the stop pulse signal passes through the first look-up table LUT1, a delay of about 2.1ns for the start pulse signal or the stop pulse signal may be achieved.
Specifically, the output pin Q of the first flip-flop DFF1 is connected to the input pin I0 of the first path look-up table LUT1 (a plurality of look-up tables LUT of cascade stages) and the input pin I0 of the second path look-up table LUT2, the output pin O of the first path look-up table LUT1 is connected to the clock pin C of the second flip-flop DFF2, the output pin O of the second path look-up table LUT1 is connected to the reset pin clr of the second flip-flop DFF2, and the output pin Q of the second flip-flop DFF2 is connected to the reset pin clr of the first flip-flop DFF 1.
When the start pulse signal or the stop pulse signal is input to the first path lookup table LUT1 of the pulse shaping pulse circuit 30 and then input to the second flip-flop DFF2 through the first path lookup table LUT1, and output to the first flip-flop DFF1 through the second flip-flop DFF2, the fixed pulse width of the start pulse signal and the stop pulse signal can be made about 2.2ns.
In this way, the first flip-flop DFF1 of the pulse shaping circuit 30 of the present application is connected to the second flip-flop DFF2 through the first path lookup table LUT1 and the second path lookup table LUT2, respectively, so as to implement pulse shaping of the stop pulse signal by the pulse shaping circuit 30.
In addition, when the Sgn in inputs the stop pulse signal, the output pin Q of the second flip-flop DFF2 outputs the signal "1", the stop pulse signal reaches the second flip-flop DFF2 after passing through the first path of the lookup table LUT1 to become the stop pulse signal with the fixed pulse width, at this time, the output pin Q of the second flip-flop DFF2 outputs the signal "1", and outputs the stop pulse signal with the fixed pulse width to the reset pin clr of the first flip-flop DFF1, so that the first flip-flop DFF1 is reset and returns to the initial state. At this time, the output pin Q of the first flip-flop DFF1 outputs a signal "0" and outputs a stop pulse signal with a fixed pulse width to the carry chain MUXCY.
When the first flip-flop DFF1 is reset and restored to the initial state, the output pin Q of the first flip-flop DFF1 outputs a signal "0", outputs the signal "0" to the second path lookup table LUT2, delays the signal by the 4 lookup table LUTs provided in the second path lookup table LUT2 and inverts the signal "0" to the signal "1" by the last lookup table LUT, so that the second flip-flop DFF2 is reset and restored to the initial state. The delay time of the 4 lookup tables LUT may be 1.2ns, 1.25ns, or other values. It should be noted that, the delay of the second path lookup table LUT2 is smaller than the delay of the first path lookup table LUT 1. In this way, the reset is performed after the reset time delay of the second trigger DFF2 is realized through the second loop lookup table LUT2, so that the stability from the input pin of the second trigger DFF2 to the reset pin of the first trigger DFF1 is improved.
Referring to fig. 7, in some embodiments, step 01 includes:
013: inputting a stop pulse signal into the first flip-flop DFF 1;
014: the fixed pulse width of the stop pulse signal is determined according to the first flip-flop DFF1, the first way look-up table LUT1, the second way look-up table LUT2 and the second flip-flop DFF 2.
Referring to fig. 2, steps 013 and 014 may be implemented by the preprocessing module 11. That is, the preprocessing module 11 is used to input a stop pulse signal into the first flip-flop DFF 1; the fixed pulse width of the stop pulse signal is determined according to the first flip-flop DFF1, the first way look-up table LUT1, the second way look-up table LUT2 and the second flip-flop DFF 2.
For example, as shown in fig. 3, a stop pulse signal is first input from the clock pin C of the first flip-flop DFF1, then the stop pulse signal is respectively output to the input pin I0 of the first path lookup table LUT1 and the input pin I0 of the second path lookup table LUT2 through the output pin Q of the first flip-flop DFF1, then the stop pulse signal is output to the clock pin C of the second flip-flop DFF2 through the output pin O of the first path lookup table LUT1, and finally the stop pulse signal is output to the reset pin clr of the first flip-flop DFF1 through the output pin Q of the second flip-flop DFF2, thereby determining a fixed pulse width of the stop pulse signal.
In this way, the pulse shaping circuit 30 of the present application implements pulse shaping of the stop pulse signal by inputting the stop pulse signal into the first flip-flop DFF1, and then implementing the stop pulse signal with a fixed pulse width that may be about 2.2ns through the first flip-flop DFF1, the first way look-up table LUT1, the second way look-up table LUT2, and the second flip-flop DFF 2.
Referring to fig. 8, in some embodiments, step 014 includes:
0141: and adding the input path delay of the clock pin C of the second trigger DFF2 and the path delay from the output pin Q of the second trigger DFF2 to the reset pin clr of the first trigger DFF1, and calculating to obtain the fixed pulse width of the start pulse signal or the stop pulse signal.
Referring to fig. 2, step 0141 may be implemented by computing module 14. That is, the calculating module 14 is configured to add the input path delay of the clock pin C of the second flip-flop DFF2 to the path delay from the output pin Q of the second flip-flop DFF2 to the reset pin clr of the first flip-flop DFF1, so as to calculate a fixed pulse width of the start pulse signal or the stop pulse signal.
Referring to fig. 3, a first look-up table LUT of the first path look-up table LUT1 is connected to an output pin Q of the first flip-flop DFF1, a last look-up table LUT of the first path look-up table LUT1 is connected to a clock pin C of the second flip-flop DFF2, one end of the second path look-up table LUT2 is connected to the output pin Q of the first flip-flop DFF1, and the other end of the second path look-up table LUT2 is connected to a reset pin clr of the second flip-flop DFF 2.
For example, as shown in fig. 3, taking the signal input to the first flip-flop DFF1 as the stop pulse signal, the fixed pulse width of the stop pulse signal is equal to the path delay of the stop pulse signal from the output pin Q of the first flip-flop DFF1 to the clock pin C of the second flip-flop DFF2 through the plurality of look-up tables LUT1 of the first path look-up table LUT1 plus the path delay of the stop pulse signal from the output pin Q of the second flip-flop DFF2 to the reset pin clr of the first flip-flop DFF 1. If the path delay of the stop pulse signal from the output pin Q of the first flip-flop DFF1 to the clock pin C of the second flip-flop DFF2 through the plurality of look-up tables LUT of the first path look-up table LUT1 is about 2.1ns, the path delay of the stop pulse signal from the output pin Q of the second flip-flop DFF2 to the reset pin clr of the first flip-flop DFF1 is about 0.1ns, and the fixed pulse width of the stop pulse signal is about 2.2ns.
In this way, the pulse shaping circuit 30 of the measuring method of the present application delays the stop pulse signal by cascading a plurality of lookup tables LUT of a plurality of stages and adds the delay from the output pin Q of the second flip-flop DFF2 to the reset pin clr of the first flip-flop DFF1, thereby obtaining the stop pulse signal of a fixed pulse width.
Referring to fig. 9, in some embodiments, after the preprocessed start pulse signal and stop pulse signal are respectively input into the carry chain MUXCY of the corresponding preset chip 40, the measurement method includes:
05: generating a first enabling signal counten while inputting the preprocessed stop pulse signal and the preprocessed start pulse signal into a carry chain MUXCY of the preset chip 40, triggering a clock signal to control a third trigger, a fourth trigger and a configurable module in the preset chip 40 to start working, and controlling the configurable module to output the first enabling signal counten through an AND gate;
06: and controlling and outputting a first time between the stop pulse signal and the start pulse signal calculated by the carry chain MUXCY according to the first enable signal coarse count en.
Referring to fig. 2, steps 05 and 06 may be implemented by the determining module 13. That is, the determining module 13 is configured to generate a first enable signal count en while inputting the preprocessed stop pulse signal AND start pulse signal into the carry chain MUXCY of the preset chip 40, trigger a clock signal to control the third flip-flop DFF3, the fourth flip-flop DFF4, AND the configurable module 50 in the preset chip 40 to start operation, AND control the configurable module 50 to output the first enable signal count en through the AND gate AND; and controlling and outputting a first time between the stop pulse signal and the start pulse signal calculated by the carry chain MUXCY according to the first enable signal coarse count en.
As shown in fig. 3, the carry chain MUXCY of the preset chip 40 may be plural, and the plural carry chains MUXCY are disposed in the preset chip 40 in a step-by-step serial manner. The input pin D of the third flip-flop DFF3 is connected to the output pin O of the carry-in chain MUXCY, the output pin Q of the third flip-flop DFF3 is connected to the input pin D of the fourth flip-flop DFF4 AND the first input pin I0 of the AND-gate AND, respectively, the output pin Q of the fourth flip-flop DFF4 is connected to the second input pin I1 of the AND-gate AND, AND the output pin O of the AND-gate AND is connected to the configurable module 50. The configurable module 50 comprises a fifth flip-flop DFF5 AND a sixth flip-flop DFF6, the output pin O of the AND gate AND being connected to the input pin D of the fifth flip-flop DFF5 AND the input pin D of the sixth flip-flop DFF6, respectively. The fifth flip-flop DFF5 is for outputting a first enable signal coarse count en. The sixth flip-flop DFF6 is for outputting the second enable signal aden.
Specifically, when the stop pulse signal AND the start pulse signal are preprocessed by the pulse shaping circuit 30 to obtain a stop pulse signal AND a preprocessed start pulse signal with a fixed pulse width, the stop pulse signal AND the preprocessed start pulse signal with a fixed pulse width are input to the carry chain MUXCY of the preset chip 40 through the output pin Q of the first flip-flop DFF1, AND the first enable signal count en is generated AND output to the third flip-flop DFF3 through the output pin O of the first carry chain MUXCY, AND at this time, the clock signal is triggered to control the third flip-flop DFF3, the fourth flip-flop DFF4 AND the configurable module 50 to start working, AND the fifth flip-flop DFF5 of the configurable module 50 is controlled by the AND gate AND to output the first enable signal count en. The carry chain MUXCY is then controlled by the fifth flip-flop DFF5 of the configurable module 50 to output a first enable signal coarse count en to output a first time between the calculated stop pulse signal and the start pulse signal.
In this way, the measurement method of the present application controls the output of the first time between the stop pulse signal and the start pulse signal calculated by the carry chain MUXCY through the first enable signal coarse count en, so as to obtain the first time.
Referring to fig. 10, in some embodiments, step 03 includes:
031: controlling the emission of a clock signal clk while inputting the preprocessed stop pulse signal and start pulse signal into the carry chain MUXCY of the preset chip 40, to control counting of clock cycles between the stop pulse signal and the start pulse signal through the third flip-flop DFF3 and the fourth flip-flop DFF4, so as to determine the number of clock cycles between the stop pulse signal and the start pulse signal;
032: the second time between the stop pulse signal and the start pulse signal is determined according to the number of clock cycles and the clock cycles between the stop pulse signal and the start pulse signal.
Referring to fig. 2, step 031 and step 032 may be implemented by the determining module 13. That is, the determining module 13 is configured to control the issuing clock signal clk to control counting of clock cycles between the stopping pulse signal and the starting pulse signal through the third flip-flop DFF3 and the fourth flip-flop DFF4 while inputting the stopping pulse signal and the starting pulse signal after the preprocessing into the carry chain MUXCY of the preset chip 40, so as to determine the number of clock cycles between the stopping pulse signal and the starting pulse signal; the second time between the stop pulse signal and the start pulse signal is determined according to the number of clock cycles and the clock cycles between the stop pulse signal and the start pulse signal.
Specifically, in the case where the stop pulse signal and the start pulse signal are preprocessed by the pulse shaping circuit 30 to obtain the stop pulse signal and the preprocessed start pulse signal of a fixed pulse width, the clock signal clk is issued and input through the clock pin of the third flip-flop DFF3 while the stop pulse signal and the preprocessed start pulse signal of a fixed pulse width are input into the carry chain MUXCY through the output pin Q of the first flip-flop DFF1, so as to control the third flip-flop DFF3 and the fourth flip-flop DFF4 to count the clock cycles between the stop pulse signal and the start pulse signal, thereby determining the number of clock cycles between the stop pulse signal and the start pulse signal. The second time between the stop pulse signal and the start pulse signal is then obtained by multiplying the number of clock cycles between the stop pulse signal and the start pulse signal by the clock cycles.
In this way, the measurement method of the present application controls the third flip-flop DFF3 and the fourth flip-flop DFF4 to count the clock cycles between the stop pulse signal and the start pulse signal by the clock signal clk to obtain the number of clock cycles between the stop pulse signal and the start pulse signal, and determines the second time by multiplying the number of clock cycles by the clock cycles.
Referring to fig. 11, in some embodiments, the measurement method includes:
07: generating a second enable signal aden while inputting the preprocessed stop pulse signal AND start pulse signal into the carry chain MUXCY of the preset chip 40, triggering the clock signal clk to control the third flip-flop DFF3, the fourth flip-flop DFF4 AND the configurable module 50 in the preset chip 40 to start working, AND controlling the configurable module 50 to output the second enable signal aden through the AND gate AND;
08: and controlling and outputting a second time between the stop pulse signal and the start pulse signal according to the second enable signal aden.
Referring to fig. 2, steps 07 and 08 may be implemented by the determining module 13. That is, the determining module 13 is configured to generate the second enable signal aden while inputting the preprocessed stop pulse signal AND start pulse signal into the carry chain MUXCY of the preset chip 40, trigger the clock signal clk to control the third flip-flop DFF3, the fourth flip-flop DFF4, AND the configurable module 50 in the preset chip 40 to start operation, AND control the configurable module 50 to output the second enable signal aden through the AND gate AND; and controlling and outputting a second time between the stop pulse signal and the start pulse signal according to the second enable signal aden.
Specifically, in the case where the stop pulse signal AND the start pulse signal are preprocessed by the pulse shaping circuit 30 to obtain the stop pulse signal AND the preprocessed start pulse signal with a fixed pulse width, the stop pulse signal AND the preprocessed start pulse signal with a fixed pulse width are input to the carry chain MUXCY of the preset chip 40 through the output pin Q of the first flip-flop DFF1, AND the second enable signal aden is generated AND output to the third flip-flop DFF3 through the output pin O of the first carry chain MUXCY, AND at this time, the clock signal clk is triggered to control the third flip-flop DFF3, the fourth flip-flop DFF4, AND the configurable module 50 to start operating, AND the sixth flip-flop DFF6 of the configurable module 50 is controlled by the AND gate AND to output the second enable signal aden. The output of the second time between the stop pulse signal and the start pulse signal is then controlled according to the second enable signal adeen output by the sixth flip-flop DFF6 of the configurable module 50.
In this way, the measurement method of the present application controls the output of the second time between the stop pulse signal and the start pulse signal by the second enable signal aden, thereby obtaining the second time.
Referring to fig. 12, in some embodiments, step 04 includes:
041: and adding the second time and the first time to obtain the interval time between the stop pulse signal and the start pulse signal.
Referring to FIG. 2, step 041 may be implemented by computing module 14. That is, the calculating module 14 is configured to add the second time and the first time to obtain an interval time between the stop pulse signal and the start pulse signal.
For example, in connection with fig. 5, the interval time between the stop pulse signal and the start pulse signal is equal to the second time (e.g., NTc of fig. 5) plus the first time (e.g., t1 and t2 of fig. 5), i.e., ti= NTc +t1-t2.
In this way, the measuring method of the present application obtains the time interval between the stop pulse signal and the start pulse signal by adding the first time and the second time.
The measuring device 10 in the embodiment of the present application is identical to the description of the above embodiment, and will not be described again here.
In this way, before the start pulse signal and the stop pulse signal enter the carry chain MUXCY, the measurement device 10 of the present application performs preprocessing by inputting the start pulse signal to one pulse shaping circuit 30 and inputting the stop pulse signal to the other pulse shaping circuit 30, thereby obtaining the stop pulse signal shaped into a fixed pulse width and the preprocessed start pulse signal, and then inputting the shaped stop pulse signal and the shaped start pulse signal to the carry chain MUXCY of the preset chip 40, thereby obtaining the first time between the stop pulse signal and the start pulse signal, and realizing the measurement of the interval time between two pulses of the start pulse signal and the stop pulse signal, and when the pulse interval time between two adjacent stop pulse signals in the stop pulse signal is as low as 5ns, the measurement of the interval time between the stop pulse signal and the start pulse signal can be realized, and the purpose of simultaneously considering both high precision and low precision pulse interval time is achieved.
The present application also provides a computer-readable storage medium. The computer readable storage medium stores a computer program, which when executed by one or more processors, implements the measurement method in the above embodiments, and is not described herein for brevity.
In this way, before the start pulse signal and the stop pulse signal enter the carry chain MUXCY, the start pulse signal is input to one path of pulse shaping circuit 30 and the stop pulse signal is input to the other path of pulse shaping circuit 30 for preprocessing, so that the stop pulse signal and the preprocessed start pulse signal which are shaped into the fixed pulse width are obtained, then the shaped stop pulse signal and the shaped start pulse signal are input to the carry chain MUXCY of the preset chip 40 to obtain the first time between the stop pulse signal and the start pulse signal, so that the shaped stop pulse signal and the preprocessed start pulse signal are obtained, then the shaped stop pulse signal and the shaped start pulse signal are input to the carry chain MUXCY of the preset chip 40 to obtain the first time between the stop pulse signal and the start pulse signal, and accordingly, the measurement of the interval time between two adjacent stop pulse signals in the stop pulse signal is realized, and the measurement of the interval time between the stop pulse signal and the start pulse signal is low to 5ns, and the time interval between the stop pulse signal and the start pulse signal is measured with high precision.
The foregoing examples represent only a few embodiments of the present application, which are described in more detail and are not thereby to be construed as limiting the scope of the present application. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (8)
1. A method of measuring pulse interval time, the method comprising:
respectively inputting a start pulse signal and a stop pulse signal into two paths of pulse shaping circuits for preprocessing to obtain the preprocessed start pulse signal and the preprocessed stop pulse signal, wherein the interval time of two adjacent pulses of the stop pulse signal is more than or equal to 5ns, and the preprocessed stop pulse signal is of a fixed pulse width which is more than the clock period of a system working clock; the pulse shaping circuit comprises a first trigger, a plurality of lookup tables and a second trigger, wherein the first trigger and the second trigger are respectively connected through a first path of lookup table and a second path of lookup table, the first path of lookup table comprises a plurality of lookup tables of cascade multistage, and the second path of lookup table comprises a plurality of lookup tables of cascade multistage; preprocessing the stop pulse signal according to the pulse shaping circuit, wherein obtaining the stop pulse signal with the fixed pulse width comprises inputting the stop pulse signal into the first trigger; determining a fixed pulse width of the stop pulse signal according to the first trigger, the first path lookup table, the second path lookup table and the second trigger;
Respectively inputting the preprocessed starting pulse signals and the preprocessed stopping pulse signals into carry chains of corresponding preset chips, and measuring to obtain first time of a time interval between the stopping pulse signals and the starting pulse signals;
the system working clock is controlled to send a clock signal to count clock cycles between the stop pulse signal and the start pulse signal while the preprocessed stop pulse signal and the preprocessed start pulse signal are input into a carry chain of a preset chip, and second time between the stop pulse signal and the start pulse signal is determined;
and calculating the interval time between the stop pulse signal and the start pulse signal according to the first time and the second time.
2. The method for measuring pulse interval time according to claim 1, wherein the step of inputting the start pulse signal and the stop pulse signal to the two pulse shaping circuits respectively to perform preprocessing, and obtaining the start pulse signal and the stop pulse signal after preprocessing includes:
shaping the starting pulse signal according to the pulse shaping circuit to obtain a preprocessed starting pulse signal; and
And shaping the stop pulse signal according to the pulse shaping circuit to obtain the stop pulse signal with the fixed pulse width.
3. The method for measuring pulse interval time according to claim 1, wherein a first lookup table of the first path lookup table is connected with an output pin of the first trigger, a last lookup table of the first path lookup table is connected with a clock pin of the second trigger, one end of the second path lookup table is connected with the output pin of the first trigger, and the other end of the second path lookup table is connected with a reset pin of the second trigger;
the determining the fixed pulse width of the stop pulse signal according to the first trigger, the first way lookup table, the second way lookup table and the second trigger comprises:
and adding the input path delay of the clock pin of the second trigger and the path delay from the output pin of the second trigger to the reset pin of the first trigger, and calculating to obtain the fixed pulse width of the stop pulse signal.
4. The method according to claim 1, wherein after the first time of the time interval between the stop pulse signal and the start pulse signal is measured after the pre-processed start pulse signal and the stop pulse signal are respectively input into a carry chain of a corresponding preset chip, the method comprises:
Generating a first enabling signal while inputting the preprocessed stopping pulse signal and the starting pulse signal into a carry chain of a preset chip, triggering a clock signal to control a third trigger, a fourth trigger and a configurable module in the preset chip to start working, and controlling the configurable module to output the first enabling signal through an AND gate;
and controlling and outputting first time between the stop pulse signal and the start pulse signal calculated by the carry chain according to the first enabling signal.
5. The method according to claim 4, wherein the step of controlling the system operation clock to send out a clock signal to count clock cycles between the stop pulse signal and the start pulse signal while inputting the stop pulse signal and the start pulse signal after the preprocessing into a carry chain of a preset chip, and determining a second time between the stop pulse signal and the start pulse signal, comprises:
controlling to send a clock signal to control counting of clock cycles between the stop pulse signal and the start pulse signal through a third trigger and a fourth trigger while inputting the preprocessed stop pulse signal and the start pulse signal into a carry chain of a preset chip so as to determine the number of the clock cycles between the stop pulse signal and the start pulse signal;
A second time between the stop pulse signal and the start pulse signal is determined from the number of clock cycles and the clock cycles between the stop pulse signal and the start pulse signal.
6. The method for measuring pulse interval time according to claim 5, wherein the method for measuring pulse interval time comprises:
generating a second enabling signal while inputting the preprocessed stopping pulse signal and the starting pulse signal into a carry chain of a preset chip, triggering the clock signal to control a third trigger, a fourth trigger and the configurable module in the preset chip to start working, and controlling the configurable module to output the second enabling signal through an AND gate;
and controlling and outputting a second time between the stop pulse signal and the start pulse signal according to the second enabling signal.
7. A pulse interval measurement device, comprising:
the pretreatment module is used for respectively inputting a start pulse signal and a stop pulse signal into the two pulse shaping circuits to carry out pretreatment to obtain the pretreated start pulse signal and the pretreated stop pulse signal, wherein the interval time of two adjacent pulses of the stop pulse signal is more than or equal to 5ns, the pretreated stop pulse signal is of a fixed pulse width, and the fixed pulse width is more than the clock period of a system working clock; the pulse shaping circuit comprises a first trigger, a plurality of lookup tables and a second trigger, wherein the first trigger and the second trigger are respectively connected through a first path of lookup table and a second path of lookup table, the first path of lookup table comprises a plurality of lookup tables of cascade multistage, and the second path of lookup table comprises a plurality of lookup tables of cascade multistage; preprocessing the stop pulse signal according to the pulse shaping circuit, wherein obtaining the stop pulse signal with the fixed pulse width comprises inputting the stop pulse signal into the first trigger; determining a fixed pulse width of the stop pulse signal according to the first trigger, the first path lookup table, the second path lookup table and the second trigger;
The measurement module is used for respectively inputting the preprocessed starting pulse signals and the preprocessed stopping pulse signals into carry chains of corresponding preset chips, and measuring to obtain first time of a time interval between the stopping pulse signals and the starting pulse signals;
the determining module is used for controlling the system working clock to send out a clock signal to count clock cycles between the stop pulse signal and the start pulse signal while inputting the preprocessed stop pulse signal and the preprocessed start pulse signal into a carry chain of a preset chip, and determining second time between the stop pulse signal and the start pulse signal;
and the calculating module is used for calculating the interval time between the stop pulse signal and the start pulse signal according to the first time and the second time.
8. A computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program which, when executed by one or more processors, implements the method of measuring pulse interval time according to any of claims 1-6.
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