CN116073855B - BL-DSSS signal code tracking method based on frequency domain matched filtering and time delay adjustment - Google Patents

Abstract

According to the BL-DSSS signal code tracking method based on frequency domain matched filtering and time delay adjustment, the computational complexity of an original code tracking method is obviously reduced through the matched filtering and time delay adjustment realized by the frequency domain, and the application range of the BL-DSSS system is expanded; meanwhile, the frequency domain delay adjustment method has higher equivalent order and higher precision than the common interpolation method adopted by the delay phase-locked loop, thereby bringing smaller tracking error.

Description

BL-DSSS signal code tracking method based on frequency domain matched filtering and time delay adjustment

Technical Field

The invention belongs to the technical field of communication, and particularly relates to a BL-DSSS signal code tracking method based on frequency domain matched filtering and time delay adjustment.

Background

Direct sequence spread spectrum systems (DSSS) have found widespread use in the fields of communications, navigation, radar, etc. The traditional direct sequence spread spectrum system generally adopts a rectangular waveform, has lower frequency spectrum efficiency and smaller sideband attenuation, simultaneously generates interference to signals of other frequency bands, and gradually cannot meet the requirements of modern communication and measurement systems. The band-limited direct sequence spread spectrum (BL-DSSS) system adopts band-limited waveforms such as raised cosine waveforms and gauss to replace rectangular waveforms, can realize higher frequency spectrum efficiency and sideband attenuation, improves communication data rate and measurement accuracy, reduces interference to signals of other frequency bands, and is widely studied.

Code synchronization is an important component of a BL-DSSS signal receiver, including code acquisition and code tracking. The code capturing process is to reduce the time delay difference between the local signal and the received signal to be within one chip interval through a signal estimation technology, and is a rough estimation process for decoration, and initialization parameters are provided for follow-up code tracking. The code tracking is a feedback control process, and the time delay is mainly carried out through a loop, and the main functions of the code tracking are as follows: firstly, on the basis of code capture, the time delay is further accurately estimated, so that the time delay difference between a local signal and a received signal is as small as possible, the signal-to-noise ratio of the input signal of the subsequent data detection is improved, and the error rate is reduced; and secondly, continuously tracking the time delay of the received signal, so that the time delay of the local signal and the time delay of the received signal are consistent under a dynamic condition.

The existing code tracking method for BL-DSSS signals mainly adopts a delay phase-locked loop principle, as shown in fig. 1, specifically, the time delay difference between a local signal and a received signal is estimated through different error discrimination methods after matched filtering is completed in a time domain, and the received signal is interpolated through a designed loop filter control interpolator, so that the time delay adjustment of the received signal is completed.

(1) The existing code tracking method has higher calculation complexity

The existing BL-DSSS signal code tracking method based on the delay phase-locked loop principle is high in impurity degree, and mainly has two reasons: firstly, the receiving signal needs to complete matched filtering in the time domain, which is a digital convolution process, and higher computational complexity is needed when the receiving signal is implemented in a digital circuit; and secondly, the delay error adjustment of the received signal is realized through an interpolator, which also brings higher computational complexity.

(2) The existing code tracking method has poor time delay adjustment precision

The existing time delay adjustment method is realized through different interpolators, and in order to relatively reduce complexity, the order of the interpolators is low, such as a cubic interpolator or a polynomial interpolator. The low-order interpolator is used for adjusting the time delay of a received signal, and a large precision error is inevitably brought.

Disclosure of Invention

In view of the above, the present invention aims to provide a BL-DSSS signal code tracking method based on frequency domain matched filtering and time delay adjustment, which reduces the computational complexity and can well solve the problem of poor precision caused by the traditional interpolator.

A BL-DSSS signal code tracking method comprising:

let the signal received by the receiver be sampled and then expressed as r _n The method comprises the steps of carrying out a first treatment on the surface of the In the matched filtering process, the received signal r _n Firstly, performing integer time delay adjustment, then multiplying the integer time delay adjustment by a frequency domain fractional time delay filter after matched filtering realized by FFT, and finally obtaining a signal y after time delay adjustment and matched filtering after IFFT calculation _n ；

Will signal y _n Through error identification and loop filtering, the method enters a matched filtering and time delay adjusting process, and the like, so that the loop tracking of BL-DSSS signal codes is realized.

Preferably, in the matched filtering process, a frequency domain form of the matched filter is:

H _MF,k ＝FFT _2M [h _MF,n ]

wherein ,

n represents the sampling point sequence number, T _s Representing the sampling period, p _R (nT _s ) Representing the time domain response of the matched filter, M is the number of points of the matched filter.

Preferably, the frequency domain fractional delay filter is:

wherein i represents the number of times sequence of loop tracking and the time delay estimated valueRepresenting the delay estimate for the ith loop tracking.

Preferably, the integer delay adjustment is performed on the received signal r _n Integer left shift in time domainIs realized by the method; />Representing the delay estimate.

Preferably, the delay estimation value is updated in the loop filtering part according to the following formula:

wherein ,delay estimation value h representing ith+1st loop tracking _i Representing the loop filter, G being the gain factor of the loop filter part, z _i Representing the output of the error discrimination section.

Preferably, the error discrimination section is implemented by lead and lag error discrimination.

The invention has the following beneficial effects:

according to the BL-DSSS signal code tracking method based on frequency domain matched filtering and time delay adjustment, the computational complexity of an original code tracking method is obviously reduced through the matched filtering and time delay adjustment realized by the frequency domain, and the application range of the BL-DSSS system is expanded; meanwhile, the frequency domain delay adjustment method has higher equivalent order and higher precision than the common interpolation method adopted by the delay phase-locked loop, thereby bringing smaller tracking error.

Drawings

FIG. 1 is a block diagram of a code tracking method based on a delay locked loop in the prior art;

FIG. 2 is a schematic block diagram of a code tracking method based on frequency domain matched filtering and delay adjustment according to the present invention;

FIGS. 3 (a) and 3 (b) are respectively the code tracking cases under the conditions that the loop bandwidth is 10Hz and 100 Hz;

fig. 4 (a) and fig. 4 (b) are respectively the code tracking cases under the conditions of signal-to-noise ratio snr= -25dB and 5dB of the input signal;

fig. 5 is a steady state error variance comparison result.

Detailed Description

The invention will now be described in detail by way of example with reference to the accompanying drawings.

1. Signal model

The transmitting end of the invention adopts root raised cosine signal waveform, and the data symbol adopts BPSK modulation mode, the transmitting signal of the transmitting end can be expressed as:

wherein ,a_i In the form of a data symbol,representing a rounding down operation, c _m = ±1 is a spreading code sequence, p _T (t) is a pulse waveform of the radiation signal, in the present invention, a root raised cosine signal waveform, whose frequency response is +.> wherein P_N (f) Is the frequency response of a raised cosine filter. In addition, T _c For the chip period, T is the spreading code period, n=t/T _c Is the spread spectrum gain. When the above formula is used to represent the transmitted signal, since x (t) is a stationary followerThe power spectral density of s (t) can be expressed as |P _T (f)| ² /T _c The average power of the modulated signal x (t) is 1, due to the nature of the raised cosine waveform. Considering the effects of received signal delay and white gaussian noise, a signal received by a receiving end can be expressed as:

where θ is the unsynchronized carrier phase, subject to a uniform distribution over [ -pi, pi); τ is the pseudo code delay remaining after capture, satisfying |τ| is less than or equal to T _c The method comprises the steps of carrying out a first treatment on the surface of the w (t) is Gaussian white noise signal with power spectral density N ₀/P, wherein N₀ The power spectrum density of noise is single-sided, and P is the power of the received intermediate frequency signal. The invention sets a sampling period T _s ＝T _c And/2, n represents the sampling point sequence number, the sampled signal can be expressed as:

2. BL-DSSS signal code tracking method based on frequency domain matched filtering and time delay adjustment

The code tracking method based on frequency domain matched filtering and time delay adjustment provided by the invention is shown in fig. 2, and can be divided into a matched filtering part, an error discriminating part, a loop filtering part and a time delay adjustment part as a whole.

Because the tracking method is a negative feedback process, it is first assumed that the received signal has undergone sampling and delay adjustment, where in the ith loop update, the delay estimate is assumed to beInitial value of delay adjustment in loop update 0 th timeDelay error after delay adjustment>

(1) In the matched filtering part, the received signal r after sampling and time delay adjustment _n First, matched filtering is completed in the frequency domain, specifically by using FFT through overlap-and-hold method. The time domain response of a matched filter is known as p _R (t) its frequency domain response isThen a discrete form matched filter suitable for overlap preservation with a number of significant points M can be constructed as:

its frequency domain form can be expressed as:

H _MF,k ＝FFT _2M [h _MF,n ] (5)

the received signal is multiplied by the matched filter in the frequency domain to complete the function of the matched filter, after the IFFT, the signal without aliasing at the middle M point is output, and after serial-parallel conversion, the signal after matched filtering can be obtained, which can be expressed as:

wherein, P (T) is raised cosine waveform, and its frequency domain response is P (f) =t _c P _N (f)，Has a power spectral density of N ₀ P _N (f)/P。

(2) The error discrimination section follows, and the principle of lead-lag error discrimination is adopted. Since the sampling rate is twice the symbol rate, the output signal y can be filtered by matching _n The extraction is carried out for 2 times,to obtain the middle branch data y _2n And leading branch data y _2n+1 . The middle branch data is used as the output of code tracking and can be used as the input signal for subsequent carrier recovery and data detection after despreading. The leading branch data is delayed by one sampling point to obtain the lagging branch data y _2n-1 . And after despreading and accumulating the data of the leading branch and the lagging branch, obtaining the error discrimination output. Wherein the output of the advanced leg can be expressed as:

in the above formula, the first term is a useful signal; the second term is self-noise, denoted v _S,i It is under steady state conditions, i.e. when% _i |<<T _c When it is equal to 0 in mean, the variance approaches 0; the third term is white noise term, and the equivalent noise at the baseband is 1/T _s Under the condition v _W,i The digital power spectral density of (2) is:

in the above formula, ω represents a digital angular frequency;

likewise, the output of the lagging leg can be expressed as:

x _L,i ＝e ^jθ a _i p(-T _s -ε _i )+v _S,i +v _W,i (9)

the mean and variance of the advanced leg output can be expressed as:

E(x _E,i )＝e ^jθ a _i p(T _s -ε _i )

in the derivation of the above equation, the frequency domain response characteristic of the raised cosine filter is used. The mean and variance of the output of the lagging branch are the same as those of the leading branch, and the two can be considered to be mutually independent, and the mean and variance of the lagging branch can be obtained as follows:

the invention adopts the principle of lead and lag to carry out error discrimination and utilizes the output x of the lead branch _E,i The square of (1) minus the lagging leg output x _L,i The square of (c) yields the output of the error discrimination expressed as:

z _i ＝|x _E,i | ² -|x _L,i | ² (12)

because of x _E,i And x _L,i Are complex Gaussian random processes whose mean and variance are given in equation (10), and whose absolute value is calculated by removing carrier phase e from the signal ^jθ And data symbol a _i Is a function of (a) and (b). Thus, |x _E,i | ² and |x_L,i | ² Obeying a non-central chi-square distribution of both degrees of freedom, so that the complex random process z can be found _i The mean and variance of (c) are respectively:

E(z _i )＝var(x _E,i )+|E(x _E,i )| ² -var(x _L,i )-|E(x _L,i )| ²

＝p ² (T _s -ε _i )-p ² (-T _s -ε _i )

when under stable tracking conditions, |ε _i |<<T _c Thus z _i The variance of (c) can be reduced to:

(3) In the loop filter part, due toFor aliasing in the frequency domain, the output z of the error discrimination section _i May be approximated as a white process. At the same time combine z _i Mean and variance of (2), complex stochastic process z _i Can be approximated as:

wherein The digital power spectral density of (2) can be expressed as:

to properly design the loop gain factor, the error output z needs to be calculated _i The expression for the raised cosine filter p (t) is known as:

where α is the roll-off factor of the waveform. At the same time let z _i Is a signal term of (2):

η(ε _i )＝p ² (T _s -ε _i )-p ² (-T _s -ε _i ) (18)

the slope of the above equation at zero is found to be:

then z _i The approximation under steady state conditions can be expressed as:

thus, the gain factor g=1/a of the loop can be made, and the dynamic differential variance of the loop can be written as:

in the above, h _i Representing a loop filter;

in order to meet the high-precision fractional delay adjustment and reduce errors caused by the difference between cyclic delay adjustment and linear delay adjustment at the error adjustment part, the invention adopts a delay adjustment method of separating integer delay from fractional delay. In the integer time delay adjusting part, the invention adopts the integer left shift of the received signal in the time domainIs realized by the method; in the fractional delay adjustment part, a frequency domain fractional delay filter is adopted to realize the method, and when the normalized delay estimation valueThe frequency domain fractional delay filter implementing the left delay can be expressed as:

received signal r _n Through integer delay adjustment, FFT, and frequency domain fractional delay filter H _FD,k (d _i ) The multiplication completes the fractional delay adjustment of the received signal.

3. Computational complexity analysis and simulation verification

(1) Computational complexity analysis

The computational complexity of the traditional delay phase-locked loop and the proposed method is analyzed, and the complex multiplication times required by unit code period average are adopted for quantization, wherein a loop filtering part, an error identification part and a time delay adjustment part with more complex multiplication times are mainly considered. The number of multiplications required for each part is shown in table 1:

table 1 required computational complexity

Wherein M is the number of points of the matched filter, N _IT The number of points of the interpolator, and N is the length of the spreading code. Let the spreading code length n=1023 when typical parameter settings are used, N when a conventional delay locked loop uses a cubic interpolator _IT Effective length m=16 of the matched filter. At this time, the complex multiplication number required by the traditional delay locked loop is 42966, and the complex multiplication number required by the frequency domain matching filtering and time delay adjusting method of the invention is 30690, and only 0.7143 of the calculated amount of the traditional method is required. In order to improve the precision of the delay adjustment of the traditional delay locked loop, when the interpolator of the traditional delay locked loop adopts the same number of points as the proposed method, namely N _IT =2m, the proposed method only requires 0.3061 of the traditional method calculation. It can be found that the proposed code tracking method has significantly reduced computational complexity compared to the conventional delay locked loop method.

(2) Simulation verification

The invention performs simulation verification on the traditional phase-locked loop method (figure 1) and the frequency domain matched filtering and time delay adjusting method provided by the invention. The pseudo code period is set to t=1 ms, the pseudo code length is set to n=1023, the pseudo code type is Gold code, and the sampling rate is set to 1/T _s =2.046 MHz, i.e. two samples averaged over one chip period, the length of the matched filter is set to m=16. In the delay phase-locked loop method, a cubic interpolation method is adopted for delay adjustment.

First, the same pseudo code time delay is set to 0.25T _s Compared with the same input signal at signal to noise ratio snr=10lg (PT _s /N ₀ ) = -10dB, B under different loop bandwidth conditions _L =10hz and B _L As a result of code tracking at 100Hz, as shown in fig. 3 (a) and 3 (b), under the condition of small loop bandwidth, the steady-state noise of both tracking methods is smaller, but the setup time of the steady state is longer; under the condition of large loop bandwidth, the two tracking methods are stableThe state set-up time is relatively small, but the steady state noise is relatively large. Meanwhile, as can be seen from fig. 3 (a), the frequency domain matched filtering and delay adjustment method has smaller steady-state error than the delay locked loop method, presumably because the delay locked loop method uses a cubic interpolator to perform delay adjustment, which is equivalent to a 4-point FIR filter, while the delay adjustment method of the frequency domain method is equivalent to a 2 m=32-point filter, and the accuracy is significantly higher.

Then, the time delay of 0.25T at the same pseudo code is compared _s The same loop bandwidth B _L Code tracking conditions of two methods under conditions of 10Hz and different input signal-to-noise ratio snr= -25dB and snr=5 dB, the results are shown in fig. 4 (a) and fig. 4 (b). Both tracking methods have a larger steady state error at low signal to noise ratios of the input signal, while the steady state error is smaller at high signal to noise ratios. In fig. 4 (b) on the right, it can be seen that the delay locked loop method has a large error due to the cubic interpolation method.

The variance of the delay error at steady state tracking was then compared for both methods. A Monte Carlo simulation method is adopted, and the normalized display is carried out by using a sampling period. 9 different signal-to-noise ratios of the input signals are set, and under the condition of each signal-to-noise ratio, the stable tracking variance of 200 times of 1s data is averaged to obtain a variance value of a steady state error. The results obtained are shown in FIG. 5.

As can be seen from the figure, the steady-state tracking error variances of the two tracking methods are not greatly different, but the errors of the frequency domain matching filtering and the time delay adjusting method are relatively smaller, and the guess is that the delay adjusting is carried out by adopting a cubic interpolation method by adopting a delay phase-locked loop method, and the additional variances are brought due to inaccurate time delay adjustment caused by the smaller number of points of the filter.

In summary, the above embodiments are only preferred embodiments of the present invention, and are not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (5)

1. A BL-DSSS signal code tracking method, comprising:

let the signal received by the receiver be sampled and then expressed as r _n The method comprises the steps of carrying out a first treatment on the surface of the In the matched filtering process, the received signal r _n Firstly, performing integer time delay adjustment, then multiplying the integer time delay adjustment by a frequency domain fractional time delay filter after matched filtering realized by FFT, and finally obtaining a signal y after time delay adjustment and matched filtering after IFFT calculation _n ；

Will signal y _n Performing error identification and loop filtering, then entering a matched filtering and time delay adjusting process, and the like, so as to realize the loop tracking of BL-DSSS signal codes;

the error identification method comprises the following steps:

by matching the filtered output signal y _n Extracting 2 times to obtain middle branch data y _2n And leading branch data y _2n+1 The method comprises the steps of carrying out a first treatment on the surface of the The middle branch data is used as the output of code tracking and is used as the input signal of subsequent carrier recovery and data detection after despreading; the leading branch data is delayed by one sampling point to obtain the lagging branch data y _2n-1 The method comprises the steps of carrying out a first treatment on the surface of the After despreading and accumulating the data of the leading branch and the lagging branch, obtaining error discrimination output; wherein the output of the advanced branch is expressed as:

in the above formula, i represents the number of times of loop tracking, and the first term is a useful signal; second item v _S,i Is self-noise; third item v _W,i Is a white noise term; n represents the sampling point number, c _n Is a spread code sequence; t (T) _s Representing a sampling period; n is the length of the spreading code; a, a _i Data symbols; θ is the unsynchronized carrier phase; p (t) is a raised cosine waveform; epsilon _i Representing the delay error after delay adjustment;

the output of the hysteresis loop is expressed as:

x _L,i ＝e ^jθ a _i p(-T _s -ε _i )+v _S,i +v _W,i

using the output x of the leading branch _E,i The square of (1) minus the lagging leg output x _L,i The square of (c) yields the output of the error discrimination expressed as:

z _i ＝|x _E,i | ² -|x _L,i | ² (12)。

2. the BL-DSSS signal code tracking method of claim 1 wherein the matched filter used in the matched filtering is in the frequency domain form of:

H _MF,k ＝FFT _2M [h _MF,n ]

wherein ,

n represents the sampling point sequence number, T _s Representing the sampling period, p _R (nT _s ) Representing the time domain response of the matched filter, M is the number of points of the matched filter.

3. The BL-DSSS signal code tracking method of claim 2 wherein the frequency domain fractional delay filter is:

wherein i represents the number of times sequence of loop tracking and normalized time delay estimated value Representing the delay estimate for the ith loop tracking.

4. A BL-DSSS signal code tracking method according to claim 2 or 3, whichCharacterized in that the integer delay adjustment is performed on the received signal r _n Integer left shift in time domainIs realized by the method; />Representing the delay estimate for the ith loop tracking.

5. The BL-DSSS signal code tracking method of claim 4 wherein the delay estimate is updated in the loop filter section according to the following formula:

wherein ,delay estimation value h representing ith+1st loop tracking _i Representing the loop filter, G being the gain factor of the loop filter part, z _i Representing the output of the error discrimination section.