CN116073822A - Gapped clock regeneration circuit and regeneration method - Google Patents

Abstract

The invention discloses a Gapped clock regeneration circuit and a regeneration method, wherein the Gapped clock regeneration circuit comprises: the device comprises a first counting module, a control module, a second counting module, a first digital filter and a clock generation module. According to the Gapped clock regeneration circuit, the first counting module counts the notch clock signals to obtain indication signals representing the completion of the counting period; receiving the indication signal through the control module to generate a control signal; counting the clock signals based on the control signals through a second counting module to obtain count values, and generating a difference value between the count values and a first preset value by the control module; processing the difference value through a first digital filter to obtain a frequency division signal; the clock signal is obtained based on the frequency division signal through the clock generation module, so that the frequency of the clock signal can be quickly converged, and the clock signal with lower jitter performance and higher frequency precision can be obtained.

Description

Gapped clock regeneration circuit and regeneration method

Technical Field

The present invention relates to the field of integrated circuits, and more particularly, to a Gapped clock regeneration circuit and a regeneration method.

Background

The gapped clock is a clock signal with periodic gaps, namely, part of signals are lack compared with the normal clock signal in a certain period, the number and the positions of the gaps are determined, and the non-ideal clock signal with the gaps is regenerated into the normal clock signal with uniform period, namely, the gapped clock regeneration technology.

The conventional gapped clock regeneration circuit has a slow convergence rate of the generation loop, and the jitter performance of the clock signal regenerated after locking is poor.

The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.

Disclosure of Invention

The invention aims to provide a Gapped clock regeneration circuit and a regeneration method, which can improve the convergence speed of clock signal frequency and the jitter performance of a locked clock signal.

To achieve the above object, an embodiment of the present invention provides a Gapped clock regeneration circuit, including: the device comprises a first counting module, a control module, a second counting module, a first digital filter and a clock generation module.

The first counting module is used for periodically counting the notch clock signals to obtain indication signals used for representing the completion of each counting period; the control module is used for receiving the indication signal and adaptively generating a control signal; the second counting module is used for periodically counting the clock signals based on the control signals to obtain count values, and the control module receives the count values and generates difference values of the count values and first preset values; the first digital filter is used for processing the difference value based on the coefficient thereof to obtain a frequency division signal; the clock generation module is used for obtaining a clock signal based on the frequency division signal and feeding the clock signal back to the second counting module.

In one or more embodiments of the present invention, the first counting module includes a first counter, a first register, and a synchronizer, the first counter is connected to the first register, the first counter is connected to the synchronizer, and the synchronizer is connected to the control module.

In one or more embodiments of the invention, the first preset value is configured by a second register.

In one or more embodiments of the invention, the clock generation module includes a voltage controlled oscillator and a digitally controlled oscillator coupled to each other, the first digital filter number being coupled to the digitally controlled oscillator, the digitally controlled oscillator being coupled to the second counting module.

In one or more embodiments of the present invention, the regeneration circuit further includes a phase-locked loop coupled to the first digital filter, the clock generation module, and the second counting module, the clock generation module generating an intermediate clock signal based on an output signal of the phase-locked loop, the phase-locked loop being configured to divide the intermediate clock signal based on the divided signal to generate the clock signal.

In one or more embodiments of the present invention, the phase-locked loop includes a first time-to-digital converter, a phase-frequency detector, a second digital filter, a frequency divider, and a second time-to-digital converter, where the first time-to-digital converter is configured to receive a reference clock signal and is simultaneously connected to the phase-frequency detector, the phase-frequency detector is connected to the second digital filter, the second digital filter is connected to a clock generation module, the clock generation module is connected to the frequency divider, the frequency divider is connected to the second time-to-digital converter and the second counting module, and the first digital filter, and the second time-to-digital converter is connected to the phase-frequency detector.

The invention also discloses a method for regenerating the Gapped clock, which comprises the following steps:

periodically counting the notch clock signals through a first counting module to obtain indication signals used for representing the completion of each counting period;

receiving the indication signal through the control module to adaptively generate a control signal;

periodically counting the clock signals based on the control signals by a second counting module to obtain count values;

receiving the count value and generating a difference value between the count value and a first preset value through a control module;

processing the difference value based on the coefficient thereof by a first digital filter to obtain a frequency division signal;

the clock signal is obtained by the clock generation module based on the frequency division signal and fed back to the second counting module.

In one or more embodiments of the invention, the Gapped clock regeneration method further comprises:

the coefficients of the first digital filter are adjusted according to the sign of the difference value produced each time.

In one or more embodiments of the present invention, the Gapped clock regeneration method further comprises:

the absolute value of the difference is adjusted according to the sign of the difference generated each time.

In one or more embodiments of the present invention, the Gapped clock regeneration method further comprises:

the divided signal is adjusted according to the sign of the difference generated each time.

In one or more embodiments of the present invention, the Gapped clock regeneration method further comprises:

setting a second preset value;

and adjusting the output signal of the first digital filter based on the second preset value according to the sign of the difference value generated each time to obtain a frequency division signal.

Compared with the prior art, according to the Gapped clock regeneration circuit and the Gapped clock regeneration method, the indication signal used for representing the completion of each counting period is obtained through the periodic counting of the notch clock signal by the first counting module; receiving the indication signal through the control module to adaptively generate a control signal; the second counting module is used for periodically counting the clock signals based on the control signals to obtain count values, and the control module is used for receiving the count values and generating difference values between the count values and first preset values; processing the difference value based on the coefficient thereof by a first digital filter to obtain a frequency division signal; the clock signal is obtained based on the frequency division signal through the clock generation module and is fed back to the second counting module, so that the frequency of the clock signal can be quickly converged, and the clock signal with lower jitter performance and higher frequency precision can be obtained after the clock signal is locked.

Drawings

Fig. 1 is a schematic circuit diagram of a Gapped clock regeneration circuit according to a first embodiment of the invention.

Fig. 2 is a flowchart of a Gapped clock regeneration method according to a first embodiment of the invention.

Fig. 3 is a schematic circuit diagram of a Gapped clock regeneration circuit according to a second embodiment of the invention.

Detailed Description

Specific embodiments of the invention will be described in detail below with reference to the drawings, but it should be understood that the scope of the invention is not limited to the specific embodiments.

Throughout the specification and claims, unless explicitly stated otherwise, the term "comprise" or variations thereof such as "comprises" or "comprising", etc. will be understood to include the stated element or component without excluding other elements or components.

The term "coupled" or "connected" in this specification includes both direct and indirect connections. An indirect connection is a connection made through an intermediary, such as an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connections may also include connections through other active or passive devices, such as through circuits or components such as switches, follower circuits, and the like, that accomplish the same or similar functional objectives. Furthermore, in the present invention, terms such as "first," "second," and the like, are used primarily to distinguish one technical feature from another, and do not necessarily require or imply a certain actual relationship, number or order between the technical features.

As shown in fig. 1, a Gapped clock regeneration circuit comprises: a first counting module 10, a control module 20, a second counting module CNT2, a first digital filter DLPF1 and a clock generating module 40.

The first counting module 10 is configured to periodically count the gap clock signal Gapped clock to obtain an indication signal CL for indicating completion of each counting period.

Specifically, the first counting module 10 includes a first counter CNT1, a first register 11, and a synchronizer 12. The first counter CNT1 is connected to the first register 11, the first counter CNT1 is connected to the synchronizer 12, and the synchronizer 12 is connected to the control module 20.

In this embodiment, the first register 11 is configured to provide a configuration value N, and the count period of the first counter CNT1 is set by the configuration value N, and the count period of the first counter CNT1 may be an integer multiple of the configuration value N. The configuration value N also corresponds to the number of active clock edges of the Gapped clock signal during one period, and one or more periods may also be referred to as a frame.

The first counter CNT1 periodically counts the gap clock signal Gapped clock according to the configuration value N, and the output signal of the first counter CNT1 performs level inversion after counting one cycle at a time. The output signal of the first counter CNT1 is converted into an indication signal CL by the clock domain of the synchronizer 12, and then is sent to the control module 20, and the control module 20 receives the indication signal CL and then adaptively generates a control signal and sends the control signal to the second counting module CNT2.

The second counting module CNT2 periodically counts the clock signal clock based on the control signal to obtain a count value CNT2, and the control module 20 receives the count value CNT2 and generates a difference diff between the count value CNT2 and the first preset value M.

Specifically, the second counting module CNT2 receives the control signal and then periodically counts the clock signal, that is, under the control of the control signal output by the control module 20, the second counting module CNT2 can sample the edge of the indication signal CL, so as to start counting, and when the next edge of the indication signal CL is sampled, the second counting module CNT2 outputs the count value CNT2 to the control module 20, and simultaneously clears the count value CNT2 to perform the counting of the next period.

In the present embodiment, the first preset value M is configured by the second register 30, and the first preset value M can be set according to the expected frequency of the clock signal clock. When the control module 20 receives the count value cnt2, the count value cnt2 is subtracted from the first preset value M to obtain a difference diff, which also characterizes the frequency difference between the notch clock signal Gapped clock and the clock signal clock.

The difference diff is used as an input of the first digital filter DLPF1, and the first digital filter DLPF1 processes the difference diff based on its coefficient to obtain a divided signal Tuning Word (i.e., a division coefficient). First digital filter DLPF1 is preferably a digital low-pass filter. The coefficients of first digital filter DLPF1 are the coefficients of the filter transfer function, which determine the performance of the filter, such as gain, bandwidth, phase margin, etc.

The clock generation module 40 obtains a clock signal clock based on the divided signal Tuning Word and feeds back the clock signal clock to the second counting module CNT2.

In this embodiment, the clock generation module 40 includes a voltage controlled oscillator VCO and a digital controlled oscillator DCO connected to each other, and the first digital filter DLPF1 is connected to the digital controlled oscillator DCO, and the digital controlled oscillator DCO is connected to the second counting module CNT2. The frequency division signal Tuning Word is input to the digitally controlled oscillator DCO as a frequency division coefficient, and the clock signal clock is output through the digitally controlled oscillator DCO.

In this embodiment, the clock signal clock output by the digitally controlled oscillator DCO is transmitted as a feedback signal to the second counting module CNT2 for the second counting module CNT2 to count.

In this embodiment, the clock generating module 40 is a negative feedback module, if the sign of the difference diff is positive, that is, the count value cnt2 is greater than the first preset value M, it indicates that the frequency of the generated clock signal clock is higher than the expected frequency, and after the difference diff is input into the first digital filter DLPF1, the first digital filter DLPF1 increases the difference diff proportionally based on the coefficient thereof, so as to reduce the frequency of the clock signal clock output by the clock generating module 40 proportionally; conversely, if the sign of the difference diff is negative, that is, the count value cnt2 is smaller than the first preset value M, it indicates that the frequency of the generated clock signal clock is lower than the expected frequency, and the first digital filter DLPF1 decreases the difference diff proportionally based on the coefficient thereof, thereby increasing the frequency of the clock signal clock output by the clock generating module 40, and repeating the steps, so that the frequency of the generated clock signal clock is closer to the expected frequency, and finally locking the clock signal clock, so that the frequency of the generated clock signal clock is equal to the expected frequency, or fluctuates up and down centering on the expected frequency.

In this embodiment, the first preset value M and the configuration value N may be set to the same value or may be set to different values. When the clock signal clock is set to the same value, the frequency of the clock signal clock after final locking is the expected frequency; when the clock signal clock is set to be different in value, the frequency of the clock signal clock after final locking is M/N times of the expected frequency, so that the clock signal clock can be conveniently and flexibly adjusted on the basis of the expected frequency according to the requirement.

The frequency of the clock signal clock is mainly adjusted by adjusting the frequency division coefficient of the clock generating module 40, that is, adjusting the frequency division signal Tuning Word output by the first digital filter DLPF1, but there are various ways that the magnitude of the frequency division coefficient can be affected.

For example, as shown in fig. 2, the embodiment further discloses a method for regenerating a Gapped clock, which includes:

the gap clock signal Gapped clock is periodically counted by the first counting module 10 to obtain an indication signal CL for indicating the completion of each counting period.

The control signal is adaptively generated by the control module 20 receiving the indication signal CL.

The count value CNT2 is obtained by periodically counting the clock signal clock based on the control signal by the second counting module CNT2.

The control module 20 receives the count value cnt2 and generates a difference diff between the count value cnt2 and the first preset value M.

The divided signal Tuning Word is obtained by processing the difference diff by the first digital filter DLPF1 based on its coefficients. In the present embodiment, first digital filter DLPF1 processes the absolute value of difference diff.

The clock generation module 40 obtains a clock signal clock based on the frequency division signal Tuning Word and feeds back the clock signal clock to the second counting module CNT2.

In the present embodiment, the coefficients of first digital filter DLPF1 are adjusted by control module 20 according to the sign of difference diff each time.

Specifically, the frequency of the clock signal clock fed back negatively makes the coefficient of the first digital filter DLPF1 unchanged if the difference diff has the same sign as the difference diff generated last time (i.e. is either both positive or both negative); if the sign of the difference diff of the two times is opposite (i.e. from positive to negative, or from negative to positive), the coefficients of the first digital filter DLPF1 are changed, the coefficients may be scaled down. The coefficients of first digital filter DLPF1 may be adjusted by control module 20, and may be adjusted by employing other adjustment modules in other embodiments.

In addition, in the initial stage, the step size can be increased to adjust the coefficient of the first digital filter DLPF1, namely, a larger frequency division signal Tuning Word is output by adopting a larger coefficient, so that the expected frequency is approximated at a faster speed, and the convergence speed of the frequency of the clock signal clock is improved; as the frequency of the clock signal clock gets closer to the expected frequency, the step size is reduced to adjust the coefficient of the first digital filter DLPF1, i.e. a smaller coefficient is used, so that the frequency of the locked clock signal clock has lower jitter.

The invention also discloses a chip comprising the Gapped clock regeneration circuit.

Example 2

As shown in fig. 3, on the basis of embodiment 1, the Gapped clock regeneration circuit of this embodiment further includes a phase-locked loop 50, where the phase-locked loop 50 is connected to the first digital filter DLPF1, the clock generation module 40 and the second counting module CNT2, the clock generation module 40 generates an intermediate clock signal based on an output signal of the phase-locked loop 50, and the phase-locked loop 50 is configured to divide the intermediate clock signal based on the frequency division signal Tuning Word to generate the clock signal clock.

Specifically, the phase-locked loop 50 includes a first time-to-digital converter tdc_r, a phase frequency detector DPFD, a second digital filter DLPF2, a frequency divider MDiv, and a second time-to-digital converter tdc_fb. The first time-to-digital converter tdc_r is configured to receive the reference clock signal ref_clock and is simultaneously connected to the phase frequency detector DPFD, which is connected to the second digital filter DLPF2, the second digital filter DLPF2 is connected to the clock generating module 40, the clock generating module 40 is connected to the frequency divider MDiv, the frequency divider MDiv is connected to the second time-to-digital converter tdc_fb and the second counting module CNT2, and the first digital filter DLPF1, and the second time-to-digital converter tdc_fb is connected to the phase frequency detector.

The frequency dividing signal Tuning Word generated by the first digital filter DLPF1 is used as a frequency dividing coefficient of the frequency divider MDiv, the output signal of the second digital filter DLPF2 is used as a frequency dividing coefficient of the digitally controlled oscillator DCO, and the frequency divider MDiv outputs a clock signal clock after dividing an intermediate clock signal output by the digitally controlled oscillator DCO and feeds back the clock signal clock to the second counting module CNT2. Second digital filter DLPF2 is preferably a digital low-pass filter.

In this embodiment, the high-precision frequency divider MDiv (12-bit integer and 36-bit fractional) of the phase-locked loop 50 is adopted, so that the clock signal clock with higher frequency precision can be obtained after the intermediate clock signal output by the clock generating module 40 passes through the high-precision frequency divider MDiv.

The invention also discloses a chip comprising the Gapped clock regeneration circuit.

Example 3

In this embodiment, the frequency division signal Tuning Word can be adjusted in different ways based on the circuit configuration of embodiment 1 or embodiment 2.

The absolute value of the difference diff is adjusted, for example, by the control module 20, in dependence on the sign of the difference diff generated each time.

Specifically, the first counting module 10 is configured to periodically count the gap clock signal Gapped clock, so as to obtain an indication signal CL for indicating completion of each counting period.

The control signal is generated by the control module 20 receiving the indication signal CL.

The count value CNT2 is obtained by periodically counting the clock signal clock based on the control signal by the second counting module CNT2.

The control module 20 receives the count value cnt2 and generates a difference diff between the count value cnt2 and the first preset value M.

The divided signal Tuning Word is obtained by processing the difference diff by the first digital filter DLPF1 based on its coefficients. In general, first digital filter DLPF1 processes the absolute value of difference diff.

The clock generation module 40 obtains a clock signal clock based on the frequency division signal Tuning Word and feeds back the clock signal clock to the second counting module CNT2.

When the sign of the difference diff obtained by re-counting the clock signal clock fed back is the same as that of the previous difference diff (i.e. the difference diff is positive or negative), the adjustment is not performed, and if the sign of the difference diff is different from that of the previous difference diff (i.e. the difference diff is changed from positive to negative or from negative to positive), the absolute value of the current difference diff is adjusted, e.g. reduced proportionally. The change of the difference diff corresponds to the adjustment of the frequency-divided signal Tuning Word output by the first digital filter DLPF 1.

In the initial stage, the step size may be increased to adjust the absolute value of the difference diff, and when the frequency of the clock signal clock is closer to the expected frequency, the step size may be decreased to adjust the absolute value of the difference diff. In other embodiments, the adjustment of the absolute value of the difference diff may also be adjusted by other adjustment modules.

Example 4

In this embodiment, the frequency division signal Tuning Word can be adjusted in different ways based on the circuit configuration of embodiment 1 or embodiment 2.

For example, the control module 20 adjusts the output signal of the first digital filter by a second preset value according to the sign of the difference diff generated each time. In other embodiments, other adjustment modules may be used to set the second preset value and adjust the output signal of the first digital filter DLPF 1.

Specifically, a second preset value is set by the control module 20, the second preset value is a constant, the frequency division signal Tuning Word is obtained by adding the second preset value to the variable portion of the first digital filter DLPF1 based on the difference diff, when the sign of the difference diff obtained by counting the clock signal clock fed back again is the same as that of the last difference diff (i.e. same positive sign or same negative sign), the variable portion based on the difference diff is not changed, and when the sign of the difference diff is different from that of the last difference diff (i.e. change from positive sign to negative sign or from negative sign to positive sign), the variable portion based on the difference diff is changed.

In the initial stage, the step size can be increased to adjust the second preset value, and when the frequency of the clock signal clock is closer to the expected frequency, the step size is decreased to adjust the second preset value.

The foregoing descriptions of specific exemplary embodiments of the present invention are presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teachings or may be acquired from other forms, structures, arrangements, proportions, and with other components, materials and parts. The exemplary embodiments were chosen and described in order to explain the principles of the invention and its practical application to thereby enable others skilled in the art to make and utilize the invention in various exemplary embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.

Claims (10)

1. A Gapped clock regeneration circuit, comprising:

the first counting module is used for periodically counting the notch clock signals and obtaining indication signals used for representing the completion of each counting period;

the control module is used for receiving the indication signal and adaptively generating a control signal;

the second counting module is used for periodically counting the clock signals based on the control signals to obtain count values, and the control module receives the count values and generates difference values of the count values and first preset values;

a first digital filter for processing the difference value based on its coefficient to obtain a frequency-divided signal; and

and the clock generation module is used for obtaining a clock signal based on the frequency division signal and feeding the clock signal back to the second counting module.

2. The Gapped clock regeneration circuit of claim 1, wherein the first counting module comprises a first counter, a first register, and a synchronizer, the first counter coupled to the first register, the first counter coupled to the synchronizer, the synchronizer coupled to the control module.

3. The Gapped clock generation circuit of claim 1 wherein the first preset value is configured by a second register.

4. The Gapped clock regeneration circuit of claim 1, wherein the clock generation module comprises a connected voltage controlled oscillator and a digitally controlled oscillator, the first digital filter number being connected to the digitally controlled oscillator, the digitally controlled oscillator being connected to the second counting module.

5. The Gapped clock regeneration circuit of claim 1, further comprising a phase-locked loop coupled to the first digital filter, the clock generation module, and the second count module, the clock generation module generating an intermediate clock signal based on an output signal of the phase-locked loop, the phase-locked loop configured to divide the intermediate clock signal based on the divided signal to generate the clock signal.

6. The Gapped clock regeneration circuit of claim 5, wherein the phase-locked loop comprises a first time-to-digital converter, a phase-frequency detector, a second digital filter, a frequency divider, and a second time-to-digital converter, the first time-to-digital converter configured to receive the reference clock signal and simultaneously coupled to the phase-frequency detector, the phase-frequency detector coupled to the second digital filter, the second digital filter coupled to the clock generation module, the clock generation module coupled to the frequency divider, the frequency divider coupled to the second time-to-digital converter and the second counting module, and the first digital filter, the second time-to-digital converter coupled to the phase-frequency detector.

7. A Gapped clock regeneration method, comprising:

periodically counting the notch clock signals through a first counting module to obtain indication signals used for representing the completion of each counting period;

receiving the indication signal through the control module to adaptively generate a control signal;

periodically counting the clock signals based on the control signals by a second counting module to obtain count values;

receiving the count value and generating a difference value between the count value and a first preset value through a control module;

processing the difference value based on the coefficient thereof by a first digital filter to obtain a frequency division signal;

the clock signal is obtained by the clock generation module based on the frequency division signal and fed back to the second counting module.

8. The Gapped clock regeneration method of claim 7, further comprising:

the coefficients of the first digital filter are adjusted according to the sign of the difference value produced each time.

9. The Gapped clock regeneration method of claim 7, further comprising:

the absolute value of the difference is adjusted according to the sign of the difference generated each time.

10. The Gapped clock regeneration method of claim 7, further comprising:

setting a second preset value;

and adjusting the output signal of the first digital filter based on the second preset value according to the sign of the difference value generated each time to obtain a frequency division signal.

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