CN116072717A - Semiconductor structure and manufacturing method thereof, transistor and manufacturing method thereof - Google Patents

Semiconductor structure and manufacturing method thereof, transistor and manufacturing method thereof Download PDF

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Publication number
CN116072717A
CN116072717A CN202111269573.0A CN202111269573A CN116072717A CN 116072717 A CN116072717 A CN 116072717A CN 202111269573 A CN202111269573 A CN 202111269573A CN 116072717 A CN116072717 A CN 116072717A
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layer
oxide layer
silicate
forming
metal oxide
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沈宇桐
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to PCT/CN2021/136467 priority patent/WO2023070846A1/en
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    • H01L29/513—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L29/51—
    • H01L29/517—
    • H01L29/66477—
    • H01L29/66568—
    • H01L29/76—
    • H01L29/78—
    • H01L29/7838—

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  • Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract

The embodiment of the disclosure discloses a semiconductor structure, a manufacturing method thereof, a transistor and a manufacturing method thereof. Wherein, the semiconductor structure is used for forming a gate oxide layer, and the semiconductor structure includes: a metal oxide layer, wherein the dielectric constant of the material of the metal oxide layer is larger than a preset value, and the metal oxide layer is provided with a first surface and a second surface which are oppositely arranged; and a silicate layer covering the first surface and/or the second surface, the silicate layer having the same metal element as the metal oxide layer, the silicon content in the silicate layer gradually increasing along a first direction, the first direction being directed away from the metal oxide layer by the metal oxide layer.

Description

Semiconductor structure and manufacturing method thereof, transistor and manufacturing method thereof
Technical Field
The present disclosure relates to the field of semiconductor structures, and more particularly, to a semiconductor structure, a method of manufacturing the semiconductor structure, a transistor, and a method of manufacturing the transistor.
Background
Metal-Oxide-Semiconductor (MOS) devices are complementary Metal Oxide semiconductors employed in modern integrated circuitsConductor (CMOS, complementary Metal Oxide Semiconductor) logic. One or more layers of dielectric material are formed on a semiconductor (typically silicon) substrate, and then a gate is formed on the dielectric. Early devices used silicon oxide (SiO 2 ) As gate dielectric layer, and polysilicon (Poly) is used as gate. However, as feature sizes decrease, the thickness of the gate dielectric layer becomes smaller and smaller. The reduction in oxide thickness directly results in significant gate oxide leakage current caused by tunneling. In order to alleviate this problem, a material having a higher dielectric constant than silicon oxide, i.e., a high-K material, has been used in the related art instead of silicon oxide as the gate dielectric layer. Here, high K materials generally refer to materials having a dielectric constant above 3.9, and typically significantly above this value. For example, k=5 is considered to be moderately high, and k=20 is considered to be extremely high. The high-K material used for the gate dielectric layer is typically a metal oxide, such as hafnium oxide (HfO 2 )。
However, the introduction of high-K materials in the gate dielectric layer in the related art presents some new challenges.
Disclosure of Invention
In order to solve the related technical problems, embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, and a transistor and a manufacturing method thereof.
Embodiments of the present disclosure provide a semiconductor structure for forming a gate oxide layer, the semiconductor structure comprising:
a metal oxide layer, wherein the dielectric constant of the material of the metal oxide layer is larger than a preset value, and the metal oxide layer is provided with a first surface and a second surface which are oppositely arranged;
and a silicate layer covering the first surface and/or the second surface, the silicate layer having the same metal element as the metal oxide layer, the silicon content in the silicate layer gradually increasing along a first direction, the first direction being directed away from the metal oxide layer by the metal oxide layer.
In the above scheme, the material of the metal oxide layer comprises hafnium oxide or zirconium oxide.
In the above aspect, the silicate layer includes a continuous silicate layer, and the silicon content in the continuous silicate layer gradually increases along the first direction;
or,
the silicate layer includes a plurality of stacked sub-silicate layers, and the silicon content in the plurality of stacked sub-silicate layers gradually increases along a first direction.
In the above aspect, the silicate layer includes a first silicate layer and a second silicate layer, the first silicate layer covers the first surface, the second silicate layer covers the second surface, and the silicon content in the first silicate layer and the silicon content in the second silicate layer both gradually increase along the first direction.
The embodiment of the disclosure also provides a transistor, which comprises:
a substrate;
a source and a drain in the substrate;
a gate oxide layer between the source and drain electrodes; the gate oxide layer comprises the semiconductor structure provided by the embodiment of the disclosure;
and a gate electrode on the gate oxide layer.
In the above scheme, the gate oxide layer further comprises a silicon oxide layer located between the substrate and the semiconductor structure.
Embodiments of the present disclosure further provide a method for manufacturing a semiconductor structure for forming a gate oxide layer, the method including:
forming a metal oxide layer; the dielectric constant of the material of the metal oxide layer is larger than a preset value; the metal oxide layer is provided with a first surface and a second surface which are oppositely arranged;
forming a silicate layer on the first surface and/or the second surface, the silicate layer having the same metal element as the metal oxide layer; the silicon content in the silicate layer gradually increases along a first direction; the first direction is directed by the metal oxide layer away from the metal oxide layer.
In the above aspect, the forming a silicate layer on the first surface and/or the second surface includes:
a silicate layer having a gradient of silicon content along a first direction is formed on the first surface and/or the second surface using a deposition parameter having a gradient over time.
In the above aspect, the deposition parameters include at least one of:
the proportion of silicon source in the deposition reaction gas;
the rate of introduction of the silicon source into the deposition reaction gas.
In the above aspect, the forming a silicate layer on the first surface and/or the second surface includes:
forming a continuous silicate layer, the silicon content of the continuous silicate layer gradually increasing along a first direction;
or,
a sub-silicate layer having a plurality of stacks is formed, the silicon content in the plurality of stacked sub-silicate layers gradually increasing along a first direction.
In the above aspect, the forming a silicate layer on the first surface and/or the second surface includes:
depositing a material for forming a silicate layer on the first surface and/or the second surface;
and annealing the deposited material for forming the silicate layer to obtain the silicate layer.
In the above aspect, the depositing the material for forming the silicate layer on the first surface and/or the second surface includes:
the material for forming the silicate layer is deposited on the first surface and/or the second surface by atomic layer deposition, chemical vapor deposition or molecular beam epitaxy.
In the above scheme, in the annealing process, the adopted temperature range is as follows: 500-900 ℃.
In the above scheme, in the annealing process, the pressure range adopted is as follows: 1.2Pa to 1.4Pa.
The embodiment of the disclosure also provides a method for manufacturing the transistor, which comprises the following steps:
providing a substrate;
forming a source electrode and a drain electrode in the substrate;
forming a gate oxide layer between the source electrode and the drain electrode; the grid electrode oxide layer is formed by adopting the manufacturing method of the semiconductor structure provided by the embodiment of the disclosure;
and forming a gate electrode on the gate oxide layer.
In the above scheme, the gate oxide layer further includes: a silicon oxide layer; the forming a gate oxide layer between the source and the drain includes:
forming a silicon oxide layer between the substrate and the semiconductor structure;
and forming the semiconductor structure on the silicon oxide layer to obtain the gate oxide layer.
The embodiment of the disclosure provides a semiconductor structure, a manufacturing method thereof, a transistor and a manufacturing method thereof. Wherein, the semiconductor structure is used for forming a gate oxide layer, and the semiconductor structure includes: a metal oxide layer; the dielectric constant of the material of the metal oxide layer is larger than a preset value; the metal oxide layer is provided with a first surface and a second surface which are oppositely arranged; a silicate layer; the silicate layer covers the first and/or second surface; the silicate layer has the same metal element as the metal oxide layer; the silicon content of the silicate layer gradually increases along a first direction; the first direction is directed by the metal oxide layer away from the metal oxide layer. In embodiments of the present disclosure, a metal-based silicate of graded silicon composition is disposed on one side, or two opposite sides, of a metal oxide having a high dielectric constant, wherein the silicon content of the metal-based silicate on each side increases with increasing distance from the metal oxide layer. It will be appreciated that the metal-based silicate with increased silicon content forms metal-based siloxane bonds when in direct contact with silicon that have better stability at high temperatures, thus introducing higher silicon content metal-based silicate at the interface where contact with silicon is possible; the too high silicon component can reduce the dielectric constant, so that the thickness of the equivalent oxide layer is increased, which is extremely unfavorable for further optimization and dimensional shrinkage of the high-K device, so that the contact surface layer can be ensured to have more stable metal-based silicon-oxygen bond through the introduction of metal-based silicate with gradually changed components, and the degradation of the device performance caused by the introduction of silicon can be reduced.
Drawings
Fig. 1 is a schematic implementation flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;
FIGS. 2 a-2 c are schematic illustrations of the structural relationship between several metal oxide layers and silicate layers provided by embodiments of the present disclosure;
fig. 3 is a schematic implementation flow chart of a method for manufacturing a transistor according to an embodiment of the disclosure;
fig. 4 is a schematic structural diagram of a transistor according to an embodiment of the present disclosure.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.
In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.
It will be appreciated that spatially relative terms such as "under … …," "under … …," "below," "under … …," "over … …," "above," and the like may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under … …" and "under … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
It should be noted that: "first," "second," etc. are used to distinguish similar objects and not necessarily to describe a particular order or sequence.
So that the manner in which the features and techniques of the disclosed embodiments can be understood in more detail, a more particular description of the embodiments of the disclosure, briefly summarized below, may be had by reference to the appended drawings, which are not intended to be limiting of the embodiments of the disclosure.
In the field of semiconductor device fabrication, dielectric layers are continually thinned as dimensions continue to shrink. Silicon oxide is used as a dielectric layer to bring about non-negligible gate leakage, so that a high dielectric constant (high-K) material is introduced in the device dielectric layer preparation process. With the intensive research, some high-K materials, such as hafnium oxide (HfO 2 ) The wide band gap and the high stability of the interface with silicon (Si) become excellent candidate materials. However, with further investigation into the dielectric layer fabrication process, the introduction of high-K materials presents some new challenges.
In various embodiments of the present disclosure, a metal-based silicate of graded silicon composition is disposed on one side, or two opposite sides, of a metal oxide having a high dielectric constant, wherein the silicon content of the metal-based silicate on each side increases with increasing distance from the metal oxide layer. It will be appreciated that the provision of metal oxide may allow for a reduction in the equivalent oxide thickness (EOT, equivalent Oxide Thickness) of the dielectric layer; meanwhile, the metal-based silicon oxide bond formed when the metal-based silicate with increased silicon content is directly contacted with silicon has better stability at high temperature, so that the metal-based silicate with higher silicon component is introduced at the interface which is possibly contacted with silicon; the too high silicon component can reduce the dielectric constant, so that the EOT is increased, so that the contact surface layer can be ensured to have more stable metal-based silicon-oxygen bonds through the introduction of metal-based silicate with gradually changed components, and the increase of the EOT caused by the introduction of silicon can be reduced.
An embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, and fig. 1 is a schematic implementation flow diagram of the method for manufacturing a semiconductor structure according to the embodiment of the present disclosure. As shown in fig. 1, the semiconductor structure is used for forming a gate oxide layer, and the manufacturing method of the semiconductor structure includes:
step 101: forming a metal oxide layer; the dielectric constant of the material of the metal oxide layer is larger than a preset value; the metal oxide layer is provided with a first surface and a second surface which are oppositely arranged;
step 102: forming a silicate layer on the first surface and/or the second surface, the silicate layer having the same metal element as the metal oxide layer; the silicon content in the silicate layer gradually increases along a first direction; the first direction is directed by the metal oxide layer away from the metal oxide layer.
It should be understood that the operations shown in fig. 1 are not exclusive and that other operations may be performed before, after, or between any of the operations shown. In practical application, the execution sequence can be adjusted according to the needs, and even the steps 101 and 102 can be alternately executed.
It should be noted that the semiconductor structure is to be used in a subsequent process to form a gate oxide or a gate dielectric.
In step 101, the preset value is greater than 3.9, that is, the dielectric constant of the material of the metal oxide layer in the embodiment of the disclosure is higher. In some embodiments, the material of the metal oxide layer comprises hafnium oxide or zirconium oxide (ZrO 2 )。
Here, the first surface and the second surface are two surfaces where the metal oxide layers are disposed opposite to each other. In practice, one of the first surface and the second surface (lower surface) is close to a substrate, for example, a silicon substrate, and the other surface (upper surface) is close to a gate electrode, such as a polysilicon gate electrode or a metal gate electrode. In the latter embodiment, the first surface is defined as the lower surface of the metal oxide layer and the second surface is defined as the upper surface of the metal oxide layer for clarity and conciseness of expression.
In step 102, the silicate layer includes a metal-based silicate layer, and the metal-based is the same as the metal element in the metal oxide layer in step 101.
Illustratively, the material of the metal oxide layer is hafnium oxide, then the material of the silicate layer is hafnium-based silicate (HfSiO x ) The method comprises the steps of carrying out a first treatment on the surface of the Alternatively, the material of the metal oxide layer is zirconia, and the material of the silicate layer is zirconium-based silicate (ZrSiO x )。
Here, for the metal oxide, whether the upper surface or the lower surface, the first direction is directed away from the metal oxide layer.
Fig. 2 a-2 c are schematic illustrations of the structural relationship between several metal oxide layers and silicate layers provided by embodiments of the present disclosure.
Illustratively, as shown in fig. 2a, the silicate layer 202 covers the lower surface of the metal oxide layer 201, and the silicon content of the silicate layer gradually increases in the direction indicated by the arrow in fig. 2 a. It will be appreciated that in practice, the silicate layer 202 needs to be formed first, and then the metal oxide layer 201 needs to be formed on the silicate layer 202.
Illustratively, as shown in fig. 2b, the silicate layer 202 covers the upper surface of the metal oxide layer 201, and the silicon content of the silicate layer gradually increases in the direction indicated by the arrow in fig. 2 b. It will be appreciated that in practical applications, the metal oxide layer 201 needs to be formed first, and then the silicate layer 202 needs to be formed on the metal oxide layer 201.
Illustratively, as shown in FIG. 2c, the silicate layers include a first silicate layer 202-1 and a second silicate layer 202-2; wherein the first silicate layer 202-1 covers the lower surface of the metal oxide layer 201, the second silicate layer 202-2 covers the upper surface of the metal oxide layer, and the silicon content of each of the first silicate layer 202-1 and the second silicate layer 202-2 increases gradually in the direction indicated by the corresponding arrow in fig. 2 c. It will be appreciated that in practice, it is necessary to form the first silicate layer 202-1, then form the metal oxide layer 201 on the first silicate layer 202-1, and then form the second silicate layer 202-2 on the metal oxide layer 201.
It should be noted that the arrangement of the silicate layer 202 with respect to the metal oxide layer 201 may depend on whether the metal oxide layer 201 is close to the substrate material that is easily oxidized in practical applications. That is, when the silicate layer 202 is close to a substrate material that is susceptible to oxidation, a metal-based silicate layer incorporating a graded silicon composition is required.
In some embodiments, the forming a silicate layer on the first surface and/or the second surface comprises:
a silicate layer having a gradient of silicon content along a first direction is formed on the first surface and/or the second surface using a deposition parameter having a gradient over time.
Wherein, in some embodiments, the deposition parameters include at least one of:
the proportion of silicon source in the deposition reaction gas;
the rate of introduction of the silicon source into the deposition reaction gas.
That is, in practical applications, the silicate layer of graded composition may be formed by controlling the proportion of the silicon source in the deposition reaction gas or controlling the rate of introduction of the silicon source in the deposition reaction gas, or the like. Taking the silicate layer shown in fig. 2c as an example, the portion of the silicate layer with a small silicon component may be formed by controlling the proportion of the silicon source in the deposition reaction gas to be smaller and smaller or controlling the introduction rate of the silicon source in the deposition reaction gas to be smaller and smaller so that the deposition reaction is insufficient; the silicon component of the silicate layer can be formed in a large part by controlling the proportion of the silicon source in the deposition reaction gas to be larger or controlling the introducing rate of the silicon source in the deposition reaction gas to be larger so that the deposition reaction is sufficient.
In some embodiments, the forming a silicate layer on the first surface and/or the second surface comprises:
forming a continuous silicate layer, the silicon content of the continuous silicate layer gradually increasing along a first direction;
or,
a sub-silicate layer having a plurality of stacks is formed, the silicon content in the plurality of stacked sub-silicate layers gradually increasing along a first direction.
In practical applications, the silicate layer may be a silicate layer having a continuously graded silicon content, or may be a silicate layer having a silicon content that is graded at intervals, formed from a plurality of sub-silicate layers.
In some embodiments, the forming a silicate layer on the first surface and/or the second surface comprises:
depositing a material for forming a silicate layer on the first surface and/or the second surface;
and annealing the deposited material for forming the silicate layer to obtain the silicate layer.
Here, in practical application, when the silicate layer is formed as a continuous silicate layer, the annealing treatment is an annealing treatment after the formation of the entire gate oxide layer; when the silicate layer is formed as a sub-silicate layer having a plurality of stacks, the annealing treatment is an annealing treatment after each sub-silicate layer is formed.
In practice, in some embodiments, the depositing of the material for forming the silicate layer on the first surface and/or the second surface comprises:
the material for forming the silicate layer is deposited on the first surface and/or the second surface by atomic layer deposition (ALD, atomic Layer Deposition), chemical vapor deposition (CVD, chemical Vapour Deposition) or molecular beam epitaxy (MBE, molecular Beam Epitaxy). In some embodiments, the temperature ranges employed during the annealing are: 500-900 ℃.
In some embodiments, the pressure ranges employed during the annealing are: 1.2Pa to 1.4Pa. Annealing at this temperature and pressure range can fully activate the silicate layer in the gate oxide layer.
Illustratively, the preparation of the high-K dielectric layer is performed on the silicon substrate by a cycle-by-cycle deposition process using ALD or the like, so as to ensure the formation of a uniform and dense thin film. And can be deposited at a faster growth rate, e.g., 0.1 nm/cycle. In the process, the reaction temperature in the reaction furnace tube, the introducing speed of a silicon source, the air pressure in the furnace and other factors are controlled, and the introducing of silicon is controlled; and using a rapid annealing furnace to rapidly anneal the sample (RTA): the rapid annealing is completed at 600 ℃ and 800 ℃ under the condition that the vacuum degree in the annealing tube is about 1.3Pa, and the uniform and compact silicate layer can be ensured to be formed.
The embodiment of the disclosure provides a manufacturing method of a semiconductor structure, wherein the semiconductor structure is used for forming a gate oxide layer, and the manufacturing method of the semiconductor structure comprises the following steps: forming a metal oxide layer; the dielectric constant of the material of the metal oxide layer is larger than a preset value; the metal oxide layer is provided with a first surface and a second surface which are oppositely arranged; forming a silicate layer on the first surface and/or the second surface, the silicate layer having the same metal element as the metal oxide layer; the silicon content in the silicate layer gradually increases along a first direction; the first direction is directed by the metal oxide layer away from the metal oxide layer. In embodiments of the present disclosure, a metal-based silicate of graded silicon composition is disposed on one side, or two opposite sides, of a metal oxide having a high dielectric constant, wherein the silicon content of the metal-based silicate on each side increases with increasing distance from the metal oxide layer. It will be appreciated that the metal-based silicate with increased silicon content forms metal-based siloxane bonds when in direct contact with silicon that have better stability at high temperatures, thus introducing higher silicon content metal-based silicate at the interface where contact with silicon is possible; the too high silicon component can reduce the dielectric constant, so that the thickness of the equivalent oxide layer is increased, which is extremely unfavorable for further optimization and dimensional shrinkage of the high-K device, so that the contact surface layer can be ensured to have more stable metal-based silicon-oxygen bond through the introduction of metal-based silicate with gradually changed components, and the degradation of the device performance caused by the introduction of silicon can be reduced.
Based on the above method for manufacturing a semiconductor structure, an embodiment of the present disclosure further provides a method for manufacturing a transistor, as shown in fig. 3, where the method for manufacturing a transistor includes:
step 301: providing a substrate;
step 302: forming a source electrode and a drain electrode in the substrate;
step 303: forming a gate oxide layer between the source electrode and the drain electrode; the grid electrode oxide layer is formed by adopting the manufacturing method of the semiconductor structure provided by the embodiment of the disclosure;
step 304: and forming a gate electrode on the gate oxide layer.
In practice, the gate material may include polysilicon and/or a metal material, which may include, but is not limited to, titanium nitride (TiN) or tantalum nitride (TaN), among others, in some embodiments.
Wherein, in some embodiments, the gate oxide layer further comprises: a silicon oxide layer; the forming a gate oxide layer between the source and the drain includes:
forming a silicon oxide layer between the substrate and the semiconductor structure;
and forming the semiconductor structure on the silicon oxide layer to obtain the gate oxide layer.
Fig. 4 is a schematic structural diagram of a transistor according to an embodiment of the disclosure. The process of manufacturing the transistor is described in connection with fig. 4.
Here, in practical applications, the material of the substrate includes, but is not limited to, silicon. Ion implantation may be used to form the source and drain electrodes in the substrate. Pocket doping (halo implant) or Lightly Doped Drain (LDD) doping may also be performed beside the source and drain, respectively, to form pocket doped and lightly doped regions. Thereafter, a gate oxide layer is formed using the method for manufacturing a semiconductor structure provided in the embodiments of the present disclosure, and fig. 4 only shows a case where a silicate layer includes a first silicate layer and a second silicate layer, and the first silicate layer covers a lower surface of the metal oxide layer and the second silicate layer covers an upper surface of the metal oxide layer. In a related development, to be more compatible with high-K dielectric layers, polysilicon gates have been replaced with metal gates, based on which metal gates can be formed on the gate oxide layer. In some embodiments, the gate may include polysilicon and/or a metallic material. And protective side walls can be formed on two sides of the metal grid electrode.
Based on the above method for manufacturing a semiconductor structure, an embodiment of the present disclosure further provides a semiconductor structure for forming a gate oxide layer, where the semiconductor structure includes:
a metal oxide layer, wherein the dielectric constant of the material of the metal oxide layer is larger than a preset value, and the metal oxide layer is provided with a first surface and a second surface which are oppositely arranged;
and a silicate layer covering the first surface and/or the second surface, the silicate layer having the same metal element as the metal oxide layer, the silicon content in the silicate layer gradually increasing along a first direction, the first direction being directed away from the metal oxide layer by the metal oxide layer.
Wherein in some embodiments, the material of the metal oxide layer comprises hafnium oxide or zirconium oxide.
In some embodiments, the silicate layer comprises a continuous silicate layer having a silicon content that increases gradually in a first direction;
or,
the silicate layer includes a plurality of stacked sub-silicate layers, and the silicon content in the plurality of stacked sub-silicate layers gradually increases along a first direction.
In some embodiments, the silicate layers include a first silicate layer covering the first surface and a second silicate layer covering the second surface, the silicon content in the first silicate layer and the silicon content in the second silicate layer both increasing gradually along the first direction.
In some embodiments, the first silicate layer and the second silicate layer may each comprise a hafnium (zirconate).
It will be appreciated that the graded composition hafnium (zirconium) based silicate/hafnium (zirconium) oxide/graded composition hafnium (zirconium) based silicate dielectric layer advantageously reduces the formation of interfacial silicon oxide (low K material) while improving the thermal stability of the hafnium (zirconium) based silicate (high K material).
Because hafnium (zirconium) -based silicate exhibits better electrical properties and higher thermal stability when in direct contact with silicon, the resultant Hf (Zr) -Si-O bond has better stability at high temperatures, introducing higher Si content Hf-based silicate at the interface with Si; too high a Si composition affects the relative permittivity of the dielectric layer, thereby increasing EOT, which is extremely disadvantageous for further optimization of high K devices already in terms of dimensional shrinkage; by introducing a hafnium (zirconium) -based silicate with graded composition, it is possible to ensure more stable Hf (Zr) -Si-O on the contact surface layer while controlling the Si composition by layer growth to reduce degradation of device performance due to Si introduction.
Embodiments of the present disclosure provide a high-K dielectric layer utilizing a graded silicon composition hafnium (zirconium) based silicate/hafnium (zirconium) oxide/graded silicon composition hafnium (zirconium) based silicate, wherein the performance of the high-K dielectric layer can be further tuned by adjusting the thickness of the hafnium (zirconium) oxide by controlling the uptake of a silicon-based source during the growth of the high-K dielectric layer material to form a graded silicate layer.
Based on the above semiconductor structure, an embodiment of the present disclosure further provides a transistor, including:
a substrate;
a source and a drain in the substrate;
a gate oxide layer between the source and drain electrodes; the gate oxide layer comprises the semiconductor structure provided by the embodiment of the disclosure;
and a gate electrode on the gate oxide layer.
In practice, the gate material may include polysilicon and/or a metal material, which may include, but is not limited to, titanium nitride (TiN) or tantalum nitride (TaN), among others, in some embodiments. Wherein in some embodiments the gate oxide layer further comprises a silicon oxide layer between the substrate and the semiconductor structure.
It should be noted that the embodiments of the present disclosure propose a new structure and manufacturing method of a high-K dielectric layer, which can be used to form CMOS based on the high-K dielectric layer.
It should be appreciated that reference throughout this specification to "some embodiments" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in some embodiments" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by their functions and internal logic, and should not constitute any limitation on the implementation of the embodiments of the present disclosure. The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments.
The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment.
The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (16)

1. A semiconductor structure for forming a gate oxide layer, the semiconductor structure comprising:
a metal oxide layer, wherein the dielectric constant of the material of the metal oxide layer is larger than a preset value, and the metal oxide layer is provided with a first surface and a second surface which are oppositely arranged;
and a silicate layer covering the first surface and/or the second surface, the silicate layer having the same metal element as the metal oxide layer, the silicon content in the silicate layer gradually increasing along a first direction, the first direction being directed away from the metal oxide layer by the metal oxide layer.
2. The semiconductor structure of claim 1, wherein the material of the metal oxide layer comprises hafnium oxide or zirconium oxide.
3. The semiconductor structure of claim 1, wherein,
the silicate layer comprises a continuous silicate layer, wherein the silicon content of the continuous silicate layer gradually increases along a first direction;
or,
the silicate layer includes a plurality of stacked sub-silicate layers, and the silicon content in the plurality of stacked sub-silicate layers gradually increases along a first direction.
4. The semiconductor structure of claim 1, wherein the silicate layer comprises a first silicate layer and a second silicate layer, the first silicate layer overlying the first surface and the second silicate layer overlying the second surface, the silicon content in the first silicate layer and the silicon content in the second silicate layer both increasing gradually along the first direction.
5. A transistor, comprising:
a substrate;
a source and a drain in the substrate;
a gate oxide layer between the source and drain electrodes; the gate oxide layer comprising the semiconductor structure of any of claims 1-4;
and a gate electrode on the gate oxide layer.
6. The transistor of claim 5, wherein the gate oxide layer further comprises a silicon oxide layer between the substrate and the semiconductor structure.
7. A method of manufacturing a semiconductor structure for forming a gate oxide layer, the method comprising:
forming a metal oxide layer; the dielectric constant of the material of the metal oxide layer is larger than a preset value; the metal oxide layer is provided with a first surface and a second surface which are oppositely arranged;
forming a silicate layer on the first surface and/or the second surface, the silicate layer having the same metal element as the metal oxide layer; the silicon content in the silicate layer gradually increases along a first direction; the first direction is directed by the metal oxide layer away from the metal oxide layer.
8. The method of manufacturing according to claim 7, wherein the forming a silicate layer on the first surface and/or the second surface comprises:
a silicate layer having a gradient of silicon content along a first direction is formed on the first surface and/or the second surface using a deposition parameter having a gradient over time.
9. The method of manufacturing according to claim 8, wherein the deposition parameters include at least one of:
the proportion of silicon source in the deposition reaction gas;
the rate of introduction of the silicon source into the deposition reaction gas.
10. The method of manufacturing according to claim 7, wherein the forming a silicate layer on the first surface and/or the second surface comprises:
forming a continuous silicate layer, the silicon content of the continuous silicate layer gradually increasing along a first direction;
or,
a sub-silicate layer having a plurality of stacks is formed, the silicon content in the plurality of stacked sub-silicate layers gradually increasing along a first direction.
11. The method of manufacturing according to claim 7, wherein the forming a silicate layer on the first surface and/or the second surface comprises:
depositing a material for forming a silicate layer on the first surface and/or the second surface;
and annealing the deposited material for forming the silicate layer to obtain the silicate layer.
12. The method of manufacturing according to claim 11, wherein depositing a material for forming a silicate layer on the first surface and/or the second surface comprises:
the material for forming the silicate layer is deposited on the first surface and/or the second surface by atomic layer deposition, chemical vapor deposition or molecular beam epitaxy.
13. The method of claim 11, wherein the annealing is performed at a temperature in the range of: 500-900 ℃.
14. The method of claim 11, wherein the annealing is performed under a pressure in the range of: 1.2Pa to 1.4Pa.
15. A method of manufacturing a transistor, comprising:
providing a substrate;
forming a source electrode and a drain electrode in the substrate;
forming a gate oxide layer between the source electrode and the drain electrode; the gate oxide layer is formed using the method of manufacturing a semiconductor structure as claimed in any one of claims 7 to 14;
and forming a gate electrode on the gate oxide layer.
16. The method of manufacturing of claim 15, the gate oxide layer further comprising: a silicon oxide layer; the forming a gate oxide layer between the source and the drain includes:
forming a silicon oxide layer between the substrate and the semiconductor structure;
and forming the semiconductor structure on the silicon oxide layer to obtain the gate oxide layer.
CN202111269573.0A 2021-10-29 2021-10-29 Semiconductor structure and manufacturing method thereof, transistor and manufacturing method thereof Pending CN116072717A (en)

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