CN115810538A - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
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Abstract
The application relates to a semiconductor structure and a preparation method thereof, comprising the steps of forming an oxide material layer; forming a diffusion barrier material layer on the surface of the oxide material layer; nitriding the obtained structure so as to convert part of the oxide material layer into a nitrogen-containing material layer; the nitrogen-containing material layer is located between the diffusion barrier material layer and the remaining oxide material layer. According to the preparation method of the semiconductor structure, the obtained structure is doped with nitrogen, so that boron diffusion can be effectively blocked, and the NBTI effect caused by boron diffusion is reduced; meanwhile, only part of the oxide material layer is converted into the nitrogen-containing material layer, and the doping depth of the nitrogen element is smaller than the thickness of the oxide material layer and the blocking effect of the diffusion blocking material layer, so that the nitrogen element can be accurately controlled to be positioned on the upper surface of the oxide material layer, the NBTI effect is reduced, and the reliability and the stability of the device performance are improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor structure and a method for fabricating the same.
Background
As the size of semiconductor devices is reduced and new materials and structures are used, the Negative Bias Temperature Instability (NBTI) effect of semiconductor devices becomes more and more significant, and the impact on the device performance is more severe. Among them, NBTI problems caused by breakdown of device oxide layer, leakage and boron (B) diffusion in polysilicon Gate (Gate Poly) are important factors that hinder the development of semiconductor integrated circuits.
Nitrogen (N) has proven to be an effective barrier to boron diffusion, and in conventional techniques, nitridation of oxide layers, such as nitridation of silicon oxide layers to form silicon oxynitride layers, has significantly improved the above-mentioned problems.
However, as the thickness of the oxide layer is reduced, nitrogen inevitably diffuses to the device interface, which leads to serious NBTI problem, and thus it is difficult to precisely control the nitrogen on the upper surface of the oxide layer.
Disclosure of Invention
In view of the foregoing, it is necessary to provide a semiconductor structure and a method for fabricating the same, which can solve the above problems.
To achieve the above and other objects, according to some embodiments, the present application provides a method for manufacturing a semiconductor structure, comprising:
forming an oxide material layer;
forming a diffusion barrier material layer on the surface of the oxide material layer;
nitriding the obtained structure so as to convert part of the oxide material layer into a nitrogen-containing material layer; the nitrogen-containing material layer is positioned between the diffusion barrier material layer and the remaining oxide material layer.
In one embodiment, the nitriding of the resulting structure to convert a portion of the oxide material layer into a nitrogen-containing material layer comprises:
nitriding the obtained structure to dope nitrogen elements into the oxide material layer from the surface of the oxide material layer, which is in contact with the diffusion barrier material layer; the nitrogen element reacts with a portion of the oxide material layer to form the nitrogen-containing material layer.
In one embodiment, the diffusion barrier material layer comprises a first gate material layer;
after the nitridation treatment is carried out on the obtained structure so that part of the oxide material layer is converted into the nitrogen-containing material layer, the method further comprises the following steps:
and forming a second gate material layer on the surface of the diffusion barrier material layer far away from the nitrogen-containing material layer.
In one embodiment, the semiconductor structure comprises a gate structure;
after the step of forming the second gate material layer on the surface of the diffusion barrier material layer away from the nitrogen-containing material layer, the method further comprises the following steps:
and patterning the second grid material layer, the diffusion barrier material layer, the nitrogen-containing material layer and the oxidation material layer to obtain the grid structure which comprises an oxidation layer, a nitrogen-containing layer, a diffusion barrier layer and a grid layer which are sequentially overlapped from bottom to top.
In one embodiment, after the nitridation treatment is performed on the obtained structure to convert part of the oxide material layer into the nitrogen-containing material layer, the method may further include the following steps:
and removing the diffusion barrier material layer.
In one embodiment, the diffusion barrier layer comprises a first gate material layer;
after the step of removing the diffusion barrier layer, the method further comprises the following steps:
and forming a second gate material layer on the surface of the nitrogen-containing material layer far away from the oxide material layer.
In one embodiment, the semiconductor structure comprises a gate structure;
after the step of forming the second gate material layer on the surface of the nitrogen-containing material layer away from the oxide material layer, the method further comprises the following steps:
and patterning the second grid material layer, the nitrogen-containing material layer and the oxide material layer to obtain the grid structure comprising an oxide layer, a nitrogen-containing layer and a grid layer which are overlapped from bottom to top.
In one embodiment, the thickness of the second gate material layer is greater than the thickness of the diffusion barrier material layer.
In one embodiment, the oxide material layer is formed on a substrate; the diffusion barrier material layer is formed on the surface of the oxidation material layer far away from the substrate.
In one embodiment, the resulting structure is nitrided using a remote plasma nitridation process or a decoupled plasma nitridation process.
In another aspect, the present application also provides, in accordance with some embodiments, a semiconductor structure comprising:
an oxide layer;
the nitrogen-containing layer is positioned on the surface of the oxide layer and is obtained by patterning a nitrogen-containing material layer; the nitrogen-containing material layer is obtained by nitriding a partial oxidation material layer under the protection of a diffusion barrier material layer.
In one embodiment, the semiconductor structure comprises a gate structure; the semiconductor structure further includes:
the diffusion barrier layer is positioned on the surface of the nitrogen-containing layer, which is far away from the oxide layer, and is obtained by patterning the diffusion barrier material layer;
the gate layer is positioned on the surface of the diffusion barrier layer far away from the nitrogen-containing layer;
the gate layer has a thickness greater than a thickness of the diffusion barrier layer.
In one embodiment, the semiconductor structure comprises a gate structure; the semiconductor structure further includes:
and the grid layer is positioned on the surface of the nitrogen-containing layer far away from the oxide layer.
In one embodiment, the diffusion barrier material layer and/or the gate layer comprises a polysilicon layer.
In one embodiment, the semiconductor structure further comprises a substrate;
the oxide layer is positioned on the surface of the substrate;
the nitrogen-containing layer is positioned on the surface of the oxide layer far away from the substrate.
The semiconductor structure and the preparation method thereof provided by the application have the following advantages:
according to the preparation method of the semiconductor structure, after the oxide material layer is formed, the diffusion barrier material layer is formed on the surface of the obtained structure, then the obtained structure is subjected to nitridation treatment, and nitrogen element doping is performed on the obtained structure, so that boron diffusion can be effectively blocked, and the NBTI effect caused by boron diffusion is reduced; moreover, the obtained structure is doped with nitrogen element, so that the semiconductor structure has low electric leakage, good thermal stability, low interface state density and excellent Bias Temperature Instability (BTI) characteristics.
Meanwhile, the preparation method of the semiconductor structure only enables a part of the oxidation material layer to be converted into the nitrogen-containing material layer, and due to the fact that the doping depth of nitrogen elements is smaller than the thickness of the oxidation material layer and the blocking effect of the diffusion blocking material layer, the nitrogen elements can be accurately controlled to be located on the upper surface of the oxidation material layer, the NBTI effect is reduced, and the reliability and the stability of the device performance are improved.
In the semiconductor structure provided by the application, the nitrogen-containing layer is obtained by patterning the nitrogen-containing material layer, and the nitrogen-containing material layer is obtained by performing nitridation treatment on a partial oxidation material layer under the protection of the diffusion barrier material layer, so that boron diffusion can be effectively avoided in the process of forming the nitrogen-containing layer, and the NBTI effect caused by boron diffusion is reduced; and the nitrogen-containing layer can also ensure that the semiconductor structure has low electric leakage, good thermal stability, low interface state density and excellent bias temperature instability characteristic.
Meanwhile, the nitrogen-containing layer is obtained by nitridation treatment under the protection of the diffusion barrier material layer, the barrier effect of the diffusion barrier material layer can effectively prevent nitrogen elements from diffusing and entering the device interface, the nitrogen elements are accurately controlled to be positioned on the upper surface of the oxide layer, the NBTI effect is reduced, and the reliability and the stability of the device performance are improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic cross-sectional view of a conventional semiconductor structure;
FIG. 2 is a flow chart of a method of fabricating a semiconductor structure provided in one embodiment of the present application;
fig. 3 is a schematic cross-sectional view of the structure obtained in step S1 in a method for manufacturing a semiconductor structure according to an embodiment of the present application;
fig. 4 is a schematic cross-sectional view of the structure obtained in step S2 in the method for manufacturing a semiconductor structure according to an embodiment of the present application;
fig. 5 is a schematic cross-sectional view of a structure obtained in step S3 in a method for manufacturing a semiconductor structure according to an embodiment of the present application;
fig. 6 is a schematic cross-sectional view of the structure obtained in step S4 in the method for manufacturing a semiconductor structure according to an embodiment of the present application;
fig. 7 is a schematic cross-sectional view of the structure obtained in step S5 in the method for manufacturing a semiconductor structure according to an embodiment of the present application, and fig. 7 is a schematic cross-sectional view of the semiconductor structure according to an embodiment of the present application;
FIG. 8 is a flow chart of a method of fabricating a semiconductor structure provided in another embodiment of the present application;
fig. 9 is a schematic cross-sectional view of the structure obtained in step S6 in the method for manufacturing a semiconductor structure according to an embodiment of the present application;
fig. 10 is a schematic cross-sectional view of the structure obtained in step S7 in a method for manufacturing a semiconductor structure according to an embodiment of the present application;
fig. 11 is a schematic cross-sectional view of the structure obtained in step S8 in the method for manufacturing a semiconductor structure according to an embodiment of the present application, and fig. 11 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present application.
Description of reference numerals:
1', a substrate; 2', a silicon oxide layer; 3', a silicon oxynitride layer; 4', a polysilicon gate; 1. a substrate; 2. a layer of an oxide material; 21. an oxide layer; 3. a diffusion barrier material layer; 31. a diffusion barrier layer; 4. a nitrogen-containing material layer; 41. a nitrogen-containing layer; 5. a second gate material layer; 51. a gate layer; 6. and (3) a grid structure.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on", other elements or layers, it can be directly on the other elements or layers, or intervening elements or layers may be present. It will be understood that, although the terms first, second, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention; for example, the first gate material layer may be referred to as a second gate material layer, and similarly, the second gate material layer may be referred to as a first gate material layer; the first gate material layer and the second gate material layer are different gate material layers, for example, the thickness of the second gate material layer is greater than the thickness of the first gate material layer, or the thickness of the first gate material layer is greater than the thickness of the second gate material layer.
Spatial relationship terms, such as "on.," over, "and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations from the shapes shown are to be expected, for example, due to manufacturing techniques and/or tolerances. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing techniques. Also, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
At present, the problems of breakdown of device oxide layer, leakage and Negative Bias Temperature Instability (NBTI) caused by boron (B) diffusion in polysilicon Gate (Poly Gate) are important factors that hinder the development of semiconductor integrated circuits. Nitrogen (N) has proven to be an effective barrier to boron diffusion, and in conventional techniques, nitridation of oxide layers, such as nitridation of a silicon oxide layer to form a silicon oxynitride layer, has significantly improved the above-mentioned problems. A conventional semiconductor structure is shown in fig. 1, and includes a substrate 1', a silicon oxide layer 2', a silicon oxynitride layer 3', and a polysilicon gate 4'. However, as the size of semiconductor devices is reduced, the thickness of the oxide layer is reduced, and nitrogen inevitably diffuses to the device interface, which results in serious NBTI problem, and thus it is difficult to precisely control the nitrogen on the upper surface of the oxide layer.
Referring to fig. 2, according to some embodiments, a method for fabricating a semiconductor structure is provided, comprising:
s1: forming an oxide material layer;
s2: forming a diffusion barrier material layer on the surface of the oxide material layer;
s3: nitriding the obtained structure so as to convert part of the oxide material layer into a nitrogen-containing material layer; the nitrogen-containing material layer is located between the diffusion barrier material layer and the remaining oxide material layer.
According to the preparation method of the semiconductor structure, after the oxide material layer is formed, the diffusion barrier material layer is formed on the surface of the obtained structure, then the obtained structure is subjected to nitridation treatment, and nitrogen element doping is performed on the obtained structure, so that boron diffusion can be effectively blocked, and the NBTI effect caused by boron diffusion is reduced; moreover, the obtained structure is doped with nitrogen element, so that the semiconductor structure has low electric leakage, good thermal stability, low interface state density and excellent Bias Temperature Instability (BTI) characteristics.
Meanwhile, the preparation method of the semiconductor structure only enables a part of the oxidation material layer to be converted into the nitrogen-containing material layer, and due to the fact that the doping depth of nitrogen elements is smaller than the thickness of the oxidation material layer and the blocking effect of the diffusion blocking material layer, the nitrogen elements can be accurately controlled to be located on the upper surface of the oxidation material layer, the NBTI effect is reduced, and the reliability and the stability of the device performance are improved.
In step S1, please refer to fig. 3 in conjunction with S1 in fig. 2, an oxide material layer 2 is formed.
Note that, the material of the oxide material layer 2 is not limited in the present application; in one example, the oxide material layer 2 may include, but is not limited to, silicon oxide (SiO) 2 ) A layer. Optionally, in other embodiments, the oxide material layer 2 may further include a high-k material layer, such as hafnium oxide (HfO) 2 ) Layer, tantalum oxide (Ta) 2 O 5 ) Layer, titanium oxide (TiO) 2 ) Layer or zirconium oxide (ZrO) 2 ) Layers, and the like; the preparation method of the semiconductor structure provided by the above embodiment can make the oxide material layer 2 have a thicker physical thickness through the high-k material layer, prevent tunneling current, and reduce gate leakage current.
Specifically, the manner of forming the oxide material layer 2 may include, but is not limited to, thermal oxidation, physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), plasma Enhanced CVD (PECVD), atomic Layer Deposition (ALD), or other suitable processes, and the manner of forming the oxide material layer 2 is not limited in this application.
With continued reference to fig. 3, in one embodiment, step S1 may include: a layer of oxide material 2 is formed on a substrate 1.
In one example, substrate 1 may include, but is not limited to, a silicon (Si) substrate, a silicon carbide (SiC) substrate, or sapphire (Al) 2 O 3 ) Substrate, etc., the material of the substrate 1 is not limited in the present application; specifically, in one of the embodiments, the substrate 1 includes a silicon substrate; since silicon is a good thermal conductor, the thermal conductivity of the device can be improved through the silicon substrate, and the service life of the device can be prolonged.
In step S2, please refer to fig. 4 in conjunction with S2 in fig. 2, a diffusion barrier material layer 3 is formed on the surface of the oxide material layer 2.
Alternatively, as shown in fig. 4, in an embodiment in which the oxide material layer 2 is formed on the substrate 1, the diffusion barrier material layer 3 is formed on the surface of the oxide material layer 2 away from the substrate 1.
Alternatively, the diffusion barrier material layer 3 may include, but is not limited to, a first gate material layer; of course, in other embodiments, any material layer that can act as a barrier to nitrogen during the subsequent nitridation process may be used as the diffusion barrier material layer 3.
In step S3, please refer to fig. 5 in combination with S3 of fig. 2, the obtained structure is nitrided, so that the partial oxide material layer 2 is transformed into the nitrogen-containing material layer 4; in particular, the nitrogen-containing material layer 4 may be located between the diffusion barrier material layer 3 and the remaining oxide material layer 2.
Referring to fig. 5, in one embodiment, step S3 may include the following steps:
nitriding the obtained structure to dope nitrogen elements into the oxide material layer 2 from the surface of the oxide material layer 2, which is in contact with the diffusion barrier material layer 3; the nitrogen element reacts with the partially oxidized material layer 2 to form a nitrogen-containing material layer 4.
It should be noted that the material of the nitrogen-containing material layer 4 is not limited in the present application; specifically, the nitrogen-containing material layer 4 may include, but is not limited to, a silicon oxynitride (SiON) layer; specifically, in an embodiment in which the oxide material layer 2 includes a silicon oxide layer, the nitrogen-containing material layer 4 includes a silicon oxynitride layer; in an embodiment where the layer of oxide material 2 comprises a hafnium oxide layer, the layer of nitrogen-containing material 4 comprises a hafnium oxynitride layer.
Optionally, in step S3, the obtained structure may be subjected to Nitridation processing by using, but not limited to, a Remote Plasma Nitridation process (RPN) or a Decoupled Plasma Nitridation process (DPN), and the like, and the Nitridation processing method in this application is not limited; specifically, in one embodiment, the structure is subjected to nitridation treatment by using a remote plasma nitridation process or a decoupled plasma nitridation process, and the method for manufacturing the semiconductor structure in the embodiment performs nitridation treatment on the structure by using the remote plasma nitridation process and the decoupled plasma nitridation process, so that the working environment is clean without special equipment for preventing pollution, and the cost can be reduced; since the ion nitriding method utilizes the ionized gas sputtering action, the treatment time can be significantly shortened as compared with the conventional nitriding treatment; even temperature distribution can be obtained without special heating and heat preservation equipment, the heating efficiency is higher compared with an indirect heating mode, and the energy-saving effect is achieved.
Referring to fig. 6 in conjunction with fig. 3, in an embodiment, the following step may be further included after step S3:
s4: a second gate material layer 5 is formed on the surface of the diffusion barrier material layer 3 away from the nitrogen-containing material layer 4.
It should be noted that the diffusion barrier material layer 3 and the second gate material layer 5 may include, but are not limited to, a polysilicon layer, a metal silicide layer, etc., and the material of the diffusion barrier material layer 3 and the second gate material layer 5 is not limited in this application.
Specifically, in one embodiment, the diffusion barrier material layer 3 comprises a polysilicon layer, and in another embodiment, the second gate material layer 5 comprises a polysilicon layer. Polysilicon is semiconductor in nature, so the polysilicon layer can change its work function by doping impurities with different polarities, and particularly, when the threshold voltage of a transistor is reduced, the work function of the polysilicon layer can be directly adjusted to meet the requirement; meanwhile, the melting point of polysilicon is higher than that of most metals, and the use of polysilicon layer in semiconductor process is used to deposit gate material at high temperature to improve device performance, so the upper limit of temperature used in the process can be increased.
In still another embodiment, the second gate material layer 5 includes a metal layer, and the use of the metal layer enables the second gate material layer 5 to have low resistivity and low gate resistance; at the same time, boron diffusion can be further blocked.
In one embodiment, the thickness of the second gate material layer 5 may be greater than the thickness of the diffusion barrier material layer 3, and the thickness of the diffusion barrier material layer 3 and the thickness of the second gate material layer 5 are not limited herein; specifically, when the ratio of the thickness of the second gate material layer 5 to the thickness of the diffusion barrier material layer 3 is greater than 3:1, the stability of the electrical performance of the device can be improved.
Referring to fig. 7 in conjunction with fig. 2, in an embodiment, the following step may be further included after step S4:
s5: the second gate material layer 5, the diffusion barrier material layer 3, the nitrogen-containing material layer 4 and the oxide material layer 2 are patterned to obtain a gate structure 6 including an oxide layer 21, a nitrogen-containing layer 41, a diffusion barrier layer 31 and a gate layer 51 stacked in sequence from bottom to top.
With reference to step S5, with continued reference to fig. 7, the second gate material layer 5, the diffusion barrier material layer 3, the nitrogen-containing material layer 4, and the oxide material layer 2 may be patterned by, but not limited to, a photolithography process to form a gate structure 6; specifically, the second gate material layer 5, the diffusion barrier material layer 3, the nitrogen-containing material layer 4, and the oxide material layer 2 may be patterned by photolithography and dry etching processes to form the gate structure 6.
It should be noted that, in some embodiments, the method for manufacturing a semiconductor structure provided herein may further remove the diffusion barrier material layer 3 on the surface of the oxide material layer 2 after performing nitridation treatment on the obtained structure so as to convert part of the oxide material layer 2 into the nitrogen-containing material layer 4, and then the following embodiments refer to a step including removing the diffusion barrier material layer 3 on the surface of the oxide material layer 2.
Referring to fig. 8 and 9, in one embodiment, the step S3 may include the following steps:
s6: the diffusion barrier material layer 3 is removed.
In step S6, please refer to fig. 5 and 9 in combination with S6 in fig. 8, the diffusion barrier material layer 3 is removed. Specifically, the diffusion barrier material layer 3 may be removed by, but not limited to, wet etching, dry etching or a grinding process, and the manner of removing the diffusion barrier material layer 3 is not limited in the present application.
Referring to fig. 8 to 10, in one embodiment, the following steps may be further included after step S6:
s7: and forming a second gate material layer on the surface of the nitrogen-containing material layer far away from the oxide material layer.
Specifically, referring to fig. 10, in one embodiment, step S7 may include: a second gate material layer 5 is formed on the surface of the nitrogen-containing material layer 4 away from the oxide material layer 2.
Referring to fig. 8 and fig. 11, in one embodiment, the following steps may be further included after step S7:
s8: the second gate material layer 5, the nitrogen-containing material layer 4 and the oxide material layer 2 are patterned to obtain a gate structure 6 including an oxide layer 21, a nitrogen-containing layer 41 and a gate layer 51 stacked from bottom to top.
Referring to fig. 11, in step S8, the oxide material layer 2, the nitrogen-containing material layer 4 and the second gate material layer 5 may be patterned by, but not limited to, a photolithography process to form a gate structure 6; specifically, the oxide material layer 2, the nitrogen-containing material layer 4, and the second gate material layer 5 may be patterned by photolithography and dry etching processes to form the gate structure 6.
With continuing reference to fig. 7, the present application further provides a semiconductor structure, according to some embodiments, including an oxide layer 21 and a nitrogen-containing layer 41; specifically, the nitrogen-containing layer 41 is located on the surface of the oxide layer 21 and is obtained by patterning the nitrogen-containing material layer 4; more specifically, the nitrogen-containing material layer 4 is obtained by nitriding the partially oxidized material layer 2 under the protection of the diffusion barrier material layer 3.
In the semiconductor structure provided by the above embodiment, since the nitrogen-containing layer is obtained by patterning the nitrogen-containing material layer, and the nitrogen-containing material layer is obtained by performing nitridation treatment on a part of the oxide material layer under the protection of the diffusion barrier material layer, boron diffusion can be effectively avoided in the process of forming the nitrogen-containing layer, and the NBTI effect caused by boron diffusion is reduced; and the nitrogen-containing layer can also ensure that the semiconductor structure has low electric leakage, good thermal stability, low interface state density and excellent bias temperature instability characteristic.
Meanwhile, the nitrogen-containing layer is obtained by nitridation treatment under the protection of the diffusion barrier material layer, the barrier effect of the diffusion barrier material layer can effectively prevent nitrogen elements from diffusing and entering the device interface, the nitrogen elements are accurately controlled to be positioned on the upper surface of the oxide layer, the NBTI effect is reduced, and the reliability and the stability of the device performance are improved.
In the present application, the material of the oxide layer 21 is not limited toLimiting; in one example, the oxide layer 21 may include, but is not limited to, silicon oxide (SiO) 2 ) And (3) a layer. Optionally, in other embodiments, the oxide layer 21 may further include a high-k material layer, such as a hafnium oxide layer, a tantalum oxide layer, a titanium oxide layer, or a zirconium oxide layer; the method for manufacturing the semiconductor structure provided by the above embodiment can make the oxide layer 21 have a thicker physical thickness through the high-k material layer, prevent tunneling current, and reduce gate leakage current.
Note that the material of the nitrogen-containing layer 41 is not limited in the present application; specifically, the nitrogen-containing layer 41 may include, but is not limited to, a silicon oxynitride (SiON) layer; specifically, in embodiments where the oxide layer 21 comprises a silicon oxide layer, the nitrogen-containing layer 41 comprises a silicon oxynitride layer; in particular, in embodiments where the oxide layer 21 comprises a hafnium oxide layer, the nitrogen containing layer 41 comprises a hafnium oxynitride layer.
In one embodiment, as shown in fig. 7, the semiconductor structure may include a gate structure 6; and may further include a diffusion barrier layer 31 and a gate layer 51.
Specifically, the diffusion barrier layer 31 is located on the surface of the nitrogen-containing layer 41 away from the oxide layer 21, and is obtained by patterning the diffusion barrier material layer 3; the gate layer 51 is located on the surface of the diffusion barrier layer 31 remote from the nitrogen-containing layer 41.
That is, on the basis of the above embodiment, the gate structure 6 may include the oxide layer 21, the nitrogen-containing layer 41, the diffusion barrier layer 31 and the gate layer 51 stacked in this order from bottom to top.
In one embodiment, the gate layer 51 may have a thickness greater than the thickness of the diffusion barrier layer 31; the thickness of the diffusion barrier layer 31 and the thickness of the gate layer 51 are not limited in the present application; specifically, when the ratio of the thickness of the gate layer 51 to the thickness of the diffusion barrier layer 31 is greater than 3:1, the stability of the electrical performance of the device can be improved.
Note that, in the semiconductor structure provided in some embodiments of the present application, the diffusion barrier layer 31 may not be included, and the following embodiments refer to the case where the diffusion barrier layer 31 is not included.
In one embodiment, as shown in fig. 11, the semiconductor structure may include a gate structure 6; a gate layer 51 may also be included.
Specifically, the gate layer 51 is located on the surface of the nitrogen-containing layer 41 away from the oxide layer 21.
That is, on the basis of the above embodiment, the gate structure 6 may include the oxide layer 21, the nitrogen-containing layer 41 and the gate layer 51 stacked from bottom to top.
In an example, the diffusion barrier layer 31 and/or the gate layer 51 may include, but are not limited to, a polysilicon layer, a metal silicide layer, and the like, and the materials of the diffusion barrier layer 31 and the gate layer 51 are not limited in this application; specifically, in one embodiment, the diffusion barrier layer 31 comprises a polysilicon layer, and in another embodiment, the gate layer 51 comprises a polysilicon layer. Polysilicon is semiconductor in nature, so the polysilicon layer can change its work function by doping impurities with different polarities, and particularly, when the threshold voltage of a transistor is reduced, the work function of the polysilicon layer can be directly adjusted to meet the requirement; meanwhile, the melting point of polysilicon is higher than that of most metals, and the use of polysilicon layer in semiconductor process is used to deposit gate material at high temperature to improve device performance, so the upper limit of temperature used in the process can be increased.
In yet another embodiment, the gate layer 51 includes a metal layer, and the use of the metal layer enables the gate layer 51 to have a low resistivity and a small gate resistance; at the same time, boron diffusion can be further blocked.
With continued reference to fig. 7, in one embodiment, a semiconductor structure is provided that further includes a substrate 1.
In one example, substrate 1 may include, but is not limited to, a silicon (Si) substrate, a silicon carbide (SiC) substrate, or sapphire (Al) 2 O 3 ) Substrate, etc., the material of the substrate 1 is not limited in the present application; specifically, in one embodiment, the substrate 1 includes a silicon substrate, and since silicon is a good thermal conductor, the thermal conductivity of the device can be improved and the service life of the device can be prolonged.
On the basis, as shown in fig. 7, in one embodiment, the oxide layer 21 is located on the surface of the substrate 1, and the nitrogen-containing layer 41 is located on the surface of the oxide layer 21 away from the substrate 1.
It should be understood that, although the steps in the flowcharts of fig. 3 and 8 are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 3 and 8 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or stages is not necessarily sequential, but may be performed alternately or alternately with other steps or at least some of the other steps or stages.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features of the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (15)
1. A method for manufacturing a semiconductor structure, comprising the steps of:
forming an oxide material layer;
forming a diffusion barrier material layer on the surface of the oxide material layer;
nitriding the obtained structure so as to convert part of the oxide material layer into a nitrogen-containing material layer; the nitrogen-containing material layer is positioned between the diffusion barrier material layer and the remaining oxide material layer.
2. The method for fabricating a semiconductor structure according to claim 1, wherein the step of performing a nitridation process on the resulting structure to convert a portion of the oxide material layer into a nitrogen-containing material layer comprises the steps of:
nitriding the obtained structure to dope nitrogen elements into the oxide material layer from the surface of the oxide material layer, which is in contact with the diffusion barrier material layer; the nitrogen element reacts with a portion of the oxide material layer to form the nitrogen-containing material layer.
3. The method of claim 1, wherein the diffusion barrier material layer comprises a first gate material layer;
after the nitridation treatment is carried out on the obtained structure so that part of the oxide material layer is converted into the nitrogen-containing material layer, the method further comprises the following steps:
and forming a second gate material layer on the surface of the diffusion barrier material layer far away from the nitrogen-containing material layer.
4. The method of claim 3, wherein the semiconductor structure comprises a gate structure;
after the step of forming the second gate material layer on the surface of the diffusion barrier material layer away from the nitrogen-containing material layer, the method further comprises the following steps:
and patterning the second grid material layer, the diffusion barrier material layer, the nitrogen-containing material layer and the oxidation material layer to obtain the grid structure which comprises an oxidation layer, a nitrogen-containing layer, a diffusion barrier layer and a grid layer which are sequentially overlapped from bottom to top.
5. The method for manufacturing a semiconductor structure according to claim 1, wherein the step of nitriding the resulting structure to convert a portion of the oxide material layer into a nitrogen-containing material layer further comprises:
and removing the diffusion barrier material layer.
6. The method of claim 5, wherein the diffusion barrier layer comprises a first gate material layer;
after the step of removing the diffusion barrier layer, the method further comprises the following steps:
and forming a second gate material layer on the surface of the nitrogen-containing material layer far away from the oxide material layer.
7. The method of claim 6, wherein the semiconductor structure comprises a gate structure;
after the step of forming the second gate material layer on the surface of the nitrogen-containing material layer away from the oxide material layer, the method further comprises the following steps:
and patterning the second grid material layer, the nitrogen-containing material layer and the oxide material layer to obtain the grid structure comprising an oxide layer, a nitrogen-containing layer and a grid layer which are overlapped from bottom to top.
8. The method of claim 7, wherein a thickness of the second gate material layer is greater than a thickness of the diffusion barrier material layer.
9. The method of claim 1, wherein the oxide material layer is formed on a substrate; the diffusion barrier material layer is formed on the surface of the oxidation material layer far away from the substrate.
10. The method of claim 1, wherein the nitridation process is performed on the resulting structure using a remote plasma nitridation process or a decoupled plasma nitridation process.
11. A semiconductor structure, comprising:
an oxide layer;
the nitrogen-containing layer is positioned on the surface of the oxide layer and is obtained by patterning a nitrogen-containing material layer; the nitrogen-containing material layer is obtained by nitriding a partial oxidation material layer under the protection of a diffusion barrier material layer.
12. The semiconductor structure of claim 11, wherein the semiconductor structure comprises a gate structure; the semiconductor structure further includes:
the diffusion barrier layer is positioned on the surface of the nitrogen-containing layer, which is far away from the oxide layer, and is obtained by patterning the diffusion barrier material layer;
the gate layer is positioned on the surface of the diffusion barrier layer far away from the nitrogen-containing layer;
the gate layer has a thickness greater than a thickness of the diffusion barrier layer.
13. The semiconductor structure of claim 11, wherein the semiconductor structure comprises a gate structure; the semiconductor structure further includes:
and the grid layer is positioned on the surface of the nitrogen-containing layer far away from the oxide layer.
14. The semiconductor structure of claim 12 or 13, wherein the diffusion barrier material layer and/or the gate layer comprises a polysilicon layer.
15. The semiconductor structure of claim 11, further comprising a substrate;
the oxide layer is positioned on the surface of the substrate;
the nitrogen-containing layer is positioned on the surface of the oxide layer far away from the substrate.
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