CN116072709B - Junction field effect transistor, manufacturing method thereof and chip - Google Patents

Junction field effect transistor, manufacturing method thereof and chip Download PDF

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CN116072709B
CN116072709B CN202310219500.3A CN202310219500A CN116072709B CN 116072709 B CN116072709 B CN 116072709B CN 202310219500 A CN202310219500 A CN 202310219500A CN 116072709 B CN116072709 B CN 116072709B
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doped region
doped
field effect
effect transistor
junction field
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CN116072709A (en
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何隽
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Smic Pioneer Integrated Circuit Manufacturing Shaoxing Co ltd
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Smic Pioneer Integrated Circuit Manufacturing Shaoxing Co ltd
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
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    • H01L29/66234—Bipolar junction transistors [BJT]
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/70—Bipolar devices
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    • H01L29/73—Bipolar junction transistors
    • H01L29/735—Lateral transistors

Abstract

The invention provides a junction field effect transistor and a manufacturing method thereof, and a chip.A doped region ring surrounding a third doped region (namely a channel) is formed between source and drain, so that the pinch-off voltage of the junction field effect transistor is determined by the line width of the third doped region in the radial direction (namely the inner diameter of the doped region ring in the direction) perpendicular to the axial direction and the thickness direction of a semiconductor substrate, and on the premise that the pinch-off voltage of JEFT in the radial direction is not higher than the pinch-off voltage of the JEFT in the thickness direction of the semiconductor substrate, the adjustable and controllable of the pinch-off voltage of a JFET can be successfully realized through the adjustable and controllable of the line width of the third doped region in the radial direction, thereby being beneficial to realizing the performances of the required JFET and the chip. Furthermore, even if the JFET is a parasitic integrated JFET on the existing 120V BCD and other BCD process platforms, the voltage of the pinch-off of the JFET can be regulated and controlled obviously.

Description

Junction field effect transistor, manufacturing method thereof and chip
Technical Field
The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a junction field effect transistor, a method for manufacturing the same, and a chip.
Background
BCD (Bipolar-CMOS-DMOS) technology is an important power integrated circuit manufacturing technology, which can integrate three different manufacturing technologies on the same chip, specifically, a Bipolar transistor (Bipolar Junction Transistor, BJT) for processing analog signals with high precision, a complementary metal oxide semiconductor transistor (Complementary Metal Oxide Semiconductor, CMOS) for designing a digital control circuit, a Double-diffused metal oxide semiconductor transistor (Double-diffused Metal Oxide Semiconductor, DMOS) for developing power supply and high-voltage switching devices, and various electronic components such as resistors, capacitors, diodes, and the like are integrated on the same chip. The various elements such as BJT, CMOS, DMOS integrated by Z in BCD can complement each other, and exert respective advantages, so that the chip as a whole has a plurality of advantages, for example: the method has the advantages of improving reliability, reducing electromagnetic interference, reducing chip area and the like, and has been widely used in the fields of mobile equipment, household appliances, displays, automobiles, data centers and the like.
A junction field effect transistor (Junction Field Effect Transistor, JFET) is a three-terminal active element with an amplifying function, which includes a gate (gate), a source (source), and a drain (drain) of a pn junction, and has the following advantages: (1) Having a very high input impedance, which allows a high degree of isolation between the input and output circuits; (2) no inherent noise of the valve and transistor; (3) Having a negative temperature coefficient, the risk of thermal runaway can be avoided; (4) Having a very high power gain can eliminate the necessity to use a driver stage. Therefore, JFETs are also parasitically integrated in some BCD chips, further improving chip performance.
The parasitic integrated JFET structure in the existing BCD chip is shown in fig. 1, and mainly comprises a P-type semiconductor substrate 7, a P-type epitaxial layer 6, an N-type second doped region 5, an N-type drain electrode 1 and an N-type source electrode 3 respectively located at two ends of the second doped region 5, a P-type first doped region 4, and a P-type doped gate electrode 2. The mask plates for manufacturing the structures of the JFET are the same mask plate for manufacturing the corresponding structures of the semiconductor transistors such as the CMOS in the chip, that is, the process for manufacturing the structures of the JFET and the process for manufacturing the corresponding structures of the semiconductor transistors such as the CMOS in the chip are the same process, and the parameters such as the depth, the doping concentration and the like of the structures of the JFET depend on the process parameters of the corresponding structures of the semiconductor transistors such as the CMOS in the chip.
In addition, when the drain-source voltage V of the JFET DS At a fixed value, the drain current I is controlled by the gate voltage D When the voltage is equal to a certain small current (for example, 50 mA), the channel is considered to be pinched off in the thickness direction of the semiconductor substrate, and the corresponding gate-source voltage is the pinch-off voltage Vp of the JFET. The pinch-off voltage Vp is a key parameter for measuring the characteristics of the JFET, and the JFET can be controlled to operate in a saturation region according to the pinch-off voltage Vp to ensure that the JFET can realize a desired amplification function.
The parasitic integrated JFET has a simple structure, but when the parasitic integrated JFET is integrated on a BCD process platform such as 120V, the pinch-off voltage Vp of the parasitic integrated JFET is completely dependent on the process parameters of the BCD process platform, which is uncontrollable due to the fact that the parameters such as the depth of the structure and the doping concentration depend on the process parameters of the BCD process platform, and is unfavorable for realizing the required JFET performance.
Disclosure of Invention
The invention aims to provide a Junction Field Effect Transistor (JFET), a manufacturing method thereof and a chip, and even if the JFET is parasitically integrated, the pinch-off voltage Vp of the JFET is adjustable and controllable, so that the required performance of the JFET and the chip can be realized.
In order to achieve the above object, the present invention provides a junction field effect transistor comprising the following structure:
a semiconductor substrate;
a doped region ring of a first conductivity type formed in the semiconductor substrate, an axial direction of the doped region ring being perpendicular to a thickness direction of the semiconductor substrate;
a second doped region of a second conductivity type formed in the semiconductor substrate outside both ends of the doped region ring in the axial direction;
a third doped region of the second conductivity type formed in the semiconductor substrate surrounded by the doped region ring and the second doped regions at both ends thereof;
a source of a second conductivity type formed in the second doped region at one end of the doped region ring and a drain of a second conductivity type formed in the second doped region at the other end of the doped region ring;
the grid electrode is formed in the surface layer of the doped region ring;
wherein the line width of the third doped region in the radial direction perpendicular to the axial direction and the thickness direction determines the pinch-off voltage required by the junction field effect transistor.
Optionally, the semiconductor substrate includes a base and an epitaxial layer of the first conductivity type formed on the base, and the doped region ring, the second doped region, and the third doped region are all formed in the epitaxial layer.
Optionally, the doped region ring includes an epitaxial layer located under the third doped region, and further includes:
first doped regions of the first conductivity type formed alternately in the radial direction in the semiconductor substrate on both sides of the third doped region; the method comprises the steps of,
a fourth doped region of the first conductivity type is formed in the epitaxial layer above the third doped region.
Optionally, the gate includes a doped region of the first conductivity type formed in a surface layer of the doped region ring.
Optionally, the pinch-off voltage required by the junction field effect transistor is a pinch-off voltage of the junction field effect transistor in the axial direction, and the pinch-off voltage of the junction field effect transistor in the thickness direction is not higher than the pinch-off voltage of the junction field effect transistor in the axial direction.
Optionally, the junction field effect transistor is a parasitic integrated junction field effect transistor on a chip, and each structure of the junction field effect transistor is formed synchronously when manufacturing a corresponding semiconductor element of the chip.
Optionally, the semiconductor element includes at least one of a bipolar transistor, a complementary metal oxide semiconductor transistor, a double diffused metal oxide semiconductor transistor, a resistor, a capacitor, and a diode.
Optionally, the pinch-off voltage required by the junction field effect transistor is within a range of-0.5V to-11V.
Based on the same inventive concept, the invention also provides a chip comprising the junction field effect transistor.
Based on the same inventive concept, the invention also provides a manufacturing method of the junction field effect transistor, which comprises the following steps:
s1, providing a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate is provided with a region to be doped, a doped region ring is to be formed in the region to be doped, and the axial direction of the region to be doped is perpendicular to the thickness direction of the semiconductor substrate;
s2, forming first doped regions of first conductivity type in the regions to be doped in an alternate arrangement, and forming second doped regions of second conductivity type in the semiconductor substrate outside the two ends of the regions to be doped in the axial direction;
s3, forming a third doped region of a second conductivity type in the region to be doped between adjacent first doped regions;
s4, forming a fourth doped region of a first conductivity type in the region to be doped between adjacent first doped regions and above the third doped region, wherein the fourth doped region, the first doped region and the semiconductor substrate below the third doped region in the region to be doped form a doped region ring surrounding the third doped region, and the linewidth of the third doped region in the radial direction perpendicular to the axial direction and the thickness direction determines the required pinch-off voltage of the junction field effect transistor;
s5, forming a source electrode, a drain electrode and a grid electrode, wherein the source electrode is formed in the second doped region at one end of the doped region ring, the drain electrode is formed in the second doped region at the other end of the doped region ring, and the grid electrode is formed in the surface layer of the doped region ring.
Optionally, an impurity implantation of the first conductivity type is performed in the surface layer of the doped region ring to form the gate.
Optionally, the junction field effect transistor is a parasitic integrated junction field effect transistor on a chip, and the steps S1 to S5 are completed in synchronization with the manufacturing steps of the corresponding semiconductor element in the chip, respectively.
Optionally, the semiconductor element comprises at least one semiconductor transistor of a bipolar transistor, a complementary metal oxide semiconductor transistor and a double-diffusion metal oxide semiconductor transistor, and each manufacturing step of the semiconductor transistor is realized by adopting a BCD (binary coded decimal) process.
Compared with the prior art, the Junction Field Effect Transistor (JFET) and the manufacturing method and the chip thereof form the doped region ring surrounding the third doped region (namely the channel) between the source electrode and the drain electrode, so that the pinch-off voltage of the junction field effect transistor is determined by the line width of the third doped region (namely the inner diameter of the doped region ring in the direction) in the radial direction perpendicular to the axial direction and the thickness direction of the semiconductor substrate, and the JEFT can successfully realize the adjustable and controllable pinch-off voltage by the adjustable and controllable line width of the third doped region on the premise that the pinch-off voltage of the JEFT in the radial direction is not higher than the pinch-off voltage of the JEFT in the thickness direction of the semiconductor substrate, thereby being beneficial to realizing the performances of the required JFET and the chip. Furthermore, even if the JFET is a parasitic integrated JFET on the existing 120V BCD and other BCD process platforms, the voltage of the pinch-off of the JFET can be regulated and controlled obviously.
Drawings
Those of ordinary skill in the art will appreciate that the figures are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention. Wherein:
fig. 1 is a schematic diagram of a structure of a conventional JFET.
Fig. 2 is a schematic perspective view of a JFET according to an embodiment of the present invention.
Fig. 3 is a schematic cross-sectional structure along the Cutline Y direction (i.e., the axial direction of the doped region ring) in fig. 2.
Fig. 4 is a schematic cross-sectional structure along the Cutline X direction (i.e., a radial direction of the doped region ring, which is perpendicular to its axial Cutline Y and the thickness direction Z of the semiconductor substrate) in fig. 2.
FIG. 5 shows drain current I of JFET of an embodiment of the invention at different N-Width D Gate voltage Vg schematic.
Fig. 6 is a flow chart of a method for fabricating a JFET according to an embodiment of the present invention.
Fig. 7 is a schematic diagram of a device structure in a method for manufacturing a JFET according to an embodiment of the present invention.
Wherein reference numerals in the drawings are as follows:
1-a drain electrode; a 2-gate; 3-source; 4-a first doped region; 5-a second doped region; 6-an epitaxial layer; 7-a substrate; 8-fourth doped region; 9-a third doped region; 10-island region.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without one or more of these details. In other instances, well-known features have not been described in detail in order to avoid obscuring the invention. It should be understood that the present invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout. It will be understood that when an element is referred to as being "connected to," "coupled to" another element, it can be directly connected to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected to" another element, there are no intervening elements present. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
The technical scheme provided by the invention is further described in detail below with reference to the attached drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Referring to fig. 2 to 4, an embodiment of the present invention provides a junction field effect transistor, which includes a semiconductor substrate of a first conductivity type, a ring of doped regions of the first conductivity type, a second doped region 5 of a second conductivity type, a third doped region 9 of the second conductivity type, a source 3 of the second conductivity type, a drain 1 of the second conductivity type, and a gate 2 of the first conductivity type.
Wherein the second conductivity type is N-type when the first conductivity type is P-type, and P-type when the first conductivity type is N-type.
In this embodiment, the bulk material of the semiconductor substrate may be any suitable semiconductor material known in the art, such as silicon, silicon-on-insulator, germanium, silicon carbide, gallium arsenide, gallium indium, and the like. The semiconductor substrate may be a bulk structure or a stacked structure formed of a base 7 of the first conductivity type and an epitaxial layer 6 of the first conductivity type formed on the base 7 as shown in fig. 2. The doped region ring, the third doped region 9, the source 3, the drain 1 and the gate 2 are all formed on the basis of the epitaxial layer 6.
The doped region ring is formed in the epitaxial layer 6, the axial direction Y of the doped region ring is perpendicular to the thickness direction Z of the epitaxial layer 6, the second doped region 5 is formed in the epitaxial layer 6 outside two ends of the doped region ring in the axial direction Y, the third doped region 9 is formed in the epitaxial layer 6 jointly surrounded by the doped region ring and the second doped regions 5 at two ends of the doped region ring, namely, the doped region ring completely surrounds the third doped region 9 at the moment, the source electrode 3 is formed in the second doped region 5 at one end of the doped region ring, the drain electrode 1 is formed in the second doped region 5 at the other end of the doped region ring, and the grid electrode 2 is formed in the surface layer of the doped region ring. The linewidth N-Width of the third doped region 9 in a radial direction X perpendicular to the axial direction Y and the thickness direction Z (i.e. the inner diameter of the doped region ring in this direction, and also the spacing between the two first doped regions 4) determines the pinch-off voltage Vp required for the JFET.
In this embodiment, the doped region ring is composed of the epitaxial layer 6 below the bottom of the third doped region 9 and the first doped region 4 on both sides thereof and the fourth doped region 8 above the third doped region 9, and the epitaxial layers 6 below the bottoms of the first doped region 4, the fourth doped region 8 and the third doped region 9 are all doped regions of the first conductivity type, so that the fourth doped region 8 and the first doped region 4 on both sides thereof and the epitaxial layer 6 below the third doped region 9 surround the third doped region 9 to form a fully-surrounding channel structure. Furthermore, the body implant dose of the first conductivity type impurity in the epitaxial layer 6, the first doped region 4, the fourth doped region 8 and the gate sequentially increases, for example, the body implant dose of the first conductivity type impurity in the epitaxial layer 6 is on the order of 10 15 /cm 3 The bulk implant dose of the impurity of the first conductivity type in the first doped region 4 and the fourth doped region 8 is of the order of 10 16 /cm 3 。
In this embodiment, the bottom depth of the third doped region 9 is shallower than the bottom depth of the second doped region 5, and the bottom depth of the first doped region 4 may be flush with the bottom depth of the second doped region 5 or flush with the bottom depth of the third doped region 9. The top surfaces of the fourth doped region 8, the first doped region 4 and the second doped region 5 are flush with the top surface of the epitaxial layer 6. The implantation boundaries of the fourth doped region 8 and the third doped region 9 are aligned in both the radial X-direction and the axial Y-direction. That is, the implantation depth of the fourth doped region 8 and the third doped region 9 is different, but the implantation area is equivalent. In other embodiments of the present invention, the implantation area of the fourth doped region 8 may be made larger or smaller than the implantation area of the third doped region 9 according to the device performance requirements.
The doping concentration of the second conductivity type impurity in the drain 1 and the source 3 is greater than the doping concentration of the second conductivity type impurity in the second doping region 5. When the first conductivity type is P-type and the second conductivity type is N-type, the drain electrode 1 and the source electrode 3 are both N-type heavily doped with respect to the second doped region 5, the epitaxial layer 6 is P-type lightly doped with respect to the first doped region 4, and the gate electrode 2 is P-type heavily doped with respect to the first doped region 4. The P-type impurity is, for example, boron, indium, gallium, boron fluoride, etc., and the N-type impurity is, for example, arsenic, germanium, antimony, etc.
It should be understood that when the JFET of the present embodiment is fabricated by using a relatively independent mask, parameters such as doping concentration, depth, area, etc. of the semiconductor substrate, the first doped region 4, the second doped region 5, the third doped region 9, the fourth doped region 8, the source 3, the drain 1, and the gate 2 can be reasonably set according to the performance requirements of the JFET.
However, when the JFET of the present embodiment is a parasitically integrated JFET, the JFET is fabricated without a separate mask, specifically on a process platform such as BCD, and is fabricated on the semiconductor substrate simultaneously during the fabrication of the semiconductor transistor (BJT, CMOS DMOS) thereon, that is, during the fabrication of the corresponding structure of the semiconductor transistor (BJT, CMOS DMOS), along with the fabrication of the corresponding structure of the JFET, the depth, doping concentration, etc. of the corresponding structure of the JFET are all dependent on the parameter requirements of the corresponding structure of the semiconductor transistor. For example, the epitaxial layer 6 of the JFET is the same epitaxial layer when manufacturing the semiconductor transistor, and the doping concentration, thickness and other parameters of the epitaxial layer 6 are completely dependent on the process parameter setting of the semiconductor transistor; the second doped region 5 and the second conductive type well of the semiconductor transistor are the same ion implantation process, the first doped region 4 and the first conductive type well of the semiconductor transistor are the same ion implantation process, the third doped region 9 and the channel of the semiconductor transistor are the same ion implantation process, the fourth doped region 8 and the first conductive type contact region of the semiconductor transistor are the same ion implantation process, the source electrode 3, the drain electrode 1 and the source electrode drain ion implantation of the second conductive type of the semiconductor transistor are the same ion implantation process, and the gate electrode 2 and the gate electrode implantation of the semiconductor transistor are the same ion implantation process.
Referring to fig. 4, in this embodiment, since a doped region ring (i.e. the structure of the first conductivity type formed by the epitaxial layer 6 under the bottom of the third doped region 9 and the first doped region 4 on both sides thereof and the fourth doped region 8 above the third doped region 9) is formed around the third doped region 9, after the corresponding gate-source voltage is applied, the Width of the depletion layer (as shown by the up-down arrow in fig. 4) can be changed from the thickness direction (i.e. the Z direction) of the semiconductor substrate, and the Width of the depletion layer (as shown by the left-right arrow in fig. 4) can be changed from the axial direction (i.e. the X direction) of the doped ring region, and when the channel is pinched off in the axial direction (i.e. the X direction) of the doped ring region, the pinch-off voltage of the JFET is dependent on the line Width N-Width of the third doped region 9 in the axial direction (i.e. the X direction) of the doped ring region.
That is, when the doping concentrations of the first doping region 4, the second doping region 5, the third doping region 9, the fourth doping region 8, the source 3, the drain 1, and the gate 2, and the depth in the Z direction are determined, and the channel of the JFET is pinched off in the X direction before it is pinched off in the Z direction, the magnitude of the pinching-off voltage of the JFET can be changed by controlling the magnitude of the line Width N-Width of the third doping region 9 in the axial direction (i.e., the X direction) of the doping ring region (i.e., the inner diameter of the doping ring in the direction, that is, the distance between the two first doping regions 4). The larger the line Width N-Width, the larger the absolute value of the pinch-off voltage Vp. The line Width N-Width of the third doped region 9 (i.e. the inner diameter of the doped region ring in this direction, and also the spacing between the two first doped regions 4) is precisely controlled and adjusted in the process, so that the pinch-off voltage of the junction field effect transistor can be precisely controlled and adjusted within a desired range.
Taking the drain electrode 1, the source electrode 3, the second doped region 5 and the third doped region 9 as N-type, the first doped region 4, the fourth doped region 8, the epitaxial layer 6 and the substrate 7 as P-type, a negative voltage (i.e. gate-source voltage V) is applied between the gate electrode 2 and the source electrode 3 GS < 0), reverse biasing the pn junction between gate 2 and source 3, gate current I G Approximately 0, the JFET presents a very high input resistance, and a positive voltage is applied between the drain 1 and the source 3 (i.e. drain-source voltage V DS > 0) to make majority carrier electrons in the channel drift from the source 3 to the drain 1 under the action of the electric field to form drain current I D . At drain-source voltage V DS When the voltage is fixed, the voltage V of the gate source is controlled GS Can control drain current I D 。
Please refer to fig. 4 and 5, assume that the drain-source voltage V DS =0. When the gate-source voltage V GS When=0, the channel is wider and the channel resistance is smaller. When V is GS <0 and |V GS When the voltage is increased, the pn junction between the gate 2 and the source 3 and the pn junction depletion layer between the gate 2 and the drain 1 are widened by the reverse bias voltage, and the voltage is increased with the voltage of |V GS The increase in i expands the depletion layer mainly into the channel, narrowing the channel and increasing the channel resistance, as indicated by the up-down arrow and the left-right arrow in fig. 4. When |V GS When the I is further increased to a certain value, depletion layers on the left side and the right side are folded at the center of the channel, the channel is pinched off in the X direction, and the drain current I is obtained D Will also be zero. Gate-source voltage V at this time GS The pinch-off voltage Vp.
Referring to fig. 5, when the JFET is a parasitic integrated JFET on a 120VBCD process platform and the first conductivity type is P-type and the second conductivity type is N-type, when the pinch-off voltage of the corresponding parasitic integrated JFET in the prior art is about-17V, the larger the line Width N-Width is, the larger the absolute value of the pinch-off voltage Vp is, the variation of the line Width N-Width from the minimum value allowed by the process to the maximum value is regulated, and the pinch-off voltage Vp of the obtained parasitic integrated JET can be regulated and controlled within the range of-0.5 to-11V.
The junction field effect transistor of this embodiment mainly adopts a structure in which the corresponding doped ring region surrounds the four sides of the third doped region 9 (the channel for forming the JFET), and under the BCD process conditions of the existing 120V BCD process platform and the like, the Width N-Width of the third doped region 9 in the radial X direction (i.e., the direction perpendicular to the thickness direction Z of the substrate and the axial Y of the doped ring region) is adjustable and controllable in the BCD process, so that the adjustment and controllability of the pinch-off voltage of the JFET can be successfully realized, thereby being beneficial to realizing the performance of the required JFET and the chip in which the JFET is located.
It should be appreciated that the junction field effect transistor of the present embodiment may include any other desired conventional structure besides the structure shown in fig. 2 to 4, for example, the junction field effect transistor further includes: at least one metal line (not shown) electrically connected to at least one of the source electrode 3, the drain electrode 1 and the gate electrode 2 through corresponding contact holes (not shown); a field oxide layer formed on the top surface of a partial region of the epitaxial layer 6; and an insulating dielectric layer (not shown) formed on the top surface of the epitaxial layer 6 and sandwiched between the epitaxial layer 6 and the corresponding metal lines, through which contact holes between the metal lines and the source electrode 3, the drain electrode 1 and the gate electrode 2 pass.
Based on the same inventive concept, please refer to fig. 2 to fig. 4, the present embodiment also provides a chip including a Junction Field Effect Transistor (JFET) as described in the present embodiment.
The chip of the present embodiment is a chip formed using BCD process, and may further include at least one semiconductor transistor of bipolar transistor (BJT), complementary metal oxide semiconductor transistor (CMOS) and double diffused metal oxide semiconductor transistor (DMOS), which are integrated on the same semiconductor substrate together with the junction field effect transistor by BCD process, for example, formed together in epitaxial layer 6.
Optionally, the chip may further include at least one of a resistor, a capacitor, and a diode.
The chip of the embodiment integrates the Junction Field Effect Transistor (JFET) of the embodiment, so that the pinch-off voltage of the junction field effect transistor can be controlled and regulated to meet the requirement of chip performance.
Based on the same inventive concept, please refer to fig. 6, the present embodiment further provides a method for manufacturing a junction field effect transistor, which includes the following steps:
s1, providing a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate is provided with a region to be doped, a doped region ring is to be formed in the region to be doped, and the axial direction of the region to be doped is perpendicular to the thickness direction of the semiconductor substrate;
s2, forming first doped regions of first conductivity type in the regions to be doped in an alternate arrangement, and forming second doped regions of second conductivity type in the semiconductor substrate outside the two ends of the regions to be doped in the axial direction;
s3, forming a third doped region of a second conductivity type in the region to be doped between adjacent first doped regions;
s4, forming a fourth doped region of a first conductivity type in the region to be doped between adjacent first doped regions and above the third doped region, wherein the fourth doped region, the first doped region and the semiconductor substrate below the third doped region in the region to be doped form a doped region ring surrounding the third doped region, and the linewidth of the third doped region in the radial direction perpendicular to the axial direction and the thickness direction determines the required pinch-off voltage of the junction field effect transistor;
s5, forming a source electrode, a drain electrode and a grid electrode, wherein the source electrode is formed in the second doped region at one end of the doped region ring, the drain electrode is formed in the second doped region at the other end of the doped region ring, and the grid electrode is formed in the surface layer of the doped region ring.
Taking the first conductivity type as P-type and the second conductivity type as N as an example, only the structure in the region related to the JFET of the present invention is shown in fig. 7, but it is not shown that there is no other device region on the semiconductor substrate of the present invention except the region of the JFET to be manufactured.
Referring to fig. 2 to 4 and 7 (a), in step S1, a P-type epitaxial layer 6 may be grown on a P-type substrate 7, thereby obtaining a desired semiconductor substrate. This step may be performed on a BCD process platform, i.e. the epitaxial layer 6 may be an epitaxial layer required for manufacturing other semiconductor devices (e.g. at least one of a bipolar transistor, a complementary metal oxide semiconductor transistor, a double diffused metal oxide semiconductor transistor), which will not be described here. The epitaxial layer 6 has a region to be doped (not marked) in which a subsequently desired ring of doped regions is to be formed, the axial direction Y of which is perpendicular to the thickness direction Z of the epitaxial layer 6.
Referring to fig. 2 to 4 and 7 (B), in step S2, an N-type second doped region 5, a P-type first doped region 4 and an N-type third doped region 9 are formed on the P-type epitaxial layer 6 by a corresponding ion implantation process. The two first doped regions 4 are alternately arranged in the to-be-doped region, the two second doped regions 5 are respectively positioned in the epitaxial layers 6 at the outer sides of the two ends of the to-be-doped region in the axial direction, and the third doped region 9 is positioned in the epitaxial layers 6 of the to-be-doped region sandwiched by the two first doped regions 4 and the two second doped regions 5. This step may be performed on a BCD process platform, i.e. the N-type second doped region 5, the P-type first doped region 4 and the N-type third doped region 9 may be formed together with the fabrication of the corresponding doped regions required for other semiconductor elements (e.g. at least one of a bipolar transistor, a complementary metal oxide semiconductor transistor, a double diffused metal oxide semiconductor transistor) by means of corresponding reticles, which are not described here again.
Referring to fig. 2 to 4 and fig. 7 (C), in step S3, a P-type fourth doped region 8 with an implantation area equivalent to that of the P-type fourth doped region 9 and a depth shallower is formed in the region to be doped on the N-type third doped region by a corresponding ion implantation process. This step may be performed on a BCD process platform, i.e. the fourth doped region 8 may be formed together with the fabrication of the corresponding P-type doped region required for other semiconductor elements (e.g. at least one of a bipolar transistor, a complementary metal oxide semiconductor transistor, a double diffused metal oxide semiconductor transistor) by a corresponding reticle, which is not described here again. The epitaxial layer 6 under the fourth doped region 8, the first doped region 4 and the third doped region 9 constitutes a doped region ring surrounding the third doped region 9, and the Width N-Width of the third doped region 9 in the radial X direction perpendicular to the axial direction Y and the thickness direction Z (i.e. the inner diameter of the doped region ring in this direction, also the distance between the two first doped regions 4) determines the magnitude of the pinch-off voltage of the JFET to be formed.
Referring to fig. 2 to 4 and fig. 7 (D), in step S4, a heavily doped N-type drain electrode 1 and a heavily doped N-type source electrode 3 are formed on the N-type second doped region and a heavily doped P-type gate electrode 2 is formed on the P-type first doped region 4 and the P-type fourth doped region 8 by a corresponding ion implantation process. This step may be performed on a BCD process platform, i.e. the drain 1, the source 3 and the gate 3 may be formed together with the fabrication of the corresponding drain 1, the source 3 and the gate 3, respectively, required for other semiconductor elements (e.g. at least one of a bipolar transistor, a complementary metal oxide semiconductor transistor, a double diffused metal oxide semiconductor transistor) by corresponding reticles, which are not described here again.
It should be understood that, in the above manufacturing method, when the JFET to be manufactured is a parasitic integrated JFET on a chip, the steps S1 to S5 are completed in synchronization with the manufacturing steps of the corresponding semiconductor devices in the chip, respectively, which is not described herein. The semiconductor element may include at least one semiconductor transistor of a bipolar transistor, a complementary metal oxide semiconductor transistor and a double-diffused metal oxide semiconductor transistor, and each manufacturing step of the semiconductor transistor is realized by adopting a BCD (binary coded decimal) process.
The above manufacturing method may further continue to perform subsequent conventional process steps after S5 is performed, including: first, an oxide layer (e.g., low temperature oxide LTO, etc.) may be deposited on the surface of the device structure formed with the doped region ring, the third doped region 9, the source electrode 3, the drain electrode 1, and the gate electrode 2 by using Low Pressure Chemical Vapor Deposition (LPCVD), plasma enhanced chemical deposition (PECVD), etc.; then, a metal layer can be deposited on the oxide layer by adopting a sputtering process and the like, and the metal layer is photoetched; next, an interlayer insulating dielectric (ILD) is grown on the metal layer and the oxide layer, and the ILD is etched and etched to form a lead hole, etc., which will not be described herein.
In summary, the technical scheme of the invention can successfully realize that the pinch-off voltage Vp of the parasitic JFET device is adjustable and controllable under the condition of the existing 120VBCD and other process platforms.
The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention in any way, and any changes and modifications made by those skilled in the art in light of the foregoing disclosure will be deemed to fall within the scope and spirit of the present invention.

Claims (12)

1. A junction field effect transistor comprising the structure:
a semiconductor substrate of a first conductivity type;
a doped region ring of a first conductivity type formed in the semiconductor substrate, an axial direction of the doped region ring being perpendicular to a thickness direction of the semiconductor substrate;
a second doped region of a second conductivity type formed in the semiconductor substrate outside both ends of the doped region ring in the axial direction;
a third doped region of the second conductivity type formed in the semiconductor substrate surrounded by the doped region ring and the second doped regions at both ends thereof;
a source of a second conductivity type formed in the second doped region at one end of the doped region ring and a drain of a second conductivity type formed in the second doped region at the other end of the doped region ring;
the grid electrode is formed in the surface layer of the doped region ring;
the line width of the third doped region in the radial direction perpendicular to the axial direction and the thickness direction determines the pinch-off voltage required by the junction field effect transistor, the bottom depth of the third doped region is shallower than the bottom depth of the second doped region, and the top depth of the third doped region is deeper than the top depth of the second doped region;
moreover, the doped region ring includes: a semiconductor substrate located under the third doped region; first doped regions of the first conductivity type formed alternately in the radial direction in the semiconductor substrate on both sides of the third doped region; and a fourth doped region of the first conductivity type formed in the semiconductor substrate above the third doped region;
the doping concentrations of the first doping region, the second doping region, the third doping region, the fourth doping region and the gate electrode and the depth in the thickness direction are such that the channel of the junction field effect transistor is pinched off in the thickness direction before it is pinched off in the axial direction.
2. The junction field effect transistor of claim 1, wherein the semiconductor substrate comprises a base and an epitaxial layer of the first conductivity type formed on the base, the doped region ring, the second doped region, and the third doped region being formed in the epitaxial layer.
3. The junction field effect transistor of claim 1, wherein the gate includes a doped region of the first conductivity type formed in a surface layer of the doped region ring.
4. The junction field effect transistor according to claim 1, wherein a pinch-off voltage required for the junction field effect transistor is a pinch-off voltage of the junction field effect transistor in the axial direction, and the pinch-off voltage of the junction field effect transistor in the thickness direction is not higher than the pinch-off voltage of the junction field effect transistor in the axial direction.
5. The junction field effect transistor according to any of claims 1-4, wherein the junction field effect transistor is an on-chip parasitically integrated junction field effect transistor, each structure of the junction field effect transistor being formed simultaneously when fabricating a respective semiconductor element of the chip.
6. The junction field effect transistor of claim 5, wherein the semiconductor element comprises at least one of a bipolar transistor, a complementary metal oxide semiconductor transistor, a double diffused metal oxide semiconductor transistor, a resistor, a capacitor, and a diode.
7. The junction field effect transistor of claim 5, wherein a pinch-off voltage required for the junction field effect transistor is in the range of-0.5V to-11V.
8. A chip comprising a junction field effect transistor according to any one of claims 1 to 7.
9. A method of manufacturing a junction field effect transistor, comprising the steps of:
s1, providing a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate is provided with a region to be doped, a doped region ring is to be formed in the region to be doped, and the axial direction of the region to be doped is perpendicular to the thickness direction of the semiconductor substrate;
s2, forming first doped regions of first conductivity type in the regions to be doped in an alternate arrangement, and forming second doped regions of second conductivity type in the semiconductor substrate outside the two ends of the regions to be doped in the axial direction;
s3, forming a third doped region of a second conductivity type in the region to be doped between the adjacent first doped regions, wherein the bottom depth of the third doped region is shallower than the bottom depth of the second doped region, and the top depth of the third doped region is deeper than the top depth of the second doped region;
s4, forming a fourth doped region of a first conductivity type in the region to be doped between adjacent first doped regions and above the third doped region, wherein the fourth doped region, the first doped region and the semiconductor substrate below the third doped region in the region to be doped form a doped region ring surrounding the third doped region, and the linewidth of the third doped region in the radial direction perpendicular to the axial direction and the thickness direction determines the required pinch-off voltage of the junction field effect transistor;
s5, forming a source electrode, a drain electrode and a grid electrode, wherein the source electrode is formed in the second doped region at one end of the doped region ring, the drain electrode is formed in the second doped region at the other end of the doped region ring, and the grid electrode is formed in the surface layer of the doped region ring;
the doping concentrations of the first doping region, the second doping region, the third doping region, the fourth doping region and the gate and the depth in the thickness direction enable the channel of the junction field effect transistor to be pinched off in the thickness direction before the channel of the junction field effect transistor in the axial direction.
10. The method of manufacturing a junction field effect transistor according to claim 9, wherein impurity implantation of a first conductivity type is performed in a surface layer of the doped region ring, forming the gate electrode.
11. The method of claim 9, wherein the junction field effect transistor is a parasitic integrated junction field effect transistor on a chip, and steps S1 to S5 are completed in synchronization with the steps of fabricating the corresponding semiconductor device in the chip, respectively.
12. The method of claim 11, wherein the semiconductor device comprises at least one of a bipolar transistor, a complementary metal oxide semiconductor transistor, and a double diffused metal oxide semiconductor transistor, and each of the semiconductor transistor fabrication steps is performed using a BCD process.
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