CN116072520A - Method for preparing semiconductor substrate - Google Patents
Method for preparing semiconductor substrate Download PDFInfo
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- CN116072520A CN116072520A CN202310201762.7A CN202310201762A CN116072520A CN 116072520 A CN116072520 A CN 116072520A CN 202310201762 A CN202310201762 A CN 202310201762A CN 116072520 A CN116072520 A CN 116072520A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 184
- 239000000758 substrate Substances 0.000 title claims abstract description 62
- 238000000034 method Methods 0.000 title claims abstract description 44
- 239000000463 material Substances 0.000 claims abstract description 172
- 239000002131 composite material Substances 0.000 claims abstract description 28
- 238000007517 polishing process Methods 0.000 claims abstract description 13
- 238000009210 therapy by ultrasound Methods 0.000 claims abstract description 9
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 28
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 26
- 238000005498 polishing Methods 0.000 claims description 15
- 230000008569 process Effects 0.000 claims description 9
- 229910002601 GaN Inorganic materials 0.000 claims description 6
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 6
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 6
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 claims description 6
- 229910001195 gallium oxide Inorganic materials 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 230000002708 enhancing effect Effects 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 17
- 239000010410 layer Substances 0.000 description 36
- 239000013078 crystal Substances 0.000 description 8
- 238000005520 cutting process Methods 0.000 description 7
- 238000010521 absorption reaction Methods 0.000 description 3
- 238000000227 grinding Methods 0.000 description 3
- 230000006911 nucleation Effects 0.000 description 3
- 238000010899 nucleation Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 239000010959 steel Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000003763 carbonization Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/0475—Changing the shape of the semiconductor body, e.g. forming recesses
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
- H01L2221/68386—Separation by peeling
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The present invention provides a method of preparing a semiconductor substrate, comprising: bonding a first semiconductor material sheet and a second semiconductor material sheet to form a composite substrate sheet; performing laser scanning treatment on the first semiconductor material sheet so as to form a microcrack enrichment region in a preset region to be cut in the first semiconductor material sheet; carrying out ultrasonic treatment on the composite substrate sheet to expand cracks in the microcrack enrichment region and separate the composite substrate sheet so as to obtain a first component and a second component, wherein the first component carries a second semiconductor material sheet and contains a first semiconductor material residual layer; a surface of a residual layer of the first semiconductor material in the first member is subjected to a polishing process so as to obtain a semiconductor substrate. Therefore, the method can rapidly cut and separate the composite substrate slice through laser scanning treatment and ultrasonic treatment, has the advantages of high processing rate, high production efficiency and less material loss, and can reduce the production cost of the semiconductor substrate.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a method for preparing a semiconductor substrate.
Background
With the development of semiconductor technology, the requirements for preparing the semiconductor substrate with the basic structure of the semiconductor device are also higher and higher, but the existing preparation method of the semiconductor substrate has the problem of high production cost.
Accordingly, there is a need for improvements in methods of preparing semiconductor substrates.
Disclosure of Invention
The present invention has been made based on the findings and knowledge of the inventors regarding the following facts and problems:
the existing preparation method of the semiconductor substrate has the problem of high production cost. Taking silicon carbide (SiC) substrate as an example, silicon carbide crystal is very difficult to manufacture, and has high manufacturing cost, and the Physical Vapor Transport (PVT) method adopted in the industry currently has a growth temperature of 2300 ℃, a growth speed of very slow (hundreds of micrometers/hour), and high production cost. The manufactured silicon carbide ingot was cut to prepare a silicon carbide substrate. Specifically, the cutting of the silicon carbide substrate is currently carried out by a multi-wire cutting method in industry, and the silicon carbide is very hard by carrying diamond powder by using a steel wire, so that the required steel wire is thicker, the cutting edge loss of the silicon carbide material caused by cutting is generally about 200 micrometers, the cutting edge loss is very large, and meanwhile, the method has the problems of long cutting time and low production efficiency. In addition, the surface roughness of the cut silicon carbide surface cut by the method is larger, the damaged layer of the cut surface is deeper after cutting, the deeper damaged layer of the silicon carbide needs to be removed by grinding and polishing, the loss of the silicon carbide material is further increased, and the manufacturing cost is increased.
The present invention aims to improve at least to some extent at least one of the above technical problems.
The present invention provides a method of preparing a semiconductor substrate, comprising: bonding a first semiconductor material sheet and a second semiconductor material sheet to form a composite substrate sheet; performing laser scanning treatment on the first semiconductor material sheet so as to form a microcrack enrichment region in a preset region to be cut in the first semiconductor material sheet; carrying out ultrasonic treatment on the composite substrate sheet to expand cracks in the microcrack enrichment area and separate the composite substrate sheet so as to obtain a first component and a second component, wherein the first component carries the second semiconductor material sheet and contains a first semiconductor material residual layer; and polishing the surface of the residual layer of the first semiconductor material in the first component so as to obtain the semiconductor substrate. Therefore, the method can rapidly cut and separate the composite substrate slice through laser scanning treatment and ultrasonic treatment, has the advantages of less material loss, high processing speed and high production efficiency, and can reduce the production cost of the semiconductor substrate.
According to an embodiment of the invention, the method further comprises: and polishing the second component to remove the microcrack enrichment area, and bonding the polished second component serving as the first semiconductor material sheet and the second semiconductor material sheet to form a composite substrate sheet. Thus, the second component may repeat the method described above for preparing a semiconductor substrate.
According to an embodiment of the invention, the first sheet of semiconductor material comprises one or more of silicon carbide, gallium nitride, gallium oxide, aluminum nitride material.
According to an embodiment of the present invention, the first semiconductor material sheet is a silicon carbide single crystal material satisfying a basal plane dislocation density of not more than 1500/cm 2 . Thus, the first sheet of semiconductor material can be made of a higher quality.
According to an embodiment of the invention, the second sheet of semiconductor material comprises one or more of silicon, silicon carbide, gallium nitride, gallium oxide, aluminum nitride material.
According to an embodiment of the invention, the second sheet of semiconductor material is a silicon carbide material, the resistivity of the second sheet of semiconductor material not exceeding 0.01Ω·cm.
According to an embodiment of the present invention, forming a composite substrate sheet includes: forming a bond enhancing layer at least one of the first sheet of semiconductor material and the second sheet of semiconductor material surface; and bonding the first semiconductor material sheet and the second semiconductor material sheet, and enabling the bonding enhancement layer to be positioned at a bonding interface to form a composite substrate sheet. Thereby, the bonding strength of the first semiconductor material sheet and the second semiconductor material sheet can be improved.
According to an embodiment of the invention, the bonding interface between the first sheet of semiconductor material and the second sheet of semiconductor material is electrically conductive. Thus, the obtained composite substrate sheet and the finally obtained semiconductor substrate can be used for manufacturing devices with vertical structures.
According to an embodiment of the invention, the length of the microcrack enrichment region in a direction perpendicular to the interface of the first and second semiconductor material sheets is not more than 100 micrometers. Therefore, the length of the microcrack enrichment area in the thickness direction of the semiconductor material is smaller, so that the subsequent thinning amount can be reduced, the loss of the semiconductor material is reduced, and the production cost is reduced.
According to an embodiment of the invention, the laser scanning process is performed from a side of the first sheet of semiconductor material remote from the second sheet of semiconductor material.
According to an embodiment of the invention, the wavelength of the laser is more than 355nm and the energy density is 4-9J/cm during the laser scanning treatment 2 . Thus, the laser light can penetrate into the region to be cut, creating sufficient microcracks within the first sheet of semiconductor material to form a microcrack-enriched region.
According to an embodiment of the present invention, the same region is scanned by the laser light no less than twice. Thus, the density of microcracks can be increased, which is advantageous for peeling.
According to an embodiment of the present invention, the thickness of the first semiconductor material residual layer after the polishing process is not less than 1 nm. Therefore, the semiconductor substrate has higher quality and meets the use requirement.
According to an embodiment of the present invention, the first semiconductor material residual layer does not contain the crack after the polishing treatment. Thus, the semiconductor substrate can have higher quality.
Drawings
FIG. 1 is a flow chart of a method of preparing a semiconductor substrate in one embodiment of the invention;
fig. 2 is a schematic flow chart of a method for fabricating a semiconductor substrate in accordance with another embodiment of the invention.
Description of the reference numerals
100. 100B-a first sheet of semiconductor material, 100a 1-a residual layer of semiconductor material, 200-a second sheet of semiconductor material, an F-microcrack enrichment region, a-a first component, B-a second component.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.
The present invention provides a method of preparing a semiconductor substrate, referring to fig. 1, the method comprising:
s100, bonding a first semiconductor material sheet and a second semiconductor material sheet to form a composite substrate sheet;
referring to fig. 2, a first sheet of semiconductor material 100 and a second sheet of semiconductor material 200 are bonded to form a composite substrate sheet.
According to some embodiments of the invention, the crystal quality of the first sheet of semiconductor material 100 is better than the crystal quality of the second sheet of semiconductor material 200. The semiconductor substrate has two main roles in a semiconductor device, namely, the first is used as an active area of the device or used as an epitaxial nucleation layer, and the epitaxial layer is used as an active area of the device and the second is used as a supporting layer in wafer processing. Since neither the device active region nor the epitaxial nucleation layer need to be thick nor the support layer need to be of high quality, the present invention allows for a lower cost and use-friendly semiconductor substrate by bonding a high quality first sheet of semiconductor material 100 to a low quality second sheet of semiconductor material 200 that is inexpensive.
According to an embodiment of the present invention, the first sheet of semiconductor material 100 comprises one or more of silicon carbide, gallium nitride, gallium oxide, aluminum nitride materials.
According to an embodiment of the present invention, the first sheet of semiconductor material 100 is a silicon carbide single crystal material satisfying a basal plane dislocation density of not more than 1500/cm 2 . Preferably, the silicon carbide single crystal material satisfies that the basal plane dislocation density is not higher than 500/cm 2 . The lower the basal plane dislocation density in a silicon carbide single crystal, the higher the material quality and the more expensive. Thus, by using carbonization of low dislocation densitySilicon material, a high quality first semiconductor material sheet can be provided.
According to an embodiment of the present invention, the materials of the first semiconductor material sheet 100 and the second semiconductor material sheet 200 may be the same or different. Further, the second sheet of semiconductor material 200 comprises one or more of silicon, silicon carbide, gallium nitride, gallium oxide, aluminum nitride materials.
According to an embodiment of the present invention, the second semiconductor material sheet 200 is a silicon carbide material, further, the second semiconductor material sheet 200 may be single crystal, polycrystalline or amorphous, and the resistivity of the second semiconductor material sheet 200 is not more than 0.01Ω·cm.
According to an embodiment of the present invention, forming a composite substrate sheet includes: forming a bonding enhancement layer at least one of the surfaces of the first sheet of semiconductor material 100 and the second sheet of semiconductor material 200; and bonding the first semiconductor material sheet 100 and the second semiconductor material sheet 200, and positioning the bonding enhancement layer at a bonding interface to form a composite substrate sheet. Thereby, the bonding strength of the first semiconductor material sheet 100 and the second semiconductor material sheet 200 can be improved.
In common semiconductor bonding techniques, the bonding interface is typically non-conductive, e.g., si—si bonding tends to form silicon dioxide at the interface, which can enhance its bonding strength. Non-conductive bonding interfaces can adversely affect device performance and even render the prepared semiconductor substrate unusable for fabricating devices of vertical structure.
According to an embodiment of the invention, the bonding interface between the first sheet of semiconductor material 100 and the second sheet of semiconductor material 200 is electrically conductive. Thus, the obtained composite substrate sheet and the finally obtained semiconductor substrate can be used for manufacturing devices with vertical structures.
The bonding enhancing layer may be formed by modifying the surface of the first semiconductor material sheet 100 and/or the second semiconductor material sheet 200 by ion implantation, plasma bombardment, or the like, or may be formed by depositing a layer of bonding-facilitating material on the surface of the first semiconductor material sheet 100 and/or the second semiconductor material sheet 200 by magnetron sputtering or the like. Ion implantation, plasma bombardment, magnetron sputtering, etc. may be some common processes in semiconductor fabrication and are not described here.
S200, performing laser scanning treatment on the first semiconductor material sheet so as to form a microcrack enrichment region in a region to be cut preset in the first semiconductor material sheet;
referring to fig. 2, the first semiconductor material sheet 100 is subjected to a laser scanning process, laser light is focused to a preset region to be cut inside the semiconductor material 100, a high temperature is locally formed, a large number of micro cracks are induced, and a micro crack enrichment region F can be formed inside the first semiconductor material sheet 100.
According to an embodiment of the invention, the microcrack enrichment zone F has a plurality of cracks therein, each of which may be the same or different in direction and length. For example, some of the cracks extend in a direction parallel to the interface of the first sheet of semiconductor material 100 and the second sheet of semiconductor material 200, i.e. some of the cracks extend in the direction of the release surface, and some of the cracks extend at an angle to the direction of the release surface.
According to an embodiment of the invention, the length of the microcrack enrichment region F in the direction perpendicular to the interface of the first sheet of semiconductor material 100 and the second sheet of semiconductor material 200 does not exceed 100 micrometers. Preferably, the length is no more than 30 microns. Thus, the lengths of the cracks formed by the laser scanning process in the thickness direction of the first semiconductor material sheet 100 and the second semiconductor material sheet 200 are smaller, so that the subsequent polishing removal amount can be reduced, the loss of the semiconductor material can be reduced, and the production cost can be further reduced.
According to an embodiment of the present invention, when the absorptivity of the second semiconductor material sheet 200 to the laser light is high, the laser scanning process is performed from the side of the first semiconductor material sheet 100 away from the second semiconductor material sheet 200. Thereby, loss of laser energy due to absorption of laser light by the second semiconductor material sheet 200 can be avoided.
According to some embodiments of the present invention, when the absorptivity of the first semiconductor material sheet 100 to the laser light is high, the laser scanning process may be performed at this time from the side of the second semiconductor material sheet 200 remote from the first semiconductor material sheet 100. Thereby, loss of laser energy due to absorption of laser light by the material can be avoided.
According to the embodiment of the invention, the wavelength of the laser is larger than 355nm during the laser scanning treatment, so that the laser can penetrate and focus on the area to be cut. For example, the laser may have a wavelength of 1064nm. If the wavelength of the laser is too short, it cannot penetrate to the area to be cut. In some embodiments of the invention, the semiconductor material is silicon carbide, and the absorption of laser light by the silicon carbide surface layer is severe if the laser wavelength is 355nm or less; if the laser wavelength is 1064nm, the laser can penetrate into silicon carbide with a few millimeters or even centimeters, focus on a region to be cut, generate high temperature in the region to be cut, and induce a large number of microcracks.
According to an embodiment of the present invention, the energy density of the laser reaching the semiconductor material is 4J/cm or more during the laser scanning process 2 And less than or equal to 9J/cm 2 . Thus, a sufficient number of microcracks may be generated within the semiconductor material 100 to form a microcrack-rich region. If the energy density is too low, the laser generates insufficient temperature in the region to be cut inside the semiconductor material, and microcracks cannot be generated. If the energy density is too high, the crack is too long, and further the crack length in the thickness direction is too large, which increases the processing amount of thinning treatment, and also increases the loss amount of the semiconductor material, which results in insignificant effect of reducing the cost. Preferably, the energy density of the laser is 6J/cm 2 To 7J/cm 2 In between, the length of microcracks generated by the energy density is less than 25 micrometers, so that a thinner microcrack enrichment region can be obtained, and further, the processing amount of subsequent thinning treatment and the loss of semiconductor materials are reduced.
According to an embodiment of the present invention, the same region is scanned by the laser light no less than twice. Therefore, by scanning the same region for multiple times, the microcrack density of the same region can be increased, and stripping is facilitated.
Further, according to the embodiment of the invention, multiple laser scans can be realized by overlapping laser spots, specifically, the laser spots overlap when scanning, and the higher the overlapping rate of the laser spots, the more times of scanning. The number of laser scans can be controlled by adjusting the overlap ratio of the laser spots.
The microcrack enrichment region was observed by a scanning electron microscope over an area of a unit cross section (25 mu m x, 25 mu m), the number of cracks was more than 2, and the length of the cracks along the separation plane was more than 5 μm.
S300, carrying out ultrasonic treatment on the composite substrate sheet to enable cracks in the microcrack enrichment area to be expanded and separate the composite substrate sheet so as to obtain a first component and a second component, wherein the first component carries the second semiconductor material sheet and contains a first semiconductor material residual layer;
referring to fig. 2, when the micro cracks are spread and a large number of micro cracks are spread and connected during ultrasonic treatment, the composite substrate sheet can be separated to obtain a first component a and a second component B, wherein the first component a comprises a second semiconductor material sheet 200 and a first semiconductor material residual layer 100a which are stacked, the second component B comprises a first semiconductor material sheet 100B, the first semiconductor material residual layer 100a and the first semiconductor material sheet 100B both comprise a micro crack enrichment region F, and the sum of the thickness of the first semiconductor material residual layer 100a and the thickness of the first semiconductor material sheet 100B is equal to the thickness of the first semiconductor material sheet 100.
The ultrasonic treatment may be performed by placing the wafer in a liquid tank with an ultrasonic wave generating device, for example, by using water as a transmission medium of ultrasonic waves, placing the composite substrate sheet in the water, and under the action of the ultrasonic waves, the micro cracks are expanded and the first component a and the second component B are separated at a frequency of 13-400 kHz. Preferably, the ultrasonic wave frequency is 13-200kHz during ultrasonic treatment, when the ultrasonic wave frequency is too high, cracks are not easy to expand, and if the ultrasonic wave frequency is too low, cracks are too fast to expand, and cracks vertical to the separation surface are also fast to expand, so that the thickness of a microcrack enrichment area is increased, the processing amount for later treatment for removing the microcrack enrichment area is increased, and the processing loss of materials is not reduced.
According to an embodiment of the invention, the method further comprises: and polishing the second component B to remove the microcrack enrichment region F in the first semiconductor material sheet 100B, and bonding the polished second component B serving as the first semiconductor material sheet 100 and the second semiconductor material sheet 200 to form a composite substrate sheet. That is, the second member B can be reused a plurality of times, and in particular, the second member B can be used for preparing a semiconductor substrate after performing the polishing process in accordance with the method described above.
And S400, polishing the surface of the first semiconductor material residual layer in the first component so as to obtain the semiconductor substrate.
Referring to fig. 2, the first member a is subjected to a polishing process to remove the microcrack enrichment region F in the first semiconductor material residual layer 100a, resulting in a first semiconductor material residual layer 100a1, and the first semiconductor material residual layer 100a1 has a thickness smaller than that of the first semiconductor material residual layer 100a, resulting in a semiconductor substrate composed of the stacked second semiconductor material sheet 200 and first semiconductor material residual layer 100a 1. The polishing process may be a polishing process common to semiconductor materials, and will not be described in detail herein.
According to some embodiments of the invention, prior to the polishing process, a grinding process may be employed to remove the microcrack enrichment region F, e.g., a diamond-impregnated wheel may be used to grind the microcrack enrichment region. After the grinding treatment with the very fine diamond particle size is adopted, the thickness of the damaged layer on the surface of the residual layer of the first semiconductor material is lower than 5 microns, so that the removal amount of the subsequent polishing treatment can be reduced. When the first semiconductor material is silicon carbide, the polishing rate is very low, and long polishing time is required for completely removing the microcrack enrichment region only by polishing treatment, so that a grinding-before-polishing process can be adopted, the polishing removal amount is reduced, and the production efficiency is improved.
According to an embodiment of the present invention, the thickness of the first semiconductor material residual layer 100a1 after the polishing process is not less than 1 nm. Preferably, the thickness of the first semiconductor material residual layer 100a1 after the polishing process is 1 to 10 μm. The residual layer of the first semiconductor material with the thickness can be completely used as a nucleation layer for epitaxy, and a high-quality epitaxial layer is grown. Therefore, the semiconductor substrate has higher quality and meets the use requirement.
According to an embodiment of the present invention, the first semiconductor material residual layer 100a1 does not contain the crack after the polishing process. That is, by the polishing treatment, the microcrack enrichment region F can be removed, so that the semiconductor substrate has high quality.
It should be noted that, in this specification, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. In the description of the present invention, it should be understood that the directions or positional relationships indicated by the terms "upper", "lower", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or element in question must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.
In the description of the present specification, the descriptions of the terms "one embodiment," "another embodiment," "some embodiments," "example," "specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.
Claims (14)
1. A method of preparing a semiconductor substrate, comprising:
bonding a first semiconductor material sheet and a second semiconductor material sheet to form a composite substrate sheet;
performing laser scanning treatment on the first semiconductor material sheet so as to form a microcrack enrichment region in a preset region to be cut in the first semiconductor material sheet;
carrying out ultrasonic treatment on the composite substrate sheet to expand cracks in the microcrack enrichment area and separate the composite substrate sheet so as to obtain a first component and a second component, wherein the first component carries the second semiconductor material sheet and contains a first semiconductor material residual layer; and
and polishing the surface of the residual layer of the first semiconductor material in the first component so as to obtain the semiconductor substrate.
2. The method as recited in claim 1, further comprising: and polishing the second component to remove the microcrack enrichment area, and bonding the polished second component serving as the first semiconductor material sheet and the second semiconductor material sheet to form a composite substrate sheet.
3. The method of claim 1, wherein the first sheet of semiconductor material comprises one or more of silicon carbide, gallium nitride, gallium oxide, aluminum nitride material.
4. A method according to claim 3, wherein the first sheet of semiconductor material is a single crystal silicon carbide material that meets a basal plane dislocation density of not higher than1500/cm 2 。
5. The method of claim 1, wherein the second sheet of semiconductor material comprises one or more of silicon, silicon carbide, gallium nitride, gallium oxide, aluminum nitride material.
6. The method of claim 1, wherein the second sheet of semiconductor material is a silicon carbide material, and wherein the second sheet of semiconductor material has a resistivity of no more than 0.01 Ω -cm.
7. The method of claim 1, wherein forming the composite substrate sheet comprises:
forming a bond enhancing layer at least one of the first sheet of semiconductor material and the second sheet of semiconductor material surface;
and bonding the first semiconductor material sheet and the second semiconductor material sheet, and enabling the bonding enhancement layer to be positioned at a bonding interface to form a composite substrate sheet.
8. The method of claim 1, wherein a bonding interface between the first sheet of semiconductor material and the second sheet of semiconductor material is electrically conductive.
9. The method of claim 1, wherein the microcrack enrichment region has a length in a direction perpendicular to the interface of the first and second sheets of semiconductor material of no more than 100 microns.
10. The method of claim 1, wherein the laser scanning process is performed from a side of the first sheet of semiconductor material remote from the second sheet of semiconductor material.
11. The method of claim 1, wherein the laser light has a wavelength greater than that of the laser light during the laser scanning process355nm, energy density of 4-9J/cm 2 。
12. The method of claim 1, wherein the same area is scanned by the laser no less than twice.
13. The method of claim 1, wherein the thickness of the residual layer of the first semiconductor material after the polishing process is not less than 1 nanometer.
14. The method of claim 13, wherein the residual layer of the first semiconductor material is free of the crack after the polishing process.
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| US20060249748A1 (en) * | 2005-05-03 | 2006-11-09 | Nitronex Corporation | Gallium nitride material structures including substrates and methods associated with the same |
| CN103035573A (en) * | 2013-01-05 | 2013-04-10 | 合肥彩虹蓝光科技有限公司 | Separation method for semiconductor units |
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