CN116070559A - Synchronization circuit, semiconductor device, and synchronization method - Google Patents

Synchronization circuit, semiconductor device, and synchronization method Download PDF

Info

Publication number
CN116070559A
CN116070559A CN202111273358.8A CN202111273358A CN116070559A CN 116070559 A CN116070559 A CN 116070559A CN 202111273358 A CN202111273358 A CN 202111273358A CN 116070559 A CN116070559 A CN 116070559A
Authority
CN
China
Prior art keywords
circuit
data
input
output data
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111273358.8A
Other languages
Chinese (zh)
Inventor
紫藤泰平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Winbond Electronics Corp
Original Assignee
Winbond Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Winbond Electronics Corp filed Critical Winbond Electronics Corp
Priority to CN202111273358.8A priority Critical patent/CN116070559A/en
Publication of CN116070559A publication Critical patent/CN116070559A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2117/00—Details relating to the type or aim of the circuit design
    • G06F2117/04—Clock gating

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

The invention provides a synchronization circuit, a semiconductor device and a synchronization method, comprising a first delay circuit, a second delay circuit and a first delay circuit, wherein the first delay circuit delays an input synchronization signal by a first specific time to generate a first delay synchronization signal; a second delay circuit for delaying the first delay synchronous signal by a second specific time to generate a second delay synchronous signal; a first synchronizing circuit that outputs first output data that synchronizes the input data with the input synchronizing signal; a second synchronizing circuit that outputs second output data synchronizing the input data with the first delayed synchronizing signal; and the resynchronization circuit resynchronizes the input data according to the second delay synchronizing signal if the first output data is inconsistent with the second output data, and updates the first output data for the first synchronizing circuit.

Description

Synchronization circuit, semiconductor device, and synchronization method
Technical Field
The invention relates to a synchronization circuit, a semiconductor device and a synchronization method.
Background
In the logic design of the CMOS circuit, the power supply maintains the voltage VDD and the voltage VSS. However, if the input data to the flip-flop circuit does not maintain a sufficient setup margin (hold margin) for the clock, the output signal of the flip-flop circuit may enter a metastable state (meta table). That is, if the timing of the input data is similar to the timing of the input clock and the set or maintenance boundary is not maintained, the voltage of the output data may not be the voltage VDD or the voltage VSS, and may be an intermediate voltage.
In this case, a logic circuit, which inputs such a signal as a part of the intermediate voltage, treats the intermediate voltage of the output signal as the voltage VDD, and this metastable state may destroy the system.
In transmitting and receiving data between different clock domains, although a synchronous circuit is used, there is a case where such a problem of metastability occurs in the synchronous circuit. A synchronous circuit using a data strobe signal synchronized with data is known to suppress occurrence of metastable states when transmitting received data between different clock domains (for example, patent document: japanese patent application laid-open No. 10-135938).
Such a synchronization circuit requires an additional circuit associated with the data selection signal, and thus, a synchronization circuit, a semiconductor memory device, and a synchronization method capable of synchronizing with a clock on the receiving side of input data with a small circuit scale are required due to a large circuit scale.
Disclosure of Invention
The invention provides a synchronous circuit, which comprises a first delay circuit, a second delay circuit and a first delay circuit, wherein the first delay circuit delays an input synchronous signal by a first specific time to generate a first delay synchronous signal; a second delay circuit for delaying the first delay synchronous signal by a second specific time to generate a second delay synchronous signal; a first synchronizing circuit that outputs first output data that synchronizes input data with the input synchronizing signal; a second synchronizing circuit that outputs second output data that synchronizes the input data with the first delayed synchronizing signal; and the resynchronization circuit resynchronizes the input data according to the second delay synchronizing signal if the first output data is inconsistent with the second output data, and updates the first output data for the first synchronizing circuit.
The invention provides a synchronization method, which comprises the following steps: comparing first data synchronized with input data by a synchronization signal and second data synchronized with the input data according to a signal delaying the synchronization signal; and outputting data which synchronizes the input data according to more signals delaying the synchronizing signals if the first data and the second data are different, otherwise outputting the first data.
The invention provides a synchronization method, which comprises the following steps: comparing each bit width of first data synchronized by a synchronization signal to input data including a plurality of bit widths, and second data synchronized by a signal delaying the synchronization signal to the input data; outputting data which synchronizes the input data according to more signals delaying the synchronizing signals if the first data and the second data have at least one bit width difference, otherwise outputting the first data.
Based on the above, a synchronization circuit, a semiconductor memory device, and a synchronization method that can perform synchronization with a small circuit scale can be realized.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. In the drawings:
fig. 1 is a circuit diagram showing the configuration of a synchronization circuit according to a first embodiment of the present invention.
Fig. 2 is a timing chart showing an example of operation in the case where the synchronization circuit shown in fig. 1 does not perform resynchronization.
Fig. 3 is a timing chart showing a first operation example of the case where the synchronization circuit shown in fig. 1 performs resynchronization.
Fig. 4 is a timing chart showing a second operation example of the case where the synchronization circuit shown in fig. 1 performs resynchronization.
Fig. 5 is a circuit diagram showing the configuration of a synchronous circuit according to a second embodiment of the present invention.
Fig. 6 is a circuit diagram showing the configuration of a synchronization circuit according to a third embodiment of the present invention.
Fig. 7 is a timing chart showing an example of operation in the case where the synchronization circuit shown in fig. 6 does not perform resynchronization.
Fig. 8 is a timing chart showing an example of operations in the case where the synchronization circuit shown in fig. 6 performs resynchronization.
Fig. 9 is a timing chart showing a correspondence relationship between clocks in the synchronous circuit based on the first embodiment and data strobe signals in the synchronous circuit based on the second embodiment shown in fig. 5.
Detailed Description
Based on the synchronization circuit 201 of the embodiment shown in fig. 1, the input DATA is synchronized with the input clock Clk and output as the output DATA Q3. The synchronization circuit 201 may be provided in the semiconductor device. The semiconductor device may be a semiconductor memory device such as a dynamic random access memory. In the case where the synchronization circuit 201 is provided in the dynamic random access memory, the synchronization circuit 201 may process temperature-related data to be referred to when adjusting the refresh interval of the memory cell.
For example, the input DATA is synchronized with a first series of clocks and the clock Clk is synchronized with a second series of clocks. Therefore, the synchronization circuit 201 may transfer data from the first series of clocks to the second series of clocks.
The synchronization circuit 201 includes: a first D-type flip-flop circuit 211; a second D-type flip-flop circuit 213; and a third D-type flip-flop circuit 215. Here, the first D-type flip-flop circuit 211, the second D-type flip-flop circuit 213, and the third D-type flip-flop circuit 215 are examples of the first synchronization circuit, the second synchronization circuit, and the third synchronization circuit of the present invention, respectively. In addition, the synchronization circuit 201 includes: two delay circuits 221, 223; a two-input logical exclusive-or gate 225; a two-input logic AND gate 227; and a two-input logical or gate 229.
The input terminal D of the first D-type flip-flop circuit 211 and the input terminal D of the second D-type flip-flop circuit 213 are supplied with 1-bit wide input DATA. The output data Q1 from the output terminal Q of the first D-type flip-flop circuit 211 is supplied to the input terminal D of the third D-type flip-flop circuit 215.
The delay circuit 221 delays the input clock Clk by a first specific delay time and outputs it as a first delay clock clk_d1. The delay circuit 223 delays the first delay clock clk_d1 by a second specific delay time and outputs it as a second delay clock clk_d2. Here, the delay circuit 221 and the delay circuit 223 are examples of the first delay circuit and the second delay circuit of the present invention, respectively. Here, the input clock Clk, the first delay clock clk_d1, and the second delay clock clk_d2 are examples of the first synchronization signal, the second synchronization signal, and the third synchronization signal of the present invention, respectively.
The two-input logical exclusive-or gate 225 takes the logical exclusive-or of the output data Q1 from the output terminal Q of the first D-type flip-flop circuit 211 and the output data Q2 from the output terminal Q of the second D-type flip-flop circuit 213, and outputs a control signal qchk showing the result. Therefore, if the logic level of the output data Q1 from the output terminal Q of the first D-type flip-flop circuit 211 matches the logic level of the output data Q2 from the output terminal Q of the second D-type flip-flop circuit 213, the logic level of the control signal qchk is LOW, and if not, it is HIGH.
The two-input logic and gate 227 takes the logical sum of the control signal qchk and the second delay clock clk_d2, and outputs the result as the adaptive second delay clock cclk. Therefore, if the logic level of the control signal qchk is HIGH, the adaptive second delay clock cclk corresponding to the second delay clock clk_d2 is generated, however, if the logic level of the control signal qchk is LOW, the adaptive second delay clock cclk corresponding to the second delay clock clk_d2 is not generated.
The two-input logical or gate 229 takes the logical or of the input clock Clk and the adaptive second delay clock cclk, and outputs the result as the master clock lclk.
The clock terminal CK of the first D-type flip-flop circuit 211 is supplied with the master clock lclk output from the two-input logic or gate 229. The clock terminal CK of the second D-type flip-flop circuit 213 is supplied with the first delay clock clk_d1 from the first delay circuit 221. The clock terminal CK of the third D-type flip-flop circuit 215 is supplied with the second delay clock clk_d2 from the second delay circuit 223.
The first D-type flip-flop circuit 211 outputs output DATA Q1 from the output terminal Q, the output DATA Q1 synchronizing the input DATA supplied to the input terminal D with the rising of the master clock lclk supplied to the clock terminal CK from LOW to HIGH. The second D-type flip-flop circuit 213 outputs output DATA Q2 from the output terminal Q, the output DATA Q2 synchronizing the input DATA supplied to the input terminal D with the rising of the first delay clock clk_d1 supplied to the clock terminal CK from LOW to HIGH. The third D-type flip-flop circuit 215 outputs output data Q3 from the output terminal Q, the output data Q3 synchronizing the data Q1 supplied to the input terminal D with the rising of the second delay clock clk_d2 supplied to the clock terminal CK from LOW to HIGH.
First, the input DATA is synchronized with a master clock lclk in the first D-type flip-flop circuit 211, the master clock lclk being obtained by slightly delaying the input clock Clk by the two-input logic or gate 229. The input DATA synchronized with the main clock lclk is output as DATA Q1 from the output terminal Q of the first D-type flip-flop circuit 211. Next, the input DATA is synchronized with a first delay clock clk_d1 in the second D flip-flop circuit 213, the first delay clock clk_d1 being obtained by delaying the input clock Clk by the delay circuit 221. The input DATA synchronized with the first delay clock clk_d1 is output as DATA Q2 from the output terminal Q of the second D-type flip-flop circuit 213.
If the logic level of the input DATA changes at a timing similar to the rising timing of the input clock Clk from LOW to HIGH (i.e., when the set/sustain boundary required for the input DATA of the input clock Clk is not ensured), there is a possibility that the output DATA Q1 of the first D-type flip-flop circuit 211 may be metastable. The timing of the logic level change of the input DATA is similar to the timing of the rising of the first delay clock clk_d1 (i.e., when the set/sustain boundary required for the input DATA of the first delay clock clk_d1 is not ensured), there is a possibility that the meta-stable state occurs in the output DATA Q2 of the second D-type flip-flop circuit 213.
While the input DATA maintains the same logic level, in the first D-type flip-flop circuit 211, the input DATA is synchronized in accordance with the rising of the master clock lclk corresponding to the rising of the input clock Clk. Next, in the second D-type flip-flop circuit 213, if the input DATA is synchronized by the first delay clock clk_d1, the logic level of the control signal qchk output from the two-input logical exclusive-or gate 225 is LOW after the input DATA is synchronized by the first delay clock clk_d1 in the second D-type flip-flop circuit 213. Therefore, when the second delay clock clk_d2 rises thereafter, the logic level of the adaptive second delay clock cclk supplied from the output terminal of the two-input logic and gate 227 to the two-input logic or gate 229 is maintained LOW, the logic level of the main clock lclk is also maintained LOW, and the input DATA is not resynchronized in the first D-type flip-flop circuit 211. Accordingly, the logic level of the output data Q1 of the first D-type flip-flop circuit 211 updated in synchronization with the rising of the master clock lclk corresponding to the rising of the input clock Clk is maintained.
On the other hand, when the logic level of the input DATA is a certain logic level (HIGH or LOW), the first D-type flip-flop circuit 211 synchronizes the input DATA with the rising of the master clock lclk corresponding to the rising of the input clock Clk, and then, when the logic level of the input DATA changes to another logic level (LOW or HIGH), the second D-type flip-flop circuit 213 synchronizes the input DATA with the first delay clock clk_d1, and the logic level of the control signal qchk output from the two-input logical exclusive-or gate 225 is HIGH.
Therefore, even when the output data Q1 of the first D-type flip-flop circuit 211 or the output data Q2 of the second D-type flip-flop circuit 213 is in a meta-stable state and then the second delay clock clk_d2 rises, the logic level of the control signal qchk remains HIGH and the adaptive second delay clock cclk output from the two-input logic and gate 227 rises. Since the adaptive second delay clock cclk is input to one of the input terminals of the two-input logic or gate 229, the logic level of the other of the input terminals is maintained LOW, and the master clock lclk output from the two-input logic or gate 229 delays the second delay clock clk_d2 by the two-input logic and gate 227 and the two-input logic or gate 229, and then rises. Therefore, the main clock lclk corresponds to the rising of the second delay clock clk_d2, and the input DATA is resynchronized in the first D-type flip-flop circuit 211 according to the rising of the main clock lclk.
The logic level of the output data Q1 of the first D-type flip-flop circuit 211 updated in accordance with the rising synchronization of the rising master clock lclk corresponding to the input clock Clk becomes updated in accordance with the rising of the master clock lclk corresponding to the rising of the second delay clock clk_d2. In the present embodiment, the two-input logical exclusive-or gate 225, the two-input logical and gate 227, the two-input logical or gate 229, and the first D-type flip-flop circuit 211 are examples of the resynchronization circuit of the present invention.
An example of a case where the input DATA is not resynchronized in the first D flip-flop circuit 211 is described with reference to fig. 2.
At time t11, the logic level of the input DATA changes from LOW to HIGH. At time tc1, the input data having the logic level HIGH is synchronized in the first D-type flip-flop circuit 211 in accordance with the rising of the master clock lclk corresponding to the rising of the input clock Clk. The logic level of the output data Q1 of the first D-type flip-flop circuit 211 becomes HIGH after a time t12 slightly delayed from the time tc1 at which the input clock Clk rises. At time tc2, the input DATA having a logic level of HIGH is synchronized in the second D-type flip-flop circuit 213 in accordance with the rising of the first delay clock clk_d1. The logic level of the output data Q2 of the second D-type flip-flop circuit 213 becomes HIGH after a time t13 slightly delayed from the time tc2 at which the first delay clock clk_d1 rises.
The logic level of the control signal qchk becomes HIGH from time t12 to time t13, and becomes LOW after time t 13. At the time tc3 when the second delay clock clk_d2 rises, since the logic level of the output data Q1 and Q2 is the same, the logic level of the control signal qchk is LOW, and the adaptive second delay clock cclk is not generated. Accordingly, the resynchronization in the first D-type flip-flop circuit 211 according to the rising of the master clock lclk corresponding to the rising of the second delay clock clk_d2 does not occur. By synchronizing with the rising of the master clock lclk corresponding to the rising of the input clock Clk, the logic level of the output data Q1 of the first D-type flip-flop circuit 211 updated at time t12 is maintained. The output data Q1 synchronized only 1 time in the first D-type flip-flop circuit 211 is then synchronized in the third D-type flip-flop circuit 215 at the timing when the second delay clock clk_d2 rises, and is output as output data Q3 from the output terminal Q of the third D-type flip-flop circuit 215.
An example of the case where the input DATA is resynchronized in the first D-type flip-flop circuit 211 in accordance with the rising of the master clock lclk corresponding to the rising of the second delay clock clk_d2, because the output DATA Q1 of the first D-type flip-flop circuit 211 is in the meta-stable state, will be described with reference to fig. 3.
At time tc1, the input DATA whose logic level changes from LOW to HIGH is synchronized in the first D-type flip-flop circuit 211 in accordance with the rise of the master clock lclk corresponding to the rise of the input clock Clk. However, since the necessary setting/maintaining boundary for the input DATA of the input clock Clk is not ensured, the output DATA Q1 of the first D-type flip-flop circuit 211 becomes a metastable state after the time tc 1. Further, by the resynchronization described later, the logic level of the output data Q1 of the first D flip-flop circuit 211 is stabilized to HIGH after time t 22. At time tc2, the input DATA having a logic level of HIGH is synchronized in the second D-type flip-flop circuit 213 in accordance with the rising of the first delay clock clk_d1. The logic level of the output data Q2 of the second D-type flip-flop circuit 213 becomes HIGH after a time t21 slightly delayed from the time tc2 at which the first delay clock clk_d1 rises.
As described above, the output data Q1 of the first D-type flip-flop circuit 211 is in the meta-stable state from the time tc1 to the time t22, but the logic level is determined as LOW in the two-input logic exclusive or gate 225. If the logic levels of the output data Q1 and Q2 are different, the logic level of the control signal qchk output from the two-input logical exclusive-or gate 225 becomes HIGH. Accordingly, the logic level of the control signal qchk starts to be HIGH from time t 21.
At a time tc3 when the second delay clock clk_d2 rises, the logic level of the control signal qchk is HIGH, and the adaptive second delay clock cclk also rises. Although not shown, the logic level of the input clock Clk is LOW before and after the time tc3, and the master clock lclk, which also rises in response to the adaptive second delay clock cclk, also rises.
Accordingly, the resynchronization is performed in the first D-type flip-flop circuit 211 in accordance with the rising of the master clock lclk corresponding to the rising of the second delay clock clk_d2. At time t22, the logic level of the output DATA Q1 and the logic level of the input DATA of the first D-type flip-flop circuit 211 are updated to be the same HIGH, and the logic level of the control signal qchk is LOW. The output data Q1 re-synchronized in the first D-type flip-flop circuit 211 is synchronized in the third D-type flip-flop circuit 215 at the timing when the second delay clock clk_d2 rises, and is outputted as output data Q3 from the output terminal Q of the third D-type flip-flop circuit 215.
With reference to fig. 4, an example will be described in which the output DATA Q2 of the second D-type flip-flop circuit 213 is in a stable state, and therefore, the input DATA is resynchronized in the first D-type flip-flop circuit 211 in accordance with the rising of the master clock lclk corresponding to the rising of the second delay clock clk_d2.
At time tc1, the input DATA having a logic level LOW is synchronized in the first D-type flip-flop circuit 211 in accordance with the rising of the master clock lclk corresponding to the rising of the input clock Clk. The logic level of the output data Q1 of the first D flip-flop circuit 211 becomes LOW after a time t31 slightly delayed from the time tc1 at which the input clock Clk rises. In the example of fig. 4, the logic level of the output data Q1 of the first D flip-flop circuit 211 is LOW before time t 31. At time tc2, the input DATA whose logic level changes from LOW to HIGH is synchronized in the second D-type flip-flop circuit 213 in accordance with the rising of the first delay clock clk_d1. However, since the necessary setting/maintaining boundary for the input DATA of the first delay clock clk_d1 is not ensured, the output DATA Q2 of the second D-type flip-flop circuit 213 becomes a meta-stable state after the time tc 2. After time tc3, the logic level of the output data Q2 of the second D-type flip-flop circuit 213 is stabilized at HIGH.
Therefore, in the period from the time tc2 to the time tc3, although the output data Q2 of the second D-type flip-flop circuit 213 is in the meta-stable state, the logic level is determined to be HIGH in the two-input logic exclusive or gate 225. Since the logic levels of the output data Q1 and Q2 are different, the logic level of the control signal qchk output from the two-input logical exclusive-or gate 225 after the time tc2 is HIGH. At a time tc3 corresponding to the rising of the second delay clock clk_d2, the logic level of the control signal qchk is HIGH, and the adaptive second delay clock cclk also rises. Although not shown, the logic level of the input clock Clk is LOW before and after the time tc3, and the master clock lclk corresponding to the rising of the adaptive second delay clock cclk also rises.
Accordingly, the resynchronization is performed in the first D-type flip-flop circuit 211 in accordance with the rising of the master clock lclk corresponding to the rising of the second delay clock clk_d2, and at time t32, the logic level of the output DATA Q1 of the first D-type flip-flop circuit 211 and the logic level of the input DATA are updated to the same HIGH. The output data Q1 re-synchronized in the first D-type flip-flop circuit 211 is synchronized in the third D-type flip-flop circuit 215 at the timing when the second delay clock clk_d2 rises, and is outputted as output data Q3 from the output terminal Q of the third D-type flip-flop circuit 215.
Further, if the time obtained by adding the first specific delay time via the delay circuit 221 and the second specific delay time via the delay circuit 223 is shorter than the period in which the input DATA maintains the same logic level (for example, the clock period of the input DATA), the output DATA Q3 can be stabilized by the synchronization circuit 201, and even if the output DATA Q1 becomes metastable through the initial synchronization, the stabilized output DATA Q1 can be obtained by the resynchronization.
Fig. 5 shows a synchronization circuit 203 according to a second embodiment. The synchronization circuit 203 differs from the synchronization circuit 201 according to the first embodiment in the following points: the first D-type flip-flop circuit 211 and the second D-type flip-flop circuit 213 are replaced with a first latch circuit 241 and a second latch circuit 243, respectively; the third D-type flip-flop circuit 215 is omitted.
Referring to fig. 1 and 5, the synchronization circuit 203 differs from the synchronization circuit 201 according to the first embodiment in the following points: the input clock Clk, the first delay clock clk_d1, and the second delay clock clk_d2 are replaced with the input strobe signal Str, the first delay strobe signal str_d1, and the second delay strobe signal str_d2, respectively. The input strobe signal Str, the first delayed strobe signal str_d1, and the second delayed strobe signal str_d2 are other examples of the first synchronization signal, the second synchronization signal, and the third synchronization signal of the present invention, respectively. Further, the adaptive second delay clock cclk and the master clock lclk are replaced with an adaptive second delay strobe signal sstr and a master strobe signal lstr, respectively.
As shown in fig. 9, at the rising time tc1 of the input clock Clk, the input strobe signal Str falls. At a rising time tc2 of the first delayed clock clk_d1, the first delayed strobe signal str_d1 falls. At a rising time tc3 of the second delayed clock clk_d2, the second delayed strobe signal str_d2 falls.
In addition, the adaptive second delay strobe signal sstr is generated when the logic level of the control signal qchk is HIGH, similarly to the adaptive second delay clock cclk, and is not generated otherwise. When the adaptive second delayed strobe signal sstr is generated, the adaptive second delayed strobe signal sstr falls at the same timing as the timing at which the adaptive second delayed clock cclk rises. The main gate signal lstr for the first synchronization falls at the same timing as the timing at which the main clock lclk for the first synchronization rises. In addition, the master strobe signal lstr for resynchronization falls at the same timing as the timing at which the master clock lclk for resynchronization rises.
In general, a D flip-flop circuit is configured to synchronize input data with a rise of an input clock and output the data. In contrast, the latch circuit outputs the input data as output data while the logic level of the strobe signal is HIGH, but maintains the output data having the logic level of the input data when the strobe signal falls. Accordingly, the first latch circuit 241 and the second latch circuit 243 according to the second embodiment operate similarly to the first D-type flip-flop circuit 211 and the second D-type flip-flop circuit 213 according to the first embodiment, respectively. Since the D-type flip-flop circuit is replaced with the latch circuit, the circuit scale can be reduced.
In the second embodiment, there is no third latch circuit corresponding to the third D-type flip-flop circuit 215 in the first embodiment. However, a third latch circuit corresponding to the third D-type flip-flop circuit 215 may be provided.
In a dynamic random access memory, a refresh circuit for recharging a memory cell that gradually reduces accumulated charges is provided. In the update circuit, temperature data to be referred to for update rate control may be composed of a plurality of bit widths. When the clock transfer is required, the temperature data composed of a plurality of bit widths is used as input data to the synchronous circuit. However, if only a plurality of synchronization circuits each having a width of 1 bit are arranged in parallel, for example, the synchronization circuits may operate differently between bit widths, and thus clock conversion may not be performed accurately. That is, although resynchronization occurs in the synchronization circuit corresponding to a certain bit width, resynchronization does not occur in the synchronization circuit corresponding to another bit width, and thus, accurate clock transition cannot be performed. The synchronization circuit according to the third embodiment is generated so that such a problem does not occur.
Fig. 6 shows a synchronization circuit 205 according to a third embodiment. In the synchronization circuit 203 according to the second embodiment, the number of bit widths of the input DATA is 1, and in the synchronization circuit 205 according to the third embodiment, the number of bit widths of the input DATA is a complex number n (n is an integer of 2 or more).
The synchronization circuit 205 according to the third embodiment is different from the synchronization circuit 203 according to the second embodiment in the following points: the first latch circuit 241, the second latch circuit 243, and the two-input logical exclusive-OR gate 225 are replaced with plural (n in this case) first latch circuits 241-1 to 241-n, plural (n in this case) second latch circuits 243-1 to 243-n, and plural (n in this case) two-input logical exclusive-OR gates 225-1 to 225-n, respectively; an n-input logical OR gate 231 is added.
The plurality of first latch circuits 241-1 to 241-n latch the input DATA < n:1> of n-bit width by the main strobe signal lstr and output as the output DATA Q1< n:1> of n-bit width. The plurality of second latch circuits 243-1 to 243-n latch the input DATA < n:1> of n-bit width by the first delay strobe signal str_d1, and output the DATA as the output DATA Q2< n:1> of n-bit width. The i-th two-input logical exclusive OR gate 225-i (i=1, 2, …, n) among the plurality of two-input logical exclusive OR gates 225-1 to 225-n calculates the logical exclusive OR of the i-th bit width of the output data Q1< n:1> and the i-th bit width of the output data Q2< n:1>, and outputs the result as the i-th bit width of the preliminary control signal Qchk < n:1 >. The n-input logical or gate 231 performs logical or calculation of the preliminary control signal Qchk < n:1>, and supplies a control signal QchkN showing the result from the output terminal to the input terminal on one side of the two-input logical and gate 227. The two-input logical AND gate 227 and the two-input logical OR gate 229 are the same as those of the second embodiment.
Then, the output data Q1< n:1> and the output data Q2< n:1> are compared for each bit width by a plurality of two-input logical exclusive-OR gates 225-1-225-n. If the plurality of two-input logical exclusive-OR gates 225-1 to 225-n display that the output DATA Q1< n:1> and the output DATA Q2< n:1> are different in at least 1 bit width in the output preliminary control signal Qchk < n:1>, the input DATA DATA < n:1> is latched again in the plurality of first latch circuits 241-1 to 241-n upon the falling of the main strobe signal lstr corresponding to the falling of the adaptive second delayed strobe signal sstr.
An example of a case where the n-bit wide input DATA < n:1> is not re-latched in the plurality of first latch circuits 241-1 to 241-n will be described with reference to fig. 7.
At the time of falling of the main gate signal lstr corresponding to the falling of the input gate signal Str, the n-bit wide input DATA < n:1> is latched in the plurality of first latch circuits 241-1 to 241-n. Accordingly, the output data Q1< n:1> of the plurality of first latch circuits 241-1 to 241-n changes at a time t41 slightly delayed from the time tc1 at which the input strobe signal Str falls.
At the time of the falling of the first delay strobe signal str_d1, the n-bit wide input DATA < n:1> is latched in the second latch circuits 243-1 to 243-n. Accordingly, the output data Q2< n:1> of the plurality of second latch circuits 243-1 to 243-n changes at a time t42 slightly delayed from the time tc2 at which the first delayed strobe signal str_d1 falls.
In a period from time t41 to time t42, the logic level of the bit width of at least a part of the output data Q2< n:1> of the plurality of second latch circuits 243-1 to 243-n does not match the corresponding bit width of the output data Q1< n:1> of the plurality of first latch circuits 241-1 to 241-n. Therefore, at least one logic level of the preliminary control signal Qchk < n:1> outputted from the plurality of two-input logic exclusive OR gates 225-1 to 225-n becomes HIGH, and the logic level of the control signal QchkN outputted from the n-input logic OR gate 231 becomes HIGH.
After time t42, the logic level of the output data Q2< n:1> of the plurality of second latch circuits 243-1 to 243-n matches the logic level of the output data Q1< n:1> of the plurality of first latch circuits 241-1 to 241-n in all bit widths. Therefore, the logic level of all the preliminary control signals Qchk < n:1> outputted from the plurality of two-input logical exclusive OR gates 225-1 to 225-n becomes LOW, and the logic level of the control signal QchkN outputted from the n-input logical OR gate 231 becomes LOW.
At the time tc3 when the second delayed strobe signal str_d2 falls, the logic level of the control signal QchkN becomes LOW, so that the fall of the adaptive second delayed strobe signal sstr and the main strobe signal lstr does not occur, the re-latch in the plurality of first latch circuits 241-1 to 241-n does not occur, and the logic level of the output data Q1< n:1> of the plurality of latched first latch circuits 241-1 to 241-n is not updated by the re-latch, and is maintained.
In addition, even if the n-bit wide input DATA < n:1> changes during the period of the length tTRAN from the time tc3 to the time t43, the logic level of the output DATA Q1< n:1> of the plurality of first latch circuits 241-1 to 241-n remains. The n-bit-width input DATA DATA < n:1> varies with the offset between bit widths from time tc3 to time t 43.
An example of the case where the n-bit wide input DATA < n:1> is re-latched in the plurality of first latch circuits 241-1 to 241-n at the time of the fall of the main gate signal lstr corresponding to the fall of the second delayed gate signal str_d2 will be described with reference to fig. 8.
The n-bit wide input DATA DATA < n:1> is latched in the plurality of first latch circuits 241-1 to 241-n in accordance with a fall of the main strobe signal lstr corresponding to a fall of the input strobe signal Str. Accordingly, the output data Q1< n:1> of the plurality of first latch circuits 241-1 to 241-n changes at a time t51 slightly delayed from the time tc1 at which the input signal falls.
As in the case of fig. 7, from time t51, the logic level of the bit width of at least a part of the output data Q1< n:1> of the plurality of first latch circuits 241-1 to 241-n becomes inconsistent with the corresponding bit width of the output data Q2< n:1> of the plurality of second latch circuits 243-1 to 243-n. Accordingly, from time t51, at least one logic level of the preliminary control signal Qchk < n:1> outputted from the plurality of two-input logical exclusive OR gates 225-1 to 225-n becomes HIGH, and the logic level of the control signal QchkN outputted from the n-input logical OR gate 231 becomes HIGH.
Unlike the example of fig. 7, the logic level of the n-bit wide input DATA < n:1> varies around the time tc2 at which the first delay strobe signal str_d1 falls. The set n-bit wide input DATA DATA < n:1> is latched in the plurality of second latch circuits 243-1 to 243-n in accordance with the falling of the first delayed strobe signal str_d1.
Assuming that the logic level of each bit width of the n-bit-width input DATA < n:1> at time tc2 is the same as the logic level of the bit width corresponding to the n-bit-width input DATA < n:1> at time tc1, the logic level of the control signal QchkN becomes LOW after time t52 corresponding to time t42 of fig. 7. Fig. 8 does not show a case where the logic level of control signal QchkN is LOW after time t 52.
As described above, before and after the time tc2, the set/sustain boundary required for the fall of the first delay strobe signal str_d1 by the input DATA is not ensured due to the logic level change of the n-bit wide input DATA < n:1 >. Therefore, at least a part of the bit width of the output data Q2< n:1> of the plurality of second latch circuits 243-1 to 243-n becomes metastable. Alternatively, the logic level of at least a part of the bit width of the output data Q2< n:1> of the plurality of second latch circuits 243-1 to 243-n is not identical to the logic level of the corresponding bit width of the output data Q1< n:1> of the plurality of first latch circuits 241-1 to 241-n. Therefore, after time t51, the logic level of the output of at least a part of the gates included in the plurality of two-input logical exclusive-OR gates 225-1 to 225-n whose logic level is HIGH is maintained after time t52 corresponding to time t42 of FIG. 7. Thus, as shown in fig. 8, the logic level of the control signal QchkN remains HIGH after time t 52.
At the time tc3 when the second delayed strobe signal str_d2 falls, the logic level of the control signal QchkN is HIGH, and the adaptive second delayed strobe signal sstr also falls. The input DATA DATA < n:1> is re-latched in the plurality of first latch circuits 241-1 to 241-n upon the falling of the main strobe signal lstr corresponding to the falling of the adaptive second delayed strobe signal sstr. Accordingly, at time t53, the logic levels of the output data Q1< n:1> of the plurality of first latch circuits 241-1 to 241-n are updated.
Further, if the time obtained by adding the first specific delay time via the delay circuit 221 and the second specific delay time via the delay circuit 223 is set to be shorter than the time obtained by subtracting the maximum offset time from the period in which the input DATA maintains the same logic level (for example, the clock period of the input DATA), the output DATA Q3 can be stabilized from the synchronization circuit 205, and even if the output DATA Q1 becomes metastable through the initial synchronization, the stabilized output DATA Q1 can be obtained by the resynchronization.

Claims (13)

1. A synchronization circuit, comprising:
a first delay circuit for delaying the input synchronous signal by a first specific time to generate a first delayed synchronous signal;
a second delay circuit for delaying the first delay synchronous signal by a second specific time to generate a second delay synchronous signal;
a first synchronizing circuit that outputs first output data that synchronizes input data with the input synchronizing signal;
a second synchronizing circuit that outputs second output data that synchronizes the input data with the first delayed synchronizing signal;
and the resynchronization circuit resynchronizes the input data according to the second delay synchronizing signal if the first output data is inconsistent with the second output data, and updates the first output data for the first synchronizing circuit.
2. The synchronization circuit of claim 1, further comprising: and a third synchronizing circuit that outputs third output data that synchronizes the first output data with the second delayed synchronizing signal.
3. The synchronization circuit of claim 1 or 2, wherein a sum of the first specific time and the second specific time is shorter than a shortest sustain time of the input data.
4. The synchronization circuit of claim 1, wherein,
the input data, the first output data and the second output data respectively comprise a plurality of bit widths;
and if the first output data and the second output data have at least one bit width inconsistent, the resynchronization circuit resynchronizes the input data according to the second delay synchronizing signal and updates the first output data for the first synchronizing circuit.
5. The synchronization circuit of claim 1, wherein the first synchronization circuit is a first D-type flip-flop circuit and the second synchronization circuit is a second D-type flip-flop circuit.
6. The synchronization circuit of claim 1, wherein the first synchronization circuit is a first latch circuit and the second synchronization circuit is a second latch circuit.
7. The synchronization circuit of claim 1 wherein the resynchronization circuit comprises a two-input logical exclusive-or gate taking the output data from the output terminal of the first D-type flip-flop circuit and the logical exclusive-or gate taking the output data from the output terminal of the second D-type flip-flop circuit, outputting a control signal showing the result, the logic level of the control signal being low if the logic level of the output data from the output terminal of the first D-type flip-flop circuit is identical to the logic level of the output data from the output terminal of the second D-type flip-flop circuit, and high if the logic level of the control signal is not identical.
8. The synchronization circuit of claim 7 wherein the resynchronization circuit further comprises a two-input logic and gate taking the logical sum of the control signal and the second delay clock and outputting the result as an adaptive second delay clock; therefore, if the logic level of the control signal is high, an adaptive second delay clock corresponding to the second delay clock is generated.
9. The synchronization circuit of claim 8, wherein the resynchronization circuit further comprises a two-input logic or gate taking the logical or of the input clock and the adaptive second delay clock, outputting the result as a master clock, and supplying the master clock output from the two-input logic or gate to a clock terminal of the first D-type flip-flop circuit.
10. The synchronization circuit of claim 1, wherein the resynchronization circuit comprises:
the second input logic exclusive OR gate calculates the logic exclusive OR of the ith bit width of the first output data and the ith bit width of the second output data, and outputs the result as the ith bit width of a preparation control signal; and
n input logic OR gate, which performs logic OR calculation of the preliminary control signal, and supplies the control signal of the display result from the output terminal to the input terminal of one side of the two input logic AND gate.
11. A semiconductor device comprising the synchronization circuit of claim 1.
12. A method of synchronizing, comprising:
a comparison step of comparing first data synchronized with input data by a synchronization signal and second data synchronized with the input data according to a signal delaying the synchronization signal;
and outputting, namely outputting data which synchronizes the input data according to more signals delaying the synchronizing signals if the first data and the second data are different, otherwise outputting the first data.
13. The synchronization method of claim 12, wherein,
the input data includes a plurality of bit widths;
the comparing step compares each bit width of the first data and the second data;
and outputting the data which synchronizes the input data according to more signals delaying the synchronizing signals when the first data and the second data have at least one bit width difference, otherwise, outputting the first data.
CN202111273358.8A 2021-10-29 2021-10-29 Synchronization circuit, semiconductor device, and synchronization method Pending CN116070559A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111273358.8A CN116070559A (en) 2021-10-29 2021-10-29 Synchronization circuit, semiconductor device, and synchronization method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111273358.8A CN116070559A (en) 2021-10-29 2021-10-29 Synchronization circuit, semiconductor device, and synchronization method

Publications (1)

Publication Number Publication Date
CN116070559A true CN116070559A (en) 2023-05-05

Family

ID=86170238

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111273358.8A Pending CN116070559A (en) 2021-10-29 2021-10-29 Synchronization circuit, semiconductor device, and synchronization method

Country Status (1)

Country Link
CN (1) CN116070559A (en)

Similar Documents

Publication Publication Date Title
CN109074332B (en) Apparatus for controlling latency on an input signal path
JP5231045B2 (en) Clock skew controller and integrated circuit having the same
US7501866B2 (en) Delay locked loop circuit
KR100801741B1 (en) Delay Locked Loop
US6608743B1 (en) Delay locked loop, synchronizing method for the same and semiconductor device equipped with the same
US6255880B1 (en) One-shot DLL circuit and method
US20020000851A1 (en) Timing-control circuit device and clock distribution system
KR20030025181A (en) Semiconductor integrated circuit device and delay-locked loop device
US7659759B2 (en) Phase synchronous circuit
KR20010094529A (en) Delay locked loop circuit for correcting duty cycle of clock signal and delay locking method
KR20000028624A (en) Timing clock generation circuit using hierarchical dll circuit
US7135899B1 (en) System and method for reducing skew in complementary signals that can be used to synchronously clock a double data rate output
US6229360B1 (en) High speed synchronization circuit in semiconductor integrated circuit
EP0477706A2 (en) Asynchronous state machine synchronization circuit
US10715119B2 (en) Low power flip-flop circuit
US20020083358A1 (en) Generation of pulse signals from a clock signal
KR100616490B1 (en) A register-controlled digital delay locked loop
US6255870B1 (en) Apparatus for compensating locking error in high speed memory device with delay locked loop
KR100499305B1 (en) Circuit for correcting duty factor of clock signal using a couple of delay loops
JP2001168848A (en) Digital synchronization circuit
KR100776736B1 (en) Apparatus for Clock Synchronization
CN116070559A (en) Synchronization circuit, semiconductor device, and synchronization method
TWI795939B (en) Synchronization circuit, semiconductor device and synchronization method
JP7206347B1 (en) Synchronization circuit, semiconductor memory device and synchronization method
KR100505636B1 (en) Analog synchronous mirror delay with duty cycle correction scheme and internal clock generator using the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination