TWI795939B - Synchronization circuit, semiconductor device and synchronization method - Google Patents

Abstract

Providing a synchronization circuit, a semiconductor storage device, and a synchronization method capable of performing synchronization on a small circuit scale, including: a first delay circuit, generating a first delay synchronization signal by delaying a input synchronization signal by a first predetermined time; a second delay circuit, generating a second delay synchronization signal by delaying the first delay synchronization signal by a second predetermined time; a first synchronization circuit, outputting a first output data that synchronizes the input data with the input synchronization signal; a second synchronization circuit, outputting a second output data in which the input data is synchronized with the first delay synchronization signal; a resynchronization circuit, updating the first output data by resynchronizing the input data with the second delay synchronization signal to the first synchronization circuit if the first output data and the second output data are inconsistent.

Description

Synchronization circuit, semiconductor device and synchronization method

The invention relates to a synchronous circuit, a semiconductor memory device and a synchronous method.

In the logic design of the CMOS circuit, the power supply maintains the voltage VDD and the voltage VSS. However, if the input data input to the flip-flop circuit does not maintain enough setup margin/hold margin for the clock, the output signal of the flip-flop circuit may enter a metastable state (metastable) . That is to say, if the timing of the input data is close to the timing of the input clock and the boundary is not set or maintained, the voltage of the output data may not be VDD or VSS, but may be an intermediate voltage.

In this case, the input logic circuit that becomes part of the signal of the intermediate voltage treats the intermediate voltage of the output signal as the voltage VDD, and this metastable state may destroy the system.

When transmitting and receiving data between different clock domains, although a synchronous circuit is used, the problem of metastable state may occur in the synchronous circuit. There is known a synchronization circuit using a data strobe signal synchronized with data to suppress the occurrence of a metastable state when transmitting and receiving data between different clock domains (for example: Patent Document: Japanese Patent Laid-Open No. 10-135938).

A synchronous circuit like this requires an additional circuit associated with the data strobe signal. Since the circuit scale is large, a synchronous circuit, a semiconductor memory device, and a synchronous method capable of synchronizing with the clock of the receiving side of the input data with a small circuit scale are required.

The present invention provides a synchronous circuit, comprising: a first delay circuit that delays an input synchronous signal for a first specific time to generate a first delayed synchronous signal; a second delay circuit that delays the aforementioned first delayed synchronous signal by a second specific time to generate The second delay synchronization signal; the first synchronization circuit, which outputs the first output data which synchronizes the input data with the aforementioned input synchronization signal; the second synchronization circuit, which outputs the second output data which synchronizes the aforementioned input data with the aforementioned first delay synchronization signal ; A resynchronization circuit, if the first output data is inconsistent with the second output data, resynchronize the input data according to the second delayed synchronization signal, and update the first output data to the first synchronization circuit.

The present invention provides a synchronization method, comprising: comparing the first data which is synchronized with the input data by a synchronization signal, and the second data which is synchronized with the input data according to a signal delaying the synchronization signal; if the first data and the second data Differently, output the data that synchronizes the aforementioned input data according to the signal that delays the aforementioned synchronous signal more, otherwise, output the aforementioned first data.

The present invention provides a synchronization method, including: comparing the first data which is synchronized by the synchronization signal to the input data comprising a plurality of bits, and each bit of the second data which is the synchronization of the input data by a signal delaying the synchronization signal ; If the aforementioned first data and the aforementioned second data have at least one bit difference, output the data that synchronizes the aforementioned input data according to the signal that delays the aforementioned synchronization signal more, otherwise, output the aforementioned first data.

Based on the above, a synchronization circuit, a semiconductor memory device, and a synchronization method capable of synchronization at a small circuit scale can be realized.

The synchronization circuit 201 based on the embodiment shown in FIG. 1 synchronizes the input data DATA with the input clock Clk and outputs it as output data Q3. The synchronization circuit 201 may also be provided in a semiconductor device. The semiconductor device may also be a semiconductor memory device such as a dynamic random access memory. In addition, in the case that the synchronization circuit 201 is disposed in a dynamic random access memory, the synchronization circuit 201 can also process temperature-related data referred to when adjusting the refresh interval of memory cells.

For example, the input data DATA is synchronized with the first series of clocks, and the clock Clk is synchronized with the second series of clocks. Therefore, the synchronization circuit 201 can transfer data from the first series of clocks to the second series of clocks.

The synchronization circuit 201 includes: a first D-type flip-flop circuit 211 ; a second D-type flip-flop circuit 213 ; and a third D-type flip-flop circuit 215 . Here, the first D-type flip-flop circuit 211, the second D-type flip-flop circuit 213, and the third D-type flip-flop circuit 215 are respectively the first synchronous circuit, the second synchronous circuit, and the third synchronous circuit of the present invention. An example of a circuit. In addition, the synchronous circuit 201 includes: two delay circuits 221 , 223 ; a two-input logic exclusive OR gate 225 ; a two-input logic AND gate 227 ; and a two-input logic OR gate 229 .

1-bit input data DATA is supplied to the input terminal D of the first D-type flip-flop circuit 211 and the input terminal D of the second D-type flip-flop circuit 213 . The output data Q1 from the output terminal Q of the first D-type flip-flop circuit 211 is supplied to the input terminal D of the third-type flip-flop circuit 215 .

The delay circuit 221 delays the input clock Clk by a first specific delay time, and outputs it as a first delayed clock Clk_d1. The delay circuit 223 delays the first delayed clock Clk_d1 for a second specific delay time, and outputs it as a second delayed clock Clk_d2. Here, the delay circuit 221 and the delay circuit 223 are examples of the first delay circuit and the second delay circuit of the present invention, respectively. Here, the input clock Clk, the first delayed clock Clk_d1 and the second delayed clock Clk_d2 are respectively examples of the first synchronization signal, the second synchronization signal and the third synchronization signal of the present invention.

The two-input logic exclusive OR gate 225 takes the output data Q1 from the output terminal Q of the first D-type flip-flop circuit 211 and the logic mutual of the output data Q2 from the output terminal Q of the second D-type flip-flop circuit 213. Negate or, output the control signal qchk showing the result. Therefore, if the logic level of the output data Q1 from the output terminal Q of the first D-type flip-flop circuit 211 is consistent with the logic level of the output data Q2 from the output terminal Q of the second D-type flip-flop circuit 213, The logic level of the control signal qchk is LOW, and if not consistent, it is HIGH.

The two-input logical AND gate 227 takes the logical AND of the control signal qchk and the second delayed clock Clk_d2, and outputs the result as the adaptive second delayed clock cclk. Therefore, if the logic level of the control signal qchk is HIGH, the adaptive second delayed clock cclk corresponding to the second delayed clock Clk_d2 is generated; however, if the logic level of the control signal qchk is LOW, the corresponding adaptive second delayed clock Clk_d2 is not generated. The adaptive second delayed clock cclk of the second delayed clock Clk_d2.

The two-input logical OR gate 229 takes the logical OR of the input clock Clk and the adaptive second delayed clock cclk, and outputs the result as the main clock lclk.

The main clock lclk output from the two-input logical OR gate 229 is supplied to the clock terminal CK of the first D-type flip-flop circuit 211 . The first delayed clock Clk_d1 from the first delay circuit 221 is supplied to the clock terminal CK of the second D-type flip-flop circuit 213 . The second delayed clock Clk_d2 from the second delay circuit 223 is supplied to the clock terminal CK of the third D-type flip-flop circuit 215 .

The first D-type flip-flop circuit 211 outputs the output data Q1 from the output terminal Q. The output data Q1 is the input data DATA supplied to the input terminal D and the main clock lclk supplied to the clock terminal CK from LOW to HIGH. The rising synchronous output data Q1. The second D-type flip-flop circuit 213 outputs the output data Q2 from the output terminal Q. The output data Q2 is the input data DATA supplied to the input terminal D and the first delayed clock Clk_d1 supplied to the clock terminal CK from LOW Output data Q2 for rising synchronization to HIGH. The third D-type flip-flop circuit 215 outputs the output data Q3 from the output terminal Q. The output data Q3 is the data Q1 supplied to the input terminal D and the second delayed clock Clk_d2 supplied to the clock terminal CK from LOW to The output data Q3 of rising synchronization of HIGH.

First, the input data DATA is synchronized with the main clock lclk in the first D-type flip-flop circuit 211 , and the main clock lclk is obtained by slightly delaying the input clock Clk through two input logical OR gates 229 . The input data DATA synchronized with the main clock lclk is output from the output terminal Q of the first D-type flip-flop circuit 211 as data Q1. Next, the input data DATA is synchronized with the first delayed clock Clk_d1 in the second D-type flip-flop circuit 213 , and the first delayed clock Clk_d1 is obtained by delaying the input clock Clk by the delay circuit 221 . The input data DATA synchronized with the first delayed clock Clk_d1 is output from the output terminal Q of the second D-type flip-flop circuit 213 as data Q2.

If the timing of the change of the logic level of the input data DATA is similar to the timing of the rise of the input clock Clk from LOW to HIGH (that is, when there is no guarantee of setting boundaries/maintaining boundaries required for the input data DATA of the input clock Clk), There is a possibility that a metastable state will occur in the output data Q1 of the first D-type flip-flop circuit 211 . The timing of the change of the logic level of the input data DATA is similar to the rising timing of the first delayed clock Clk_d1 (that is, when the setting boundary/maintaining boundary required for the input data DATA of the first delayed clock Clk_d1 is not guaranteed), There is a possibility that a metastable state will occur in the output data Q2 of the second D-type flip-flop circuit 213 .

When the input data DATA maintains the same logic level, in the first D-type flip-flop circuit 211, the input data DATA is synchronized according to the rise of the main clock lclk corresponding to the rise of the input clock Clk. Next, in the second D-type flip-flop circuit 213, if the input data DATA is synchronized by the first delayed clock Clk_d1, the input data DATA is synchronized by the first delayed clock Clk_d1 in the second D-type flip-flop circuit 213 Afterwards, the logic level of the control signal qchk output from the two-input logical exclusive OR gate 225 is LOW. Therefore, when the second delayed clock Clk_d2 rises later, the logic level of the adaptive second delayed clock cclk supplied from the output terminal of the two-input logic AND gate 227 to the two-input logic OR gate 229 remains LOW, and the main clock lclk The logic level of DATA also remains LOW, and the input data DATA is not resynchronized in the first D-type flip-flop circuit 211 . Therefore, the logic level of the output data Q1 of the first D-type flip-flop circuit 211 that is synchronously updated by the rise of the main clock lclk corresponding to the rise of the input clock Clk is maintained.

On the other hand, when the logic level of the input data DATA is a certain logic level (HIGH or LOW), in the first D-type flip-flop circuit 211, the input data DATA is generated by the main clock corresponding to the rise of the input clock Clk. The rising synchronization of lclk, then, because the logic level of the input data DATA changes to another logic level (LOW or HIGH), if the input data DATA is in the second D-type flip-flop circuit 213 and the first delayed clock Clk_d1 Synchronously, the logic level of the control signal qchk output from the two-input logic exclusive OR gate 225 is HIGH.

Therefore, even if the output data Q1 of the first D-type flip-flop circuit 211 or the output data Q2 of the second D-type flip-flop circuit 213 is in a metastable state, and then the second delayed clock Clk_d2 rises, the control signal qchk The logic level remains HIGH, and the adaptive second delayed clock cclk output from the two-input logic AND gate 227 also rises. Since the adaptive second delayed clock cclk is input to one of the input terminals of the two input logic OR gates 229, the logic level of the other input terminal remains LOW, and the main clock lclk output from the two input logic OR gates 229 Through the two-input logical AND gate 227 and the two-input logical OR gate 229 , the second delayed clock Clk_d2 is delayed by a delay time, and then rises. Therefore, the main clock lclk corresponds to the rise of the second delayed clock Clk_d2, and the input data DATA is resynchronized in the first D-type flip-flop circuit 211 according to the rise of the main clock lclk.

The logic level of the output data Q1 of the first D-type flip-flop circuit 211, which is updated synchronously according to the rise of the main clock lclk corresponding to the rise of the input clock Clk, becomes the master clock corresponding to the rise of the second delayed clock Clk_d2. Updating update of pulse lclk. In addition, in this embodiment, the two-input logic exclusive OR gate 225, the two-input logic AND gate 227, the two-input logic OR gate 229, and the first D-type flip-flop circuit 211 are examples of the resynchronization circuit of the present invention. .

An example of the case where the input data DATA is not resynchronized in the first D-type flip-flop circuit 211 will be described with reference to FIG. 2 .

At time t11, the logic level of the input data DATA changes from LOW to HIGH. At time tc1, the input data whose logic level is HIGH is synchronized in the first D-type flip-flop circuit 211 according to the rise of the main clock lclk corresponding to the rise of the input clock Clk. The logic level of the output data Q1 of the first D-type flip-flop circuit 211 becomes HIGH after a time t12 slightly delayed from the time tc1 when the input clock Clk rises. At time tc2, the input data DATA whose logic level is HIGH is synchronized in the second D-type flip-flop circuit 213 according to the rise of the first delayed clock Clk_d1. The logic level of the output data Q2 of the second D-type flip-flop circuit 213 becomes HIGH after a time t13 slightly delayed from the time tc2 when the first delayed clock Clk_d1 rises.

Although the logic level of the control signal qchk is HIGH from time t12 to time t13, it becomes LOW after time t13. At the time tc3 when the second delayed clock Clk_d2 rises, since the logic levels of the output data Q1 and Q2 are the same, the logic level of the control signal qchk is LOW, and the adaptive second delayed clock cclk is not generated. Therefore, resynchronization in the first D-type flip-flop circuit 211 does not occur according to the rise of the main clock lclk corresponding to the rise of the second delayed clock Clk_d2. By synchronizing with the rise of the main clock lclk corresponding to the rise of the input clock Clk, the logic level of the output data Q1 of the first D-type flip-flop circuit 211 updated at time t12 is maintained. In the first D-type flip-flop circuit 211, the output data Q1 that is only synchronized once is then synchronized in the third D-type flip-flop circuit 215 at the moment when the second delayed clock Clk_d2 rises, as The output data Q3 is output from the output terminal Q of the third D-type flip-flop circuit 215 .

Referring to FIG. 3, the output data Q1 of the first D-type flip-flop circuit 211 becomes a metastable state. Therefore, the input data DATA is generated in the first D-type according to the rise of the main clock lclk corresponding to the rise of the second delayed clock Clk_d2. An example of the case of resynchronization in the flip-flop circuit 211.

At time tc1, the input data DATA whose logic level changes from LOW to HIGH is synchronized in the first D-type flip-flop circuit 211 according to the rise of the main clock lclk corresponding to the rise of the input clock Clk. However, the output data Q1 of the first D-type flip-flop circuit 211 becomes a metastable state after time tc1 because there is no necessary setting boundary/sustaining boundary for the input data DATA of the input clock Clk. In addition, through the resynchronization described later, after the time t22, the logic level of the output data Q1 of the first D-type flip-flop circuit 211 is stable at HIGH. At time tc2, the input data DATA whose logic level is HIGH is synchronized in the second D-type flip-flop circuit 213 according to the rise of the first delayed clock Clk_d1. The logic level of the output data Q2 of the second D-type flip-flop circuit 213 becomes HIGH after a time t21 slightly delayed from the time tc2 when the first delayed clock Clk_d1 rises.

As mentioned above, the output data Q1 of the first D-type flip-flop circuit 211 is in a metastable state during the period from time tc1 to time t22. However, in the two-input logical exclusive OR gate 225, the logic level is judged is LOW. If the logic levels of the output data Q1 and Q2 are different, the logic level of the control signal qchk output from the two-input logic exclusive OR gate 225 will become HIGH. Therefore, the logic level of the control signal qchk becomes HIGH from time t21.

At the moment tc3 when the second delayed clock Clk_d2 rises, the logic level of the control signal qchk is HIGH, and the adaptive second delayed clock cclk also rises. Although not shown in the figure, around the time tc3, the logic level of the input clock Clk is LOW, and the main clock lclk corresponding to the rising of the adaptive second delayed clock cclk also rises.

Therefore, resynchronization is performed in the first D-type flip-flop circuit 211 according to the rising of the main clock lclk corresponding to the rising of the second delayed clock Clk_d2. At time t22, the logic level of the output data Q1 of the first D-type flip-flop circuit 211 and the logic level of the input data DATA are updated to the same HIGH, and the logic level of the control signal qchk becomes LOW. The output data Q1 resynchronized in the first D-type flip-flop circuit 211 is then synchronized in the third D-type flip-flop circuit 215 at the rising moment of the second delay clock Clk_d2, as the output data Q3 from the first D-type flip-flop circuit The output terminal Q of the triple-D flip-flop circuit 215 is output.

Referring to FIG. 4, it is illustrated that the output data Q2 of the second D-type flip-flop circuit 213 is in a metastable state, so the input data DATA is generated in the first D-type according to the rise of the main clock lclk corresponding to the rise of the second delayed clock Clk_d2. An example of the case of resynchronization in the flip-flop circuit 211.

At time tc1, the input data DATA whose logic level is LOW is synchronized in the first D-type flip-flop circuit 211 according to the rise of the main clock lclk corresponding to the rise of the input clock Clk. The logic level of the output data Q1 of the first D-type flip-flop circuit 211 becomes LOW after a time t31 slightly delayed from the time tc1 when the input clock Clk rises. In addition, in the example shown in FIG. 4, the logic level of the output data Q1 of the first D-type flip-flop circuit 211 is also LOW before time t31. At time tc2, the input data DATA whose logic level changes from LOW to HIGH is synchronized in the second D-type flip-flop circuit 213 according to the rise of the first delayed clock Clk_d1. However, the output data Q2 of the second D-type flip-flop circuit 213 becomes a metastable state after the time tc2 because the necessary setting boundary/sustaining boundary for the input data DATA of the first delayed clock Clk_d1 is not ensured. In addition, after the time tc3, the logic level of the output data Q2 of the second D-type flip-flop circuit 213 is stable at HIGH.

Therefore, during the period from time tc2 to time tc3, although the output data Q2 of the second D-type flip-flop circuit 213 is in a metastable state, in the two-input logic exclusive OR gate 225, the logic level is judged to be HIGH . Since the logic levels of the output data Q1 and Q2 are different, after time tc2, the logic level of the control signal qchk output from the two-input logic exclusive OR gate 225 is HIGH. At the time tc3 when the second delayed clock Clk_d2 rises, the logic level of the control signal qchk is HIGH, and the adaptive second delayed clock cclk also rises. Although not shown in the figure, around the time tc3, the logic level of the input clock Clk is LOW, and the main clock lclk corresponding to the rise of the adaptive second delayed clock cclk also rises.

Therefore, according to the rise of the main clock lclk corresponding to the rise of the second delayed clock Clk_d2, resynchronization is performed in the first D-type flip-flop circuit 211. At time t32, the output data of the first D-type flip-flop circuit 211 The logic level of Q1 and the logic level of the input data DATA are updated to the same HIGH. The output data Q1 resynchronized in the first D-type flip-flop circuit 211 is then synchronized in the third D-type flip-flop circuit 215 at the rising moment of the second delay clock Clk_d2, as the output data Q3 from the first D-type flip-flop circuit The output terminal Q of the triple-D flip-flop circuit 215 is output.

In addition, if the sum of the first specific delay time through the delay circuit 221 and the second specific delay time through the delay circuit 223 is longer than the period during which the input data DATA maintains the same logic level (for example: the clock pulse of the input data DATA period) is shorter, the output data Q3 can be stably output from the synchronization circuit 201, and even if the output data Q1 becomes a metastable state through the initial synchronization, the stable output data Q1 can be obtained through resynchronization.

Fig. 5 shows the synchronization circuit 203 based on the second embodiment. When the synchronous circuit 203 is compared with the synchronous circuit 201 based on the first implementation type, there are the following differences: the first D-type flip-flop circuit 211 and the second D-type flip-flop circuit 213 are respectively replaced by the first latch The circuit 241 and the second latch circuit 243; the third D-type flip-flop circuit 215 are omitted.

In addition, when referring to Fig. 1 and Fig. 5, when the synchronous circuit 203 is compared with the synchronous circuit 201 based on the first embodiment, there are the following differences: the input clock Clk, the first delayed clock Clk_d1 and the second The delayed clock Clk_d2 is respectively replaced by the input strobe signal Str, the first delayed strobe signal str_d1 and the second delayed strobe signal str_d2. The input strobe signal Str, the first delayed strobe signal str_d1, and the second delayed strobe signal str_d2 are other examples of the first synchronization signal, the second synchronization signal, and the third synchronization signal of the present invention, respectively. Furthermore, there is a difference in that the adaptive second delayed clock cclk and the main clock lclk are respectively replaced by the adaptive second delayed strobe signal sstr and the main strobe signal lstr.

As shown in FIG. 9, at the rising time tc1 of the input clock Clk, the input strobe signal Str falls. At the rising time tc2 of the first delayed clock Clk_d1, the first delayed strobe signal str_d1 falls. At the rising time tc3 of the second delayed clock Clk_d2, the second delayed strobe signal str_d2 falls.

In addition, the adaptive second delayed strobe signal sstr is similar to the adaptive second delayed clock cclk, and is generated when the logic level of the control signal qchk is HIGH, otherwise it is not generated. When the adaptive second delayed strobe signal sstr is generated, the adaptive second delayed strobe signal sstr falls at the same timing as when the adaptive second delayed clock cclk rises. The main strobe signal lstr for the first synchronization falls at the same timing as the main clock lclk for the first synchronization rises. In addition, the main strobe signal lstr for resynchronization falls at the same timing as the main clock lclk for resynchronization rises.

Generally speaking, the D-type flip-flop circuit is set to output data synchronously with the rising of the input data and the input clock. On the contrary, the latch circuit outputs the input data as output data while the logic level of the strobe signal is HIGH, but maintains the output data having the logic level of the input data when the strobe signal falls. Therefore, the first latch circuit 241 and the second latch circuit 243 based on the second implementation mode are respectively connected with the first D-type flip-flop circuit 211 and the second D-type flip-flop circuit 213 based on the first implementation mode. Do the same. Because the D-type flip-flop circuit is replaced by a latch circuit, the circuit scale can be reduced.

In the second embodiment, there is no third latch circuit corresponding to the third D-type flip-flop circuit 215 in the first embodiment. However, a third latch circuit corresponding to the third D-type flip-flop circuit 215 may also be provided.

In DRAM, there is a refresh circuit for recharging the memory cells which slowly reduces the accumulated charge. In the update circuit, there are cases where the temperature data referred to in the update rate control is composed of a plurality of bits. The temperature data composed of multiple bits is used as the input data to the synchronous circuit, and the need for clock transfer occurs. The synchronous circuit based on the first embodiment and the synchronous circuit based on the second embodiment process input data consisting of only 1 bit, however, for example, if only a plurality of synchronous circuits that process only 1 bit In the parallel arrangement, the operation of the synchronous circuit will be different between the bits, and the clock conversion cannot be performed correctly. In other words, although resynchronization occurs in the synchronous circuit corresponding to a certain bit, resynchronization does not occur in the synchronous circuit corresponding to other bits. In such a case, correct clock conversion cannot be performed. The synchronous circuit based on the third embodiment is created in order not to cause such a problem.

FIG. 6 shows a synchronization circuit 205 based on the third embodiment. In the synchronization circuit 203 based on the second embodiment, the number of bits of the input data DATA is 1, and in the synchronization circuit 205 based on the third embodiment, the number of bits of the input data DATA is a complex number n (n is more than 2 integer).

When comparing the synchronization circuit 205 based on the third implementation type with the synchronization circuit 203 based on the second implementation type, the following points are different: the first latch circuit 241, the second latch circuit 243, and the two input logic mutual exclusion The OR gate 225 is replaced by a plurality (n here) of first latch circuits 241-1~241-n, and a plurality (n here) of second latch circuits 243-1~241-n, respectively. 243-n and two input logic exclusive OR gates 225-1~225-n of a plurality (n in this case); and n input logic OR gates 231 are added.

A plurality of first latch circuits 241-1~241-n latch n-bit input data DATA<n:1> through the main selection signal lstr, and output it as n-bit output data Q1<n:1> . The plurality of second latch circuits 243-1~243-n latch the n-bit input data DATA<n:1> through the first delay strobe signal str_d1 as the n-bit output data Q2<n:1 > output. The i-th input logic mutual exclusion OR gate 225-i (i=1,2,...,n) of the i-th input logic mutual exclusion OR gate 225-i (i=1,2,...,n) of the complex number 225-1~225-n calculates the output data Q1<n: The logical exclusive OR of the i-th bit of 1> and the i-th bit of the output data Q2<n:1> is output as the i-th bit of the preliminary control signal Qchk<n:1>. The n-input OR gate 231 performs OR calculation of the preliminary control signal Qchk<n:1>, and supplies the control signal QchkN indicating the result to the input terminal on one side of the two-input OR gate 227 from the output terminal. The two-input logic AND gate 227 and the two-input logic OR gate 229 are the same as those of the second embodiment.

Then, the output data Q1<n:1> and the output data Q2<n:1> are compared for each bit by a plurality of two-input logic exclusive OR gates 225-1˜225-n. If a plurality of two-input logic exclusive OR gates 225-1~225-n are outputting the preparation control signal Qchk<n:1>, the output data Q1<n:1> and the output data Q2<n:1> are at least 1 The bit is different, when the main strobe signal lstr corresponding to the fall of the adaptive second delay strobe signal sstr falls, the input data DATA<n:1> is in the plurality of first latch circuits 241-1~241 -n and then latched.

An example of the case where the n-bit input data DATA<n:1> is not re-latched in the plurality of first latch circuits 241-1˜241-n is described with reference to FIG. 7 .

When the main strobe signal lstr falls corresponding to the fall of the input strobe signal Str, the n-bit input data DATA<n:1> is latched in a plurality of first latch circuits 241-1˜241-n. Therefore, the output data Q1<n:1> of the plurality of first latch circuits 241-1~241-n changes at a time t41 slightly delayed from the time tc1 when the input strobe signal Str falls.

When the first delayed strobe signal str_d1 falls, the n-bit input data DATA<n:1> is latched in the second latch circuits 243-1˜243-n. Therefore, the output data Q2<n:1> of the plurality of second latch circuits 243-1~243-n changes at the time t42 slightly delayed from the time tc2 when the first delayed strobe signal str_d1 falls.

During the period from time t41 to time t42, the logic levels of at least a part of the output data Q2<n:1> of the plurality of second latch circuits 243-1˜243-n become the same as the complex number The corresponding bits of the output data Q1<n:1> of the first latch circuits 241-1~241-n are inconsistent. Therefore, at least one logic level of the preparation control signal Qchk<n:1> output by the plurality of two-input logic exclusive OR gates 225-1~225-n becomes HIGH, and the control signal QchkN output by the n-input logic OR gate 231 becomes HIGH. The logic level becomes HIGH.

After time t42, the logic level of the output data Q2<n:1> of the plurality of second latch circuits 243-1~243-n is the same as the output of the plurality of first latch circuits 241-1~241-n The logic levels of the data Q1<n:1> are consistent in all bits. Therefore, the logic levels of all the preliminary control signals Qchk<n:1> output by the plurality of two-input logic exclusive OR gates 225-1~225-n become LOW, and the logic levels of the control signal QchkN output by the n-input logic OR gate 231 The level becomes LOW.

At the moment tc3 when the second delayed strobe signal str_d2 falls, the logic level of the control signal QchkN becomes LOW, therefore, the adaptive second delayed strobe signal sstr and the main strobe signal lstr do not fall, and do not occur in multiple In the re-latching in the first latch circuits 241-1~241-n, the logic levels of the output data Q1<n:1> of the latched plural first latch circuits 241-1~241-n are different. Update by re-latch, maintain the original state.

In addition, from the time tc3 to the time t43, during the period of tTRAN, even if the n-bit input data DATA<n:1> changes, the output data Q1 of the plurality of first latch circuits 241-1~241-n The logic level of <n:1> remains the same. The n-bit input data DATA<n:1> changes with bit shift between time tc3 and time t43.

Referring to FIG. 8, when the main strobe signal lstr falls corresponding to the fall of the second delayed strobe signal str_d2, n-bit input data DATA<n:1> is displayed in the plurality of first latch circuits 241-1~241. An example of the case of re-latch in -n.

The n-bit input data DATA<n:1> is latched in a plurality of first latch circuits 241-1˜241-n according to the fall of the main strobe signal lstr corresponding to the fall of the input strobe signal Str. Therefore, the output data Q1<n:1> of the plurality of first latch circuits 241-1~241-n changes at the time t51 slightly delayed from the time tc1 when the input signal falls.

Similar to the situation in FIG. 7, starting from time t51, the logic levels of at least a part of the bits of the output data Q1<n:1> of the plurality of first latch circuits 241-1~241-n become It is inconsistent with the corresponding bits of the output data Q2<n:1> of the plurality of second latch circuits 243-1˜243-n. Therefore, starting from time t51, at least one logic level of the preliminary control signal Qchk<n:1> output by the plurality of two-input logic exclusive OR gates 225-1~225-n becomes HIGH, and the n-input logic OR gate 231 outputs The logic level of the control signal QchkN becomes HIGH.

Different from the example in FIG. 7 , the logic level of the n-bit input data DATA<n:1> changes around the time tc2 when the first delayed strobe signal str_d1 falls. The n-bit input data DATA<n:1> is set to be latched in a plurality of second latch circuits 243 - 1 - 243 -n according to the fall of the first delayed strobe signal str_d1 .

Assuming that at time tc2, the logic level of each bit of the n-bit input data DATA<n:1> is the same as the logic level of the bit corresponding to the n-bit input data DATA<n:1> at time tc1, After the time t52 corresponding to the time t42 in FIG. 7 , the logic level of the control signal QchkN becomes LOW. In addition, the case where the logic level of the control signal QchkN becomes LOW after time t52 is not shown in FIG. 8 .

As mentioned above, before and after the time tc2, due to the change of the logic level of the n-bit input data DATA<n:1>, there is no set boundary/maintain boundary required for the falling of the first delay strobe signal str_d1 by the input data DATA. Therefore, at least some bits of the output data Q2<n:1> of the plurality of second latch circuits 243-1~243-n become metastable. Or, the logic levels of at least some bits of the output data Q2<n:1> of the plurality of second latch circuits 243-1~243-n are the same as those of the plurality of first latch circuits 241-1~241 The logical level of the corresponding bit of the output data Q1<n:1> of -n remains inconsistent. Therefore, after the time t51, the logic level of the output of at least a part of the gates included in the plurality of two-input logic exclusive OR gates 225-1~225-n whose logic level becomes HIGH corresponds to the time t42 in FIG. 7 HIGH is also maintained after time t52. Therefore, as shown in FIG. 8, the logic level of the control signal QchkN remains HIGH after the time t52.

At the moment tc3 when the second delay strobe signal str_d2 falls, the logic level of the control signal QchkN is HIGH, and the adaptive second delay strobe signal sstr also falls. When the main strobe signal lstr falls corresponding to the fall of the adaptive second delay strobe signal sstr, the input data DATA<n:1> is re-latched in a plurality of first latch circuits 241-1~241-n . Therefore, at time t53, the logic levels of the output data Q1<n:1> of the plurality of first latch circuits 241-1~241-n are updated.

In addition, if the sum of the first specific delay time via the delay circuit 221 and the second specific delay time via the delay circuit 223 is set to be longer than the period during which the input data DATA maintains the same logic level (for example: input data DATA The time obtained by subtracting the maximum offset time is shorter, the output data Q3 can be stably output from the synchronization circuit 205, and even if the output data Q1 becomes metastable after the initial synchronization, it can be obtained by resynchronization Stable output data Q1.

201, 203, 205: synchronous circuit

211: The first D-type flip-flop circuit

213: The second D-type flip-flop circuit

215: The third D-type flip-flop circuit

221, 223: delay circuit

225: Two-input logic exclusive OR gate

227: Two-input logic AND gate

229: two-input logic OR gate

241: The first latch circuit

243: The second latch circuit

225-1~225-n: Multiple two-input logic exclusive OR gates

241-1~241-n: a plurality of first latch circuits

243-1~243-n: a plurality of second latch circuits

cclk: adaptive second delay clock

CK: clock terminal

Clk: input clock

Clk_d1: the first delay clock

Clk_d2: second delay clock

D: input terminal

DATA: input data

DATA<n:1>: n-bit input data

lclk: main clock

lstr: master selection signal

qchk: control signal

QchkN: control signal

Qchk<n:1>: ready control signal

sstr: adaptive second delay strobe signal

Q: output terminal

Q1, Q2, Q3: output data

Q1<n:1>, Q2<n:1>: output data

Str: input strobe signal

str_d1: first delay strobe signal

str_d2: second delay strobe signal

t11, t12, t13: time

t21, t22: time

t31, t32: time

t41, t42, t43: time

t51, t52, t53: time

tc1, tc2, tc3: time

[FIG. 1] is a circuit diagram showing the configuration of a synchronous circuit according to the first embodiment of the present invention. [FIG. 2] It is a timing chart showing an example of operation when the synchronization circuit shown in FIG. 1 does not perform resynchronization. [FIG. 3] is a timing chart showing a first example of operation when the synchronization circuit shown in FIG. 1 executes resynchronization. [FIG. 4] is a timing chart showing a second example of operation in the case where the synchronization circuit shown in FIG. 1 executes resynchronization. [FIG. 5] is a circuit diagram showing the configuration of a synchronous circuit according to the second embodiment of the present invention. [FIG. 6] is a circuit diagram showing the constitution of a synchronous circuit according to the third embodiment of the present invention. [FIG. 7] It is a timing chart showing an operation example in the case where the synchronization circuit shown in FIG. 6 does not perform resynchronization. [FIG. 8] It is a timing chart showing an operation example in the case where the synchronization circuit shown in FIG. 6 executes resynchronization. [Fig. 9] is a timing diagram showing the corresponding relationship between the clock in the synchronous circuit based on the first embodiment and the data strobe signal in the synchronous circuit based on the second embodiment shown in Fig. 5 .

201: Synchronous circuit

211: The first D-type flip-flop circuit

213: The second D-type flip-flop circuit

215: The third D-type flip-flop circuit

221, 223: delay circuit

225: Two-input logic exclusive OR gate

227: Two-input logic AND gate

229: two-input logic OR gate

cclk: adaptive second delay clock

CK: clock terminal

Clk: input clock

Clk_d1: the first delay clock

Clk_d2: second delay clock

D: input terminal

DATA: input data

1clk: main clock

qchk: control signal

Q: output terminal

Q1, Q2, Q3: output data

Claims (13)

A synchronous circuit, comprising: a first delay circuit, which delays an input synchronous signal by a first specific time to generate a first delayed synchronous signal; a second delay circuit, which delays the aforementioned first delayed synchronous signal by a second specific time, to generate a second delay Synchronization signal; the first synchronization circuit, outputting the first output data synchronizing the input data with the aforementioned input synchronizing signal; the second synchronizing circuit, outputting the second output data synchronizing the aforementioned input data with the aforementioned first delayed synchronizing signal; resynchronization The circuit, if the first output data is inconsistent with the second output data, resynchronizes the input data according to the second delayed synchronization signal, and updates the first output data to the first synchronization circuit. The synchronous circuit according to claim 1 further includes: a third synchronous circuit, outputting third output data synchronizing the first output data with the second delayed synchronous signal. The synchronous circuit according to claim 1 or 2, wherein the sum of the first specified time and the second specified time is shorter than the minimum holding time of the input data. The synchronous circuit as claimed in claim 1, wherein: the aforementioned input data, the aforementioned first output data, and the aforementioned second output data respectively include a plurality of bits; If at least one bit of the first output data is inconsistent with the second output data, the resynchronization circuit resynchronizes the input data according to the second delayed synchronization signal, and updates the first output data to the first synchronization circuit. The synchronous circuit according to claim 1, wherein the first synchronous circuit is a first D-type flip-flop circuit, and the second synchronous circuit is a second D-type flip-flop circuit. The synchronous circuit according to claim 1, wherein the first synchronous circuit is a first latch circuit, and the second synchronous circuit is a second latch circuit. Such as the synchronous circuit of claim item 5, wherein the aforementioned resynchronization circuit includes two input logic mutual exclusive OR gates, which take the output data from the output terminal of the aforementioned first D-type flip-flop circuit, and the output data from the aforementioned second D-type flip-flop circuit The logical exclusive OR of the output data of the output terminal of the circuit, output the control signal of the display result, if the logic level of the output data from the output terminal of the aforementioned first D-type flip-flop circuit is the same as that from the aforementioned second D-type flip-flop The logic level of the output data of the output terminal of the circuit is consistent, the logic level of the aforementioned control signal is a low level, and if not consistent, it is a high level. Such as the synchronous circuit of claim item 7, wherein the aforementioned resynchronization circuit further includes two input logic AND gates, which take the logical AND of the aforementioned control signal and the second delayed clock, and output the result as an adaptive second delayed clock, if the control signal The logic level is high, and an adaptive second delayed clock corresponding to the second delayed clock is generated. Such as the synchronous circuit of claim item 8, wherein the aforementioned resynchronization circuit further comprises two input logical OR gates, which take the logical OR of the input clock and the adaptive second delayed clock, output the result as the main clock, and control the aforementioned first The clock terminal of the D-type flip-flop circuit supplies the aforementioned main clock output from the aforementioned two input logic OR gates. Such as the synchronization circuit of claim 1, wherein the aforementioned resynchronization circuit includes: two input logical exclusive OR gates, calculating the logical exclusive OR of the i-th bit of the aforementioned first output data and the i-th bit of the aforementioned second output data , the result is output as the i-th bit of the preliminary control signal; and the n-input logic OR gate performs the logical OR calculation of the aforementioned preliminary control signal, and the control signal for displaying the result is supplied from the output terminal to one side of the two input logic-AND gates input terminal. A semiconductor device, including the synchronous circuit of claim 1. A synchronization method, comprising: a comparison step, comparing the first data that is synchronized with the input data by a synchronization signal, and the second data that synchronizes the aforementioned input data with a signal that delays the aforementioned synchronization signal; an output step, if the aforementioned first data and the aforementioned If the second data is different, output the data that synchronizes the aforementioned input data according to a signal that delays the aforementioned sync signal more; otherwise, output the aforementioned first data. Such as the synchronization method of claim 12, wherein: the aforementioned input data includes a plurality of bits; the aforementioned comparison step compares each bit of the aforementioned first data and the aforementioned second data; the aforementioned output step is between the aforementioned first data and the aforementioned second When the data has at least one bit difference, output the aforementioned data that synchronizes the aforementioned input data according to a signal that delays the aforementioned synchronous signal more; otherwise, output the aforementioned first data.

Images