CN116069710A - Bandwidth control method and device based on AXI bus and electronic equipment - Google Patents

Bandwidth control method and device based on AXI bus and electronic equipment Download PDF

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CN116069710A
CN116069710A CN202310095428.8A CN202310095428A CN116069710A CN 116069710 A CN116069710 A CN 116069710A CN 202310095428 A CN202310095428 A CN 202310095428A CN 116069710 A CN116069710 A CN 116069710A
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data
read data
determining
bandwidth
data quantity
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滕祖明
宋超
唐平
胡伟迪
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Aixin Yuanzhi Semiconductor Shanghai Co Ltd
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Aixin Yuanzhi Semiconductor Shanghai Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0038—System on Chip
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The application provides a bandwidth control method, a device and electronic equipment based on an AXI bus, and relates to the technical field of communication, wherein the method comprises the following steps: acquiring a pre-configured time window; determining the read data quantity of the time window and the write data quantity of the time window; comparing the read data quantity and the write data quantity with corresponding read data quantity threshold values and write data quantity threshold values respectively to obtain a comparison result; and according to the comparison result, adjusting the Ready signal to control the bandwidth of the AXI bus. Therefore, the read data quantity and the read data quantity threshold value in the time window are compared, the write data quantity and the write data quantity threshold value are compared, and the Ready signal is adjusted according to the comparison result, so that the bandwidth of the AXI bus is controlled, the bandwidth can be controlled in real time, the problem of competing the bandwidth of the AXI bus is reduced, and the control precision of the bandwidth is improved.

Description

Bandwidth control method and device based on AXI bus and electronic equipment
Technical Field
The present disclosure relates to the field of communications technologies, and in particular, to a bandwidth control method and apparatus based on an AXI bus, and an electronic device.
Background
At present, the on-chip interconnection bus is used for solving the requirements of data communication of all subsystems in a chip and accessing on-chip storage equipment and off-chip storage equipment, and because of the transmission rate of the data communication, the read-write speed of all subsystems on the storage equipment is provided with a bottleneck, and the storage equipment such as a double data rate synchronous dynamic random access Memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM) and a Flash Memory (Flash Memory), therefore, when all subsystems access the storage equipment at the same time, the subsystems can compete for the bandwidth of an AXI bus.
In the related art, the bandwidth control method of the AXI (Advanced eXtensible Interface) bus is to increase or decrease the data transmission priority of the corresponding subsystem by adjusting the quality of service signal (Quality of Service, qoS) of each subsystem, so as to achieve the purpose of controlling the bandwidth of the AXI bus.
However, in the above scheme, the purpose of controlling the bandwidth can be achieved only by matching the storage device, and the problem of competing the bandwidth of the AXI bus may still occur, and the control accuracy of the bandwidth is low.
Disclosure of Invention
The present application aims to solve, at least to some extent, one of the technical problems in the related art.
The application provides a bandwidth control method based on an AXI bus, which is used for comparing a read data quantity and a read data quantity threshold value in a time window with a write data quantity and a write data quantity threshold value, and adjusting a Ready signal according to a comparison result to realize the control of the bandwidth of the AXI bus, so that the bandwidth can be controlled in real time, the problem of competing the bandwidth of the AXI bus is reduced, and the control precision of the bandwidth is improved.
An embodiment of a first aspect of the present application provides a bandwidth control method based on an AXI bus, including: acquiring a pre-configured time window; determining the read data volume of the time window and the write data volume of the time window; comparing the read data quantity and the write data quantity with corresponding read data quantity threshold values and write data quantity threshold values respectively to obtain a comparison result; and according to the comparison result, adjusting the Ready signal to control the bandwidth of the AXI bus.
Optionally, the method further comprises: determining the ratio of the read data volume threshold to the time window as a read bus bandwidth threshold; and determining the ratio of the write data volume threshold value to the time window as a write bus bandwidth threshold value.
Optionally, the determining the read data amount of the time window includes: determining the read data amount of the ith communication transmission; determining the read data volume transmitted by the previous i-time communication according to the read data volume transmitted by the previous i-1 time communication and the read data volume transmitted by the ith time communication; wherein i is an integer greater than 1; and determining the read data quantity of the previous i communication transmissions as the read data quantity of the time window.
Optionally, the determining the read data amount of the ith communication transmission includes: acquiring the data length and the data bit width of the read data of the ith communication transmission; and multiplying the data length of the read data and the data bit width power of 2 to obtain a multiplication result, and determining the multiplication result as the read data quantity of the ith communication transmission.
Optionally, the determining the write data amount of the time window includes: determining the data writing quantity of the ith communication transmission; determining the data writing quantity transmitted by the previous i-time communication according to the data writing quantity transmitted by the previous i-1-time communication and the data writing quantity transmitted by the ith communication; wherein i is an integer greater than 1; and determining the write data quantity transmitted by the previous i times of communication as the write data quantity of the time window.
Optionally, the determining the write data amount of the ith communication transmission includes: acquiring the data length and the data bit width of the ith communication transmission write data; and multiplying the data length of the write data and the data bit width power of 2 to obtain a multiplication result, and determining the multiplication result as the write data quantity of the ith communication transmission.
Optionally, the adjusting the Ready signal according to the comparison result to control the bandwidth of the AXI bus includes: when the comparison result is that the read data quantity is larger than or equal to the read data quantity threshold value, carrying out low-pulling processing on a Ready signal of a read address channel of the AXI bus so as to control the bandwidth of the AXI bus; and under the condition that the read data quantity is smaller than the read data quantity threshold value as a result of the comparison, the Ready signal of the read address channel of the AXI bus is kept in an original state.
Optionally, the adjusting the Ready signal according to the comparison result to control the bandwidth of the AXI bus includes: when the comparison result is that the write data quantity is larger than or equal to the write data quantity threshold value, carrying out low-pulling processing on a Ready signal of a write address channel of the AXI bus so as to control the bandwidth of the AXI bus; and under the condition that the comparison result is that the write data quantity is smaller than the write data quantity threshold value, the Ready signal of the write address channel of the AXI bus is kept in an original state.
According to the AXI bus-based bandwidth control method, a preconfigured time window is obtained; determining the read data quantity of the time window and the write data quantity of the time window; comparing the read data quantity and the write data quantity with corresponding read data quantity threshold values and write data quantity threshold values respectively to obtain a comparison result; and according to the comparison result, adjusting the Ready signal to control the bandwidth of the AXI bus. Therefore, the read data quantity and the read data quantity threshold value in the time window are compared, the write data quantity and the write data quantity threshold value are compared, and the Ready signal is adjusted according to the comparison result, so that the bandwidth of the AXI bus is controlled, the bandwidth can be controlled in real time, the problem of competing the bandwidth of the AXI bus is reduced, and the control precision of the bandwidth is improved.
An embodiment of a second aspect of the present application proposes a bandwidth control device based on an AXI bus, including: the first acquisition module is used for acquiring a pre-configured time window; the first determining module is used for determining the read data quantity of the time window and the write data quantity of the time window; the comparison module is used for comparing the read data quantity and the write data quantity with corresponding read data quantity threshold values and write data quantity threshold values respectively to obtain comparison results; and the control module is used for adjusting the Ready signal according to the comparison result so as to control the bandwidth of the AXI bus.
As a possible implementation manner of the embodiment of the present application, the apparatus further includes: a second determination module and a third determination module; the second determining module is configured to determine a ratio of the read data amount threshold to the time window as a read bus bandwidth threshold; the third determining module is configured to determine a ratio of the write data amount threshold to the time window as a write bus bandwidth threshold.
As a possible implementation manner of the embodiment of the present application, the first determining module is specifically configured to determine an i-th data amount transmitted by communication, and determine the i-th data amount transmitted by communication according to the i-1 th data amount transmitted by communication and the i-th data amount transmitted by communication; wherein i is an integer greater than 1; and determining the read data quantity of the previous i communication transmissions as the read data quantity of the time window.
As a possible implementation manner of the embodiment of the present application, the first determining module is specifically configured to obtain a data length and a data bit width of the read data of the ith communication transmission; and multiplying the data length of the read data and the data bit width power of 2 to obtain a multiplication result, and determining the multiplication result as the read data quantity of the ith communication transmission.
As one possible implementation manner of the embodiment of the present application, the first determining module is specifically configured to determine an amount of write data of the ith communication transmission; determining the data writing quantity transmitted by the previous i-time communication according to the data writing quantity transmitted by the previous i-1-time communication and the data writing quantity transmitted by the ith communication; wherein i is an integer greater than 1; and determining the write data quantity transmitted by the previous i times of communication as the write data quantity of the time window.
As a possible implementation manner of the embodiment of the present application, the first determining module is specifically configured to obtain a data length and a data bit width of the ith communication transmission write data; and multiplying the data length of the write data and the data bit width power of 2 to obtain a multiplication result, and determining the multiplication result as the write data quantity of the ith communication transmission.
As a possible implementation manner of the embodiment of the present application, the control module is specifically configured to pull down a Ready signal of a read address channel of the AXI bus to control a bandwidth of the AXI bus when the comparison result is that the read data amount is greater than or equal to the read data amount threshold; and under the condition that the read data quantity is smaller than the read data quantity threshold value as a result of the comparison, the Ready signal of the read address channel of the AXI bus is kept in an original state.
As a possible implementation manner of the embodiment of the present application, the control module is specifically configured to pull down a Ready signal of a write address channel of the AXI bus to control a bandwidth of the AXI bus when the comparison result is that the write data amount is greater than or equal to the write data amount threshold; and under the condition that the comparison result is that the write data quantity is smaller than the write data quantity threshold value, the Ready signal of the write address channel of the AXI bus is kept in an original state.
According to the AXI bus-based bandwidth control device, a preconfigured time window is obtained; determining the read data quantity of the time window and the write data quantity of the time window; comparing the read data quantity and the write data quantity with corresponding read data quantity threshold values and write data quantity threshold values respectively to obtain a comparison result; and according to the comparison result, adjusting the Ready signal to control the bandwidth of the AXI bus. Therefore, the read data quantity and the read data quantity threshold value in the time window are compared, the write data quantity and the write data quantity threshold value are compared, and the Ready signal is adjusted according to the comparison result, so that the bandwidth of the AXI bus is controlled, the bandwidth can be controlled in real time, the problem of competing the bandwidth of the AXI bus is reduced, and the control precision of the bandwidth is improved.
An embodiment of a third aspect of the present application proposes a bandwidth control module, including: the device comprises a time counting unit, a data counting unit and a data limiting unit; the time counting unit is respectively connected with the data statistics unit and the data limiting unit, and generates a marking signal at the tail end of each time window for marking each time window; the data statistics unit is respectively connected with the time counting unit and the data limiting unit and is used for counting the read data quantity and the write data quantity of the time window; the data limiting unit is used for comparing the read data quantity and the write data quantity with corresponding read data quantity threshold values and write data quantity threshold values respectively to obtain comparison results, and adjusting the Ready signal according to the comparison results to control the bandwidth of the AXI bus.
An embodiment of a fourth aspect of the present application proposes a chip, including: and the bandwidth control module is used for executing the AXI bus-based bandwidth control method provided by the embodiment of the first aspect of the application.
An embodiment of a fifth aspect of the present application proposes an electronic device, including: at least one processor; and a memory communicatively coupled to the at least one processor; the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the AXI bus-based bandwidth control method according to the embodiment of the first aspect of the present application.
Embodiments of a sixth aspect of the present application provide a non-transitory computer readable storage medium storing computer instructions for causing a computer to execute the AXI bus-based bandwidth control method according to the embodiments of the first aspect of the present application.
Embodiments of a seventh aspect of the present application propose a computer program product, which when executed by an instruction processor in the computer program product, performs the AXI bus based bandwidth control method proposed by the embodiments of the first aspect of the present application. Additional aspects and advantages of the application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the application.
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The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:
fig. 1 is a flowchart of a bandwidth control method based on AXI bus according to an embodiment of the present application;
fig. 2 is a flow chart of a bandwidth control method based on AXI bus according to a second embodiment of the present application;
FIG. 3 is a schematic diagram of a method of controlling bandwidth based on an AXI bus;
Fig. 4 is a schematic structural diagram of an AXI bus-based bandwidth control device according to a third embodiment of the present application;
fig. 5 is a block diagram of an electronic device for an AXI bus-based bandwidth control method, according to an exemplary embodiment.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and intended for the purpose of explaining the present application and are not to be construed as limiting the present application.
The application provides a bandwidth control method and device based on an AXI bus and electronic equipment.
Fig. 1 is a flow chart of an AXI bus-based bandwidth control method according to an embodiment of the present application, and it should be noted that the AXI bus-based bandwidth control method may be applied to an AXI bus-based bandwidth control device. The bandwidth control device based on the AXI bus may be, for example, an electronic device, or software installed in the electronic device. The bandwidth control device based on the AXI bus will be described as an example of the execution body.
The electronic device may be any device with computing capability, and the device with computing capability may be, for example, a personal computer (Personal Computer, abbreviated as PC), a server, or the like.
As shown in fig. 1, the AXI bus-based bandwidth control method includes the steps of:
step 101, a preconfigured time window is obtained.
The preconfigured time window may be denoted as t, and the range of t may be defined according to actual needs, which is not limited herein.
For example, the period of the clock in 24MHz (megahertz) may be 41.67ns (nanoseconds), the 41.67ns is shifted left by 4 bits, that is, 666.7ns, and the time window t may be configured in a range of 666.7ns to 42666.7ns.
The number of the time windows may be 1 or plural, which is not limited herein.
It should be noted that, the AXI bus communicates through the AXI protocol, where the AXI protocol includes five channels, and the different channels are independent and different from each other, and before communicating through the channels, a Valid signal (handshake signal) and a Ready signal (handshake signal) are required to be used to handshake, where the five channels are a read address channel, a read data channel, a write address channel, a write data channel, and a write response channel, respectively.
Step 102, determining the read data amount of the time window and the write data amount of the time window.
Wherein a flag signal is present at the end of each time window for marking each time window, at which flag signal the read data amount and the write data amount of that time window will be cleared so that the read data amount and the write data amount can be re-determined in the next time window.
The communication transmission may be performed once or multiple times in each time window, that is, multiple handshakes may be performed in each time window, and the number of successful handshakes may be one or multiple times, which is not limited herein specifically.
In some embodiments, as a possible implementation, the process of determining the read data amount of the time window by the AXI bus based bandwidth control device may, for example, determine the read data amount of the ith communication transmission; determining the read data volume transmitted by the previous i-1 times of communication according to the read data volume transmitted by the previous i-1 times of communication and the read data volume transmitted by the ith time of communication; wherein i is an integer greater than 1; and determining the read data quantity of the previous i communication transmissions as the read data quantity of the time window.
In some embodiments, the process of determining the read data amount of the ith communication transmission by the AXI bus-based bandwidth control device may be to obtain the data length and the data bit width of the read data of the ith communication transmission; and multiplying the data length of the read data and the data bit width power of 2 to obtain a multiplication result, and determining the multiplication result as the read data quantity of the ith communication transmission.
When i is 1, the bandwidth control device based on the AXI bus can acquire the data length and the data bit width of the read data of the 1 st communication transmission; and multiplying according to the data length of the read data and the power of 2 data bit width to obtain a multiplication result, and determining the multiplication result as the read data quantity of the 1 st communication transmission.
The number of times that the sender (each subsystem) and the receiver (storage device) can communicate in a single time window may be one or more, which is not limited herein specifically.
Wherein the subsystem may comprise: camera module, image acceleration module, artificial intelligence module etc..
The data length and the data bit width of the read data may be the same or different in each communication transmission, which is not particularly limited herein.
The read data quantity of the time window is the accumulated result of the read data quantity of the plurality of communication transmissions.
It should be noted that, when the vaill signal and the Ready signal of the read address channel of the AXI bus are both high, a handshake recorded as the read address channel is successful, and communication can be performed.
For example, the data amount of the previous i-th communication transmission is determined according to the data amount of the previous i-1 th communication transmission and the data amount of the ith communication transmission, and the calculation formula can be shown as formula (1).
r_data i ＝r_data i-1 +(arlen+1)*2 arsize Formula (1)
Wherein r_data i Indicating the read data quantity of the previous i communication transmissions, in bytes, r_data i-1 Indicating the read data amount of the previous i-1 communication transmission, "arlen+1" indicates the read data of the ith communication transmissionThe arsize indicates the width of the read data of the ith communication transmission.
In some embodiments, as another possible implementation, the process of determining the write data amount of the time window by the AXI bus based bandwidth control device may, for example, determine the write data amount of the ith communication transmission; determining the data writing quantity transmitted by the previous i-time communication according to the data writing quantity transmitted by the previous i-1-time communication and the data writing quantity transmitted by the ith communication; wherein i is an integer greater than 1; and determining the write data quantity transmitted by the previous i times of communication as the write data quantity of the time window.
In some embodiments, the process of determining the write data amount of the ith communication transmission by the AXI bus-based bandwidth control device may be to obtain the data length and the data bit width of the write data of the ith communication transmission; and multiplying the data length of the write data and the data bit width power of 2 to obtain a multiplication result, and determining the multiplication result as the write data quantity of the ith communication transmission.
When i is 1, the bandwidth control device based on the AXI bus can acquire the data length and the data bit width of the 1 st communication transmission write data; and multiplying according to the data length of the write data and the power of 2 data bit width to obtain a multiplication result, and determining the multiplication result as the write data quantity of the 1 st communication transmission.
The data length and the data bit width of the write data may be the same or different in each communication transmission, and are not particularly limited herein.
The data writing quantity of the time window is the accumulated result of the data writing quantity transmitted by multiple times of communication.
When the vaill and Ready signals of the write address channel of the AXI bus are simultaneously high, the one-time handshake recorded as the write address channel is successful, and communication can be performed.
For example, the data amount transmitted in the previous i-time communication is determined according to the data amount transmitted in the previous i-1-time communication and the data amount transmitted in the ith communication, and the calculation formula can be shown as formula (2).
w_data i ＝w_data i-1 +(awlen+1)*2 awsize Formula (2)
Wherein w_data i Representing the data writing quantity of the previous i times of communication transmission, wherein the unit is Byte, w_data i-1 Indicating the write data amount of the previous i-1 communication transmission, "awlen+1" indicates the data length of the i-th communication transmission write data, and awsize indicates the width of the i-th communication transmission write data.
And 103, comparing the read data quantity and the write data quantity with corresponding read data quantity threshold values and write data quantity threshold values respectively to obtain a comparison result.
Wherein, the read data quantity threshold value can be configured in advance according to actual needs, for example, the read data quantity threshold value can be 1 Byte-2 16 (65535) Byte, not limited herein. Wherein, the write data quantity threshold value can be configured in advance according to actual needs, for example, the write data quantity threshold value can be 1 Byte-2 16 (65535) Byte, not limited herein.
In this embodiment of the present application, in each time window, the AXI bus-based bandwidth control device compares the read data amount with the corresponding read data amount threshold, and compares the write data amount with the corresponding write data amount threshold, so as to obtain a comparison result, where the comparison result may be multiple, and the specific number is not limited herein.
In this embodiment of the present application, during each time window, each time a communication transmission is performed, the AXI bus-based bandwidth control device compares the read data amount with the corresponding read data amount threshold value once, and compares the write data amount with the corresponding write data amount threshold value once.
And 104, adjusting the Ready signal according to the comparison result to control the bandwidth of the AXI bus.
In some embodiments, the bandwidth of the AXI bus is controlled by adjusting the Ready signal, and the bandwidth threshold (read bus bandwidth threshold, write bus bandwidth threshold) obtained by the control may be calculated.
As a possible implementation manner, the AXI bus-based bandwidth control device may further determine a ratio of the read data amount threshold to the time window as a read bus bandwidth threshold; the ratio of the write data amount threshold to the time window is determined as the write bus bandwidth threshold.
The calculation formula of the read bus bandwidth threshold may be shown in formula (3).
Figure BDA0004079650700000121
Where r_bandwidth is the read bus bandwidth threshold in MB/s, r_thr is the read data amount threshold, MB (MByte, megabyte) is the read data amount threshold in time window, and t is the time window in s (seconds).
The calculation formula of the read bus bandwidth threshold may be shown in formula (4).
Figure BDA0004079650700000122
Where w_bandwidth is the write bus bandwidth threshold, the unit is MB/s, and w_thr is the write data amount threshold.
In summary, a preconfigured time window is obtained; determining the read data quantity of the time window and the write data quantity of the time window; comparing the read data quantity and the write data quantity with corresponding read data quantity threshold values and write data quantity threshold values respectively to obtain a comparison result; and according to the comparison result, adjusting the Ready signal to control the bandwidth of the AXI bus. Therefore, the read data quantity and the read data quantity threshold value in the time window are compared, the write data quantity and the write data quantity threshold value are compared, and the Ready signal is adjusted according to the comparison result, so that the bandwidth of the AXI bus is controlled, the bandwidth can be controlled in real time, the problem of competing the bandwidth of the AXI bus is reduced, and the control precision of the bandwidth is improved.
Fig. 2 is a flow chart of a bandwidth control method based on AXI bus according to a second embodiment of the present application. As shown in fig. 2, the AXI bus-based bandwidth control method includes the steps of:
step 201, a preconfigured time window is obtained.
Step 202, determining the read data amount of the time window and the write data amount of the time window.
And 203, comparing the read data quantity and the write data quantity with corresponding read data quantity threshold values and write data quantity threshold values respectively to obtain a comparison result.
It should be noted that, the details of step 201 to step 203 may refer to the relevant content in the above embodiment, and will not be described herein.
Step 204, in the case that the read data amount is greater than or equal to the read data amount threshold, the Ready signal of the read address channel of the AXI bus is pulled down to control the bandwidth of the AXI bus.
In this embodiment of the present application, when the read data amount of the time window is greater than or equal to the read data amount threshold, the AXI bus-based bandwidth control device may pull the Ready signal of the read address channel of the AXI bus of the time window down, and back-pressure the data transmission of the AXI bus, that is, block the transmission of the read data, so as to implement control of the bandwidth of the AXI bus.
In this embodiment of the present application, during each time window, each time a communication transmission is performed, the bandwidth control device based on the AXI bus compares the read data amount with the corresponding read data amount threshold once, and when the read data amount is greater than or equal to the read data amount threshold, the Ready signal is pulled down until the next time window, that is, until the next time window, no handshake is successful, and no further accumulation operation of the read data amount is performed.
In step 205, in the case that the read data amount is smaller than the read data amount threshold as a result of the comparison, the Ready signal of the read address channel of the AXI bus is kept in the original state.
In the embodiment of the present application, in the case where the read data amount of the time window is smaller than the read data amount threshold, the AXI bus-based bandwidth control device does not need to perform a pull-down process on the Ready signal of the read address channel of the AXI bus of the time window, that is, the state is maintained.
In step 206, when the comparison result is that the write data amount is greater than or equal to the write data amount threshold, the Ready signal of the write address channel of the AXI bus is pulled down to control the bandwidth of the AXI bus.
In this embodiment of the present application, when the write data amount of the time window is greater than or equal to the write data amount threshold, the AXI bus-based bandwidth control device may perform a pull-down process on the Ready signal of the write address channel of the AXI bus of the time window, and back-pressure the data transmission of the AXI bus, that is, block the transmission of the write data, so as to implement control of the bandwidth of the AXI bus.
In this embodiment of the present application, during each time window, each time a communication transmission is performed, the bandwidth control device based on the AXI bus compares the write data amount with the corresponding write data amount threshold once, and when the write data amount is greater than or equal to the write data amount threshold, the Ready signal is pulled down until the next time window, that is, until the next time window, no handshake is successful, and no further accumulation operation of the write data amount is performed.
Step 207, when the comparison result is that the write data amount is smaller than the write data amount threshold, the Ready signal of the write address channel of the AXI bus is kept in the original state.
In the embodiment of the present application, in the case where the write data amount of the time window is smaller than the write data amount threshold, the AXI bus-based bandwidth control device does not need to perform a pull-down process on the Ready signal of the write address channel of the AXI bus of the time window, that is, the Ready signal is kept in an original state.
In summary, a preconfigured time window is obtained; determining the read data quantity of the time window and the write data quantity of the time window; comparing the read data quantity and the write data quantity with corresponding read data quantity threshold values and write data quantity threshold values respectively to obtain a comparison result; when the comparison result is that the read data quantity is larger than or equal to the read data quantity threshold value, the Ready signal of the read address channel of the AXI bus is pulled down to control the bandwidth of the AXI bus; under the condition that the comparison result is that the read data quantity is smaller than the read data quantity threshold value, the Ready signal of the read address channel of the AXI bus is kept in an original state; when the comparison result is that the write data quantity is larger than or equal to the write data quantity threshold value, the Ready signal of the write address channel of the AXI bus is pulled down to control the bandwidth of the AXI bus; and under the condition that the comparison result is that the write data quantity is smaller than the write data quantity threshold value, the Ready signal of the write address channel of the AXI bus is kept in an original state. Therefore, the read data quantity and the read data quantity threshold value in the time window are compared, the write data quantity and the write data quantity threshold value are compared, and the Ready signal is adjusted according to the comparison result, so that the bandwidth of the AXI bus is controlled, the bandwidth can be controlled in real time, the problem of competing the bandwidth of the AXI bus is reduced, and the control precision of the bandwidth is improved.
For example, fig. 3 is a schematic diagram of an AXI bus-based bandwidth control method, in fig. 3, bandwidth control modules are added at AXI bus outlets of each subsystem, the number of bandwidth control modules may be multiple, the bandwidth control modules may include a time calculation unit, a data statistics unit and a data limiting unit, the AXI bus-based bandwidth control device may implement bandwidth control of each subsystem accessing a storage device through the bandwidth control modules, and a CPU (software) is configured to configure information, where the information may include a time window t, a read data amount threshold, a write data amount threshold, and an enable signal of the bandwidth control module.
The AXI bus-based bandwidth control device can generate a mark signal at the end of each time window through the time counting unit, and the mark signal is used for marking each time window; when each communication (handshake of the read address channel is successful), the bandwidth control device based on the AXI bus can obtain the read data quantity transmitted by communication through the data statistics unit, and the read data quantity transmitted by each communication is accumulated to obtain the read data quantity in a time window; when each communication (handshake of the write address channel is successful), the bandwidth control device based on the AXI bus can obtain the write data volume transmitted by communication through the data statistics unit, and the write data volume transmitted by each communication is accumulated to obtain the write data volume in a time window; the bandwidth control device based on the AXI bus can compare the read data quantity with the read data quantity threshold value through the data limiting unit, and pull down the Ready signal of the read address channel of the AXI bus when the read data quantity is larger than or equal to the read data quantity threshold value so as to control the bandwidth of the AXI bus until the next time window; the bandwidth control device based on the AXI bus can compare the write data quantity with a write data quantity threshold through the data limiting unit, and pull down the Ready signal of the write address channel of the AXI bus when the write data quantity is larger than or equal to the write data quantity threshold so as to control the bandwidth of the AXI bus until the next time window.
Fig. 4 is a schematic structural diagram of an AXI bus-based bandwidth control device according to a third embodiment of the present application.
As shown in fig. 4, the AXI bus-based bandwidth control apparatus 400 includes: the first acquisition module 410, the first determination module 420, the comparison module 430, the control module 440.
Wherein, the first obtaining module 410 is configured to obtain a pre-configured time window; a first determining module 420, configured to determine a read data amount of the time window and a write data amount of the time window; a comparison module 430, configured to compare the read data amount and the write data amount with a corresponding read data amount threshold and write data amount threshold, respectively, to obtain a comparison result; and the control module 440 is configured to adjust the Ready signal according to the comparison result, so as to control the bandwidth of the AXI bus.
As a possible implementation manner of the embodiment of the present application, the apparatus further includes: a second determination module and a third determination module; the second determining module is configured to determine a ratio of the read data amount threshold to the time window as a read bus bandwidth threshold; the third determining module is configured to determine a ratio of the write data amount threshold to the time window as a write bus bandwidth threshold.
As one possible implementation manner of the embodiment of the present application, the first determining module 420 is specifically configured to determine the read data amount of the ith communication transmission; determining the read data volume transmitted by the previous i-time communication according to the read data volume transmitted by the previous i-1 time communication and the read data volume transmitted by the ith time communication; wherein i is an integer greater than 1; and determining the read data quantity of the previous i communication transmissions as the read data quantity of the time window.
As a possible implementation manner of the embodiment of the present application, the first determining module 420 is specifically configured to obtain a data length and a data bit width of the read data of the ith communication transmission; and multiplying the data length of the read data and the data bit width power of 2 to obtain a multiplication result, and determining the multiplication result as the read data quantity of the ith communication transmission.
As one possible implementation manner of the embodiment of the present application, the first determining module 420 is specifically configured to determine an amount of write data of the ith communication transmission; determining the data writing quantity transmitted by the previous i-time communication according to the data writing quantity transmitted by the previous i-1-time communication and the data writing quantity transmitted by the ith communication; wherein i is an integer greater than 1; and determining the write data quantity transmitted by the previous i times of communication as the write data quantity of the time window.
As a possible implementation manner of the embodiment of the present application, the first determining module 420 is specifically configured to obtain a data length and a data bit width of the ith communication transmission write data; and multiplying the data length of the write data and the data bit width power of 2 to obtain a multiplication result, and determining the multiplication result as the write data quantity of the ith communication transmission.
As a possible implementation manner of the embodiment of the present application, the control module 440 is specifically configured to, when the comparison result is that the read data amount is greater than or equal to the read data amount threshold, pull down a Ready signal of a read address channel of the AXI bus to control a bandwidth of the AXI bus; and under the condition that the read data quantity is smaller than the read data quantity threshold value as a result of the comparison, the Ready signal of the read address channel of the AXI bus is kept in an original state.
As a possible implementation manner of the embodiment of the present application, the control module 440 is specifically configured to, when the comparison result is that the write data amount is greater than or equal to the write data amount threshold, pull down a Ready signal of a write address channel of the AXI bus to control a bandwidth of the AXI bus; and under the condition that the comparison result is that the write data quantity is smaller than the write data quantity threshold value, the Ready signal of the write address channel of the AXI bus is kept in an original state.
According to the AXI bus-based bandwidth control device, a preconfigured time window is obtained; determining the read data quantity of the time window and the write data quantity of the time window; comparing the read data quantity and the write data quantity with corresponding read data quantity threshold values and write data quantity threshold values respectively to obtain a comparison result; and according to the comparison result, adjusting the Ready signal to control the bandwidth of the AXI bus. Therefore, the read data quantity and the read data quantity threshold value in the time window are compared, the write data quantity and the write data quantity threshold value are compared, and the Ready signal is adjusted according to the comparison result, so that the bandwidth of the AXI bus is controlled, the bandwidth can be controlled in real time, the problem of competing the bandwidth of the AXI bus is reduced, and the control precision of the bandwidth is improved.
In order to achieve the foregoing embodiments, the present application further proposes a bandwidth control module, which is characterized by including: the device comprises a time counting unit, a data counting unit and a data limiting unit; the time counting unit is respectively connected with the data statistics unit and the data limiting unit, and generates a marking signal at the tail end of each time window for marking each time window; the data statistics unit is respectively connected with the time counting unit and the data limiting unit and is used for counting the read data quantity and the write data quantity of the time window; the data limiting unit is used for comparing the read data quantity and the write data quantity with corresponding read data quantity threshold values and write data quantity threshold values respectively to obtain comparison results, and adjusting the Ready signal according to the comparison results to control the bandwidth of the AXI bus.
In order to implement the above embodiment, the present application further proposes a chip, which is characterized by comprising: and the bandwidth control module is used for executing the AXI bus-based bandwidth control method.
To implement the above embodiment, the present application further proposes an electronic device, as shown in fig. 5, and fig. 5 is a block diagram of an electronic device for an AXI bus-based bandwidth control method according to an exemplary embodiment.
As shown in fig. 5, the electronic device 1100 includes:
a memory 1110 and a processor 1120, a bus 1130 connecting the different components (including the memory 1110 and the processor 1120), the memory 1110 storing a computer program that when executed by the processor 1120 implements the AXI bus-based bandwidth control method described in the embodiments of the present application.
Bus 1130 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processor, or a local bus using any of a variety of bus architectures. By way of example, and not limitation, such architectures include Industry Standard Architecture (ISA) bus, micro channel architecture (MAC) bus, enhanced ISA bus, video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.
The electronic device 1100 typically includes a variety of electronic device readable media. Such media can be any available media that can be accessed by the electronic device 1100 and includes both volatile and nonvolatile media, removable and non-removable media.
Memory 1110 may also include computer system readable media in the form of volatile memory, such as Random Access Memory (RAM) 1140 and/or cache memory 1150. The electronic device 1100 may further include other removable/non-removable, volatile/nonvolatile computer system storage media. By way of example only, storage system 1160 may be used to read and write non-removable, non-volatile magnetic media (not shown in FIG. 5, commonly referred to as a "hard disk drive"). Although not shown in fig. 5, a magnetic disk drive for reading from and writing to a removable non-volatile magnetic disk (e.g., a "floppy disk"), and an optical disk drive for reading from or writing to a removable non-volatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In such cases, each drive may be coupled to bus 1130 through one or more data medium interfaces. Memory 1110 may include at least one program product having a set (e.g., at least one) of program modules configured to carry out the functions of the embodiments of the present application.
A program/utility 1180 having a set (at least one) of program modules 1170 may be stored in, for example, memory 1110, such program modules 1170 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each or some combination of which may include an implementation of a network environment. Program modules 1170 generally perform the functions and/or methods in the embodiments described herein.
The electronic device 1100 may also communicate with one or more external devices 1190 (e.g., keyboard, pointing device, display 1091, etc.), one or more devices that enable a user to interact with the electronic device 1100, and/or any device (e.g., network card, modem, etc.) that enables the electronic device 1100 to communicate with one or more other computing devices. Such communication may occur through an input/output (I/O) interface 1192. Also, the electronic device 1100 may communicate with one or more networks such as a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network, such as the Internet, through a network adapter 1193. As shown in fig. 5, the network adapter 1193 communicates with other modules of the electronic device 1100 via the bus 1130. It should be appreciated that although not shown in fig. 5, other hardware and/or software modules may be used in connection with electronic device 1100, including, but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data backup storage systems, and the like.
The processor 1120 executes various functional applications and data processing by running programs stored in the memory 1110.
It should be noted that, the implementation process and the technical principle of the electronic device in this embodiment refer to the foregoing explanation of the monitoring processing method in this embodiment, and are not repeated herein.
To implement the above embodiments, the present application also proposes a non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute the AXI bus-based bandwidth control method described in the embodiments of fig. 1 to 3.
To implement the above embodiments, the present application also provides a computer program product which, when executed by an instruction processor in the computer program product, performs the AXI bus-based bandwidth control method described in the embodiments of fig. 1 to 3.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" is at least two, such as two, three, etc., unless explicitly defined otherwise.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and additional implementations are included within the scope of the preferred embodiment of the present application in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the embodiments of the present application.
Logic and/or steps represented in the flowcharts or otherwise described herein, e.g., a ordered listing of executable instructions for implementing logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer readable medium may even be paper or other suitable medium on which the program is printed, as the program may be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.
It is to be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. As with the other embodiments, if implemented in hardware, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.
Those of ordinary skill in the art will appreciate that all or a portion of the steps carried out in the method of the above-described embodiments may be implemented by a program to instruct related hardware, where the program may be stored in a computer readable storage medium, and where the program, when executed, includes one or a combination of the steps of the method embodiments.
In addition, each functional unit in each embodiment of the present application may be integrated in one processing module, or each unit may exist alone physically, or two or more units may be integrated in one module. The integrated modules may be implemented in hardware or in software functional modules. The integrated modules may also be stored in a computer readable storage medium if implemented in the form of software functional modules and sold or used as a stand-alone product.
The above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, or the like. Although embodiments of the present application have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the application, and that variations, modifications, alternatives, and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the application.

Claims (19)

1. A method for controlling bandwidth based on an AXI bus, comprising:
acquiring a pre-configured time window;
determining the read data volume of the time window and the write data volume of the time window;
comparing the read data quantity and the write data quantity with corresponding read data quantity threshold values and write data quantity threshold values respectively to obtain a comparison result;
and according to the comparison result, adjusting the Ready signal to control the bandwidth of the AXI bus.
2. The method according to claim 1, wherein the method further comprises:
determining the ratio of the read data volume threshold to the time window as a read bus bandwidth threshold;
and determining the ratio of the write data volume threshold value to the time window as a write bus bandwidth threshold value.
3. The method of claim 1, wherein said determining the amount of read data for the time window comprises:
determining the read data amount of the ith communication transmission;
determining the read data volume transmitted by the previous i-time communication according to the read data volume transmitted by the previous i-1 time communication and the read data volume transmitted by the ith time communication; wherein i is an integer greater than 1;
and determining the read data quantity of the previous i communication transmissions as the read data quantity of the time window.
4. A method according to claim 3, wherein said determining the amount of read data for the ith communication transmission comprises:
acquiring the data length and the data bit width of the read data of the ith communication transmission;
and multiplying the data length of the read data and the data bit width power of 2 to obtain a multiplication result, and determining the multiplication result as the read data quantity of the ith communication transmission.
5. The method of claim 1, wherein the determining the amount of write data for the time window comprises:
determining the data writing quantity of the ith communication transmission;
determining the data writing quantity transmitted by the previous i-time communication according to the data writing quantity transmitted by the previous i-1-time communication and the data writing quantity transmitted by the ith communication; wherein i is an integer greater than 1;
And determining the write data quantity transmitted by the previous i times of communication as the write data quantity of the time window.
6. The method of claim 5, wherein determining the amount of write data for the ith communication transmission comprises:
acquiring the data length and the data bit width of the ith communication transmission write data;
and multiplying the data length of the write data and the data bit width power of 2 to obtain a multiplication result, and determining the multiplication result as the write data quantity of the ith communication transmission.
7. The method of claim 1, wherein said adjusting the Ready signal to control the bandwidth of the AXI bus based on the comparison result comprises:
when the comparison result is that the read data quantity is larger than or equal to the read data quantity threshold value, carrying out low-pulling processing on a Ready signal of a read address channel of the AXI bus so as to control the bandwidth of the AXI bus;
and under the condition that the read data quantity is smaller than the read data quantity threshold value as a result of the comparison, the Ready signal of the read address channel of the AXI bus is kept in an original state.
8. The method of claim 1, wherein said adjusting the Ready signal to control the bandwidth of the AXI bus based on the comparison result comprises:
When the comparison result is that the write data quantity is larger than or equal to the write data quantity threshold value, carrying out low-pulling processing on a Ready signal of a write address channel of the AXI bus so as to control the bandwidth of the AXI bus;
and under the condition that the comparison result is that the write data quantity is smaller than the write data quantity threshold value, the Ready signal of the write address channel of the AXI bus is kept in an original state.
9. A bandwidth control apparatus based on an AXI bus, comprising:
the first acquisition module is used for acquiring a pre-configured time window;
the first determining module is used for determining the read data quantity of the time window and the write data quantity of the time window;
a comparison module for comparing the read data amount and the write data amount with corresponding read data amount threshold and write data amount threshold, respectively, obtaining a comparison result;
and the control module is used for adjusting the Ready signal according to the comparison result so as to control the bandwidth of the AXI bus.
10. The apparatus of claim 9, wherein the apparatus further comprises: a second determination module and a third determination module;
the second determining module is configured to determine a ratio of the read data amount threshold to the time window as a read bus bandwidth threshold;
The third determining module is configured to determine a ratio of the write data amount threshold to the time window as a write bus bandwidth threshold.
11. The apparatus of claim 9, wherein the first determining means is specifically configured to,
determining the read data amount of the ith communication transmission;
determining the read data volume transmitted by the previous i-time communication according to the read data volume transmitted by the previous i-1 time communication and the read data volume transmitted by the ith time communication; wherein i is an integer greater than 1;
and determining the read data quantity of the previous i communication transmissions as the read data quantity of the time window.
12. The apparatus of claim 11, wherein the first determining means is specifically configured to,
acquiring the data length and the data bit width of the read data of the ith communication transmission;
and multiplying the data length of the read data and the data bit width power of 2 to obtain a multiplication result, and determining the multiplication result as the read data quantity of the ith communication transmission.
13. The apparatus of claim 9, wherein the first determining means is specifically configured to,
determining the data writing quantity of the ith communication transmission;
determining the data writing quantity transmitted by the previous i-time communication according to the data writing quantity transmitted by the previous i-1-time communication and the data writing quantity transmitted by the ith communication; wherein i is an integer greater than 1;
And determining the write data quantity transmitted by the previous i times of communication as the write data quantity of the time window.
14. The apparatus of claim 13, wherein the first determining means is specifically configured to,
acquiring the data length and the data bit width of the ith communication transmission write data;
and multiplying the data length of the write data and the data bit width power of 2 to obtain a multiplication result, and determining the multiplication result as the write data quantity of the ith communication transmission.
15. The device according to claim 9, wherein the control module is configured to,
when the comparison result is that the read data quantity is larger than or equal to the read data quantity threshold value, carrying out low-pulling processing on a Ready signal of a read address channel of the AXI bus so as to control the bandwidth of the AXI bus;
and under the condition that the read data quantity is smaller than the read data quantity threshold value as a result of the comparison, the Ready signal of the read address channel of the AXI bus is kept in an original state.
16. The device according to claim 9, wherein the control module is configured to,
when the comparison result is that the write data quantity is larger than or equal to the write data quantity threshold value, carrying out low-pulling processing on a Ready signal of a write address channel of the AXI bus so as to control the bandwidth of the AXI bus;
And under the condition that the comparison result is that the write data quantity is smaller than the write data quantity threshold value, the Ready signal of the write address channel of the AXI bus is kept in an original state.
17. A bandwidth control module, comprising: the device comprises a time counting unit, a data counting unit and a data limiting unit;
the time counting unit is respectively connected with the data statistics unit and the data limiting unit, and generates a marking signal at the tail end of each time window for marking each time window;
the data statistics unit is respectively connected with the time counting unit and the data limiting unit and is used for counting the read data quantity and the write data quantity of the time window;
the data limiting unit is used for comparing the read data quantity and the write data quantity with corresponding read data quantity threshold values and write data quantity threshold values respectively to obtain comparison results, and adjusting the Ready signal according to the comparison results to control the bandwidth of the AXI bus.
18. A chip, comprising: a bandwidth control module for performing the method of any of claims 1-8.
19. An electronic device, comprising:
At least one processor; and
a memory communicatively coupled to the at least one processor; wherein, the liquid crystal display device comprises a liquid crystal display device,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-8.
CN202310095428.8A 2023-02-03 2023-02-03 Bandwidth control method and device based on AXI bus and electronic equipment Pending CN116069710A (en)

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