CN116050528A - Method and device for constructing amplitude amplification circuit, medium and electronic device - Google Patents
Method and device for constructing amplitude amplification circuit, medium and electronic device Download PDFInfo
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Abstract
The invention discloses a construction method, a device, a medium and an electronic device of an amplitude amplification circuit, wherein the method comprises the steps of obtaining an evolution operator corresponding to a first quantum circuit, wherein the first quantum circuit is used for obtaining a target quantum state, and the target quantum state is represented by a linear combination of two orthogonal ground states corresponding to target data and noise data; and determining an amplitude amplification operator based on the evolution operator, and constructing a second quantum circuit based on the amplitude amplification operator, wherein when auxiliary bits in the second quantum circuit are measured, the probability of obtaining a ground state corresponding to the target data is larger than the probability of obtaining a ground state corresponding to the noise data, so that the construction of the amplitude amplification circuit in a quantum search algorithm can be realized, and further the search efficiency of the target data can be improved through the quantum search algorithm.
Description
Technical Field
The invention belongs to the technical field of quantum computing, and particularly relates to a method and a device for constructing an amplitude amplification circuit, a medium and an electronic device.
Background
Search fields have been devoted to providing users with more accurate search results that better conform to their search intent. However, conventional computers are actually inefficient in searching unstructured data, and typically the complexity of the algorithm is o (N), which is the data size. While the amount of operation in a quantum computerThe complexity of the sub-search algorithm is
The quantum search algorithm is an iterative algorithm, and the amplitude of the target state is finely adjusted upwards through quantum interference, so that the probability of obtaining the target state through measurement can be highlighted during measurement. The corresponding quantum circuit mainly comprises two parts, namely a quantum state preparation circuit and an iteration circuit, wherein the iteration circuit is used for iterating the amplitude amplification circuit for a plurality of times to increase the amplitude of the target state, so that the probability of measuring the target state is increased, and the searching efficiency of searching the target data corresponding to the target state is improved. Therefore, how to implement the construction of the amplitude amplification line is a key to improve the search efficiency of the target data.
Disclosure of Invention
The invention aims to provide a construction method, a device, a medium and an electronic device of an amplitude amplification circuit, which aim to realize the construction of the amplitude amplification circuit in a quantum search algorithm and further realize the aim of improving the search efficiency of target data through the quantum search algorithm.
One embodiment of the present invention provides a method for constructing an amplitude amplifying circuit, the method comprising:
acquiring an evolution operator corresponding to a first quantum circuit, wherein the first quantum circuit is used for obtaining a target quantum state, and the target quantum state is represented by a linear combination of two orthogonal ground states corresponding to target data and noise data;
and determining an amplitude amplification operator based on the evolution operator, and constructing a second quantum circuit based on the amplitude amplification operator, wherein when auxiliary bits in the second quantum circuit are measured, the probability of obtaining a ground state corresponding to the target data is larger than the probability of obtaining a ground state corresponding to the noise data.
Optionally, the first quantum circuit and the second quantum circuit each include n data bits and 1 auxiliary bit, and the linear expression corresponding to the first quantum circuit is that
A is the evolution operator, ++>
The base states corresponding to the noise data and the target data are respectively, and cos theta and sin theta are respectively measured as |0 by the auxiliary bit>、|1>Amplitude at that time.
Optionally, the amplitude amplification operator
Wherein: s is S 0 ＝I-2|0> n+1 <0| n+1 ，
Optionally, the constructing a second quantum circuit based on the amplitude amplification operator includes:
construction based on Z-gate
Corresponding first sub-line, build +.>
Corresponding second sub-line, based on the first virtual control-Z gate to construct S 0 The corresponding third sub-line and the corresponding fourth sub-line of A are constructed, and the virtual control bit of the first virtual control-Z gate is n data bits;
and cascading the first sub-circuit, the second sub-circuit, the third sub-circuit and the fourth sub-circuit in sequence to obtain a second quantum circuit.
Optionally, the first quantum circuit and the second quantum circuit each include n data bits and m auxiliary bits, and the linear expression corresponding to the first quantum circuit is that
A is the evolution operator, ++>
The base states corresponding to the noise data and the target data are respectively, and cos theta and sin theta are respectively measured as +.>
|1> m Amplitude at time, said->
And |1> m Orthogonal, m is an integer greater than 1.
Optionally, the amplitude amplification operator
Wherein:
optionally, the constructing a second quantum circuit based on the amplitude amplification operator includes:
construction based on real control-Z gate and-I gate
Corresponding fifth sub-line, build +.>
Corresponding sixth sub-line constructs S based on the second virtual control-Z gate 0 A seventh sub-line corresponding to the first virtual control-Z gate, and an eighth sub-line corresponding to the first sub-line A, wherein the virtual control bits of the second virtual control-Z gate are n data bits and m-1 auxiliary bits;
and cascading the fifth sub-line, the sixth sub-line, the seventh sub-line and the eighth sub-line in sequence to obtain a second quantum line.
Yet another embodiment of the present invention provides an apparatus for constructing an amplitude amplifying line, the apparatus including:
the information acquisition unit is used for acquiring an evolution operator corresponding to a first quantum circuit, wherein the first quantum circuit is used for obtaining a target quantum state, and the target quantum state is represented by a linear combination of two orthogonal ground states corresponding to target data and noise data;
and the circuit construction unit is used for determining an amplitude amplification operator based on the evolution operator and constructing a second quantum circuit based on the amplitude amplification operator, wherein when auxiliary bits in the second quantum circuit are measured, the probability of obtaining the ground state corresponding to the target data is larger than the probability of obtaining the ground state corresponding to the noise data.
Optionally, the first quantum circuit and the second quantum circuit each include n data bits and 1 auxiliary bit, and the linear expression corresponding to the first quantum circuit is that
A is the evolution operator, ++>
The base states corresponding to the noise data and the target data are respectively, and cos theta and sin theta are respectively measured as |0 by the auxiliary bit>、|1>Amplitude at that time.
Optionally, the amplitude amplification operator
Wherein: s is S 0 ＝I-2|0> n+1 ＜0| n+1 ，
Optionally, the second quantum circuit is constructed based on the amplitude amplification operator, and the circuit construction unit is specifically configured to:
construction based on Z-gate
Corresponding first sub-line, build +.>
Corresponding second subLine, S is constructed based on first virtual control-Z gate 0 The corresponding third sub-line and the corresponding fourth sub-line of A are constructed, and the virtual control bit of the first virtual control-Z gate is n data bits;
and cascading the first sub-circuit, the second sub-circuit, the third sub-circuit and the fourth sub-circuit in sequence to obtain a second quantum circuit.
Optionally, the first quantum circuit and the second quantum circuit each include n data bits and m auxiliary bits, and the linear expression corresponding to the first quantum circuit is that
A is the evolution operator, ++>
The base states corresponding to the noise data and the target data are respectively, and cos theta and sin theta are respectively measured as +.>
|1> m Amplitude at time, said->
And |1> m Orthogonal, m is an integer greater than 1.
Optionally, the amplitude amplification operator
Wherein:
optionally, the second quantum circuit is constructed based on the amplitude amplification operator, and the circuit construction unit is specifically configured to:
construction based on real control-Z gate and-I gate
Corresponding firstFive sub-lines, build->
Corresponding sixth sub-line constructs S based on the second virtual control-Z gate 0 A seventh sub-line corresponding to the first virtual control-Z gate, and an eighth sub-line corresponding to the first sub-line A, wherein the virtual control bits of the second virtual control-Z gate are n data bits and m-1 auxiliary bits;
and cascading the fifth sub-line, the sixth sub-line, the seventh sub-line and the eighth sub-line in sequence to obtain a second quantum line.
A further embodiment of the invention provides a storage medium having a computer program stored therein, wherein the computer program is arranged to perform the method of any of the preceding claims when run.
Yet another embodiment of the invention provides an electronic device comprising a memory having a computer program stored therein and a processor configured to run the computer program to perform the method described in any of the above.
Compared with the prior art, the method, the device, the medium and the electronic device for constructing the amplitude amplification circuit are characterized in that the evolution operator corresponding to the first quantum circuit is obtained, the first quantum circuit is used for obtaining a target quantum state, and the target quantum state is represented by the linear combination of two orthogonal ground states corresponding to target data and noise data; and determining an amplitude amplification operator based on the evolution operator, and constructing a second quantum circuit based on the amplitude amplification operator, wherein when auxiliary bits in the second quantum circuit are measured, the probability of obtaining a ground state corresponding to the target data is larger than the probability of obtaining a ground state corresponding to the noise data, so that the construction of the amplitude amplification circuit in a quantum search algorithm can be realized, and further the search efficiency of the target data can be improved through the quantum search algorithm.
Drawings
Fig. 1 is a hardware block diagram of a computer terminal according to a method for constructing an amplitude amplifying circuit according to an embodiment of the present invention;
fig. 2 is a flow chart of a method for constructing an amplitude amplifying circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a second quantum circuit according to an embodiment of the present invention.
Fig. 4 is a schematic structural diagram of another second quantum circuit according to an embodiment of the present invention.
Fig. 5 is a schematic structural diagram of a device for constructing an amplitude amplifying circuit according to an embodiment of the present invention.
Detailed Description
The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention.
The embodiment of the invention firstly provides a construction method of an amplitude amplification circuit, which can be applied to electronic equipment such as a computer terminal, in particular to a common computer, a quantum computer and the like.
The following describes the operation of the computer terminal in detail by taking it as an example. Fig. 1 is a hardware block diagram of a computer terminal according to a method for constructing an amplitude amplifying circuit according to an embodiment of the present invention. As shown in fig. 1, the computer terminal may include one or more (only one is shown in fig. 1) processors 102 (the processor 102 may include, but is not limited to, a microprocessor MCU or a processing device such as a programmable logic device FPGA) and a memory 104 for storing a construction method of an amplitude amplification circuit, and optionally, a transmission device 106 for a communication function and an input-output device 108. It will be appreciated by those skilled in the art that the configuration shown in fig. 1 is merely illustrative and is not intended to limit the configuration of the computer terminal described above. For example, the computer terminal may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.
The memory 104 may be used to store software programs and modules of application software, such as program instructions/modules corresponding to the method for constructing an amplitude amplification circuit in the embodiment of the present application, and the processor 102 executes the software programs and modules stored in the memory 104, thereby performing various functional applications and data processing, that is, implementing the method described above. Memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory remotely located relative to the processor 102, which may be connected to the computer terminal via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmission means 106 is arranged to receive or transmit data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of a computer terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, NIC) that can connect to other network devices through a base station to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module for communicating with the internet wirelessly.
It should be noted that a real quantum computer is a hybrid structure, which includes two major parts: part of the computers are classical computers and are responsible for performing classical computation and control; the other part is quantum equipment, which is responsible for running quantum programs so as to realize quantum computation. The quantum program is a series of instruction sequences written by a quantum language such as the qlunes language and capable of running on a quantum computer, so that the support of quantum logic gate operation is realized, and finally, quantum computing is realized. Specifically, the quantum program is a series of instruction sequences for operating the quantum logic gate according to a certain time sequence.
In practical applications, quantum computing simulations are often required to verify quantum algorithms, quantum applications, etc., due to the development of quantum device hardware. Quantum computing simulation is a process of realizing simulated operation of a quantum program corresponding to a specific problem by means of a virtual architecture (namely a quantum virtual machine) built by resources of a common computer. In general, it is necessary to construct a quantum program corresponding to a specific problem. The quantum program, namely the program for representing the quantum bit and the evolution thereof written in the classical language, wherein the quantum bit, the quantum logic gate and the like related to quantum computation are all represented by corresponding classical codes.
Quantum circuits, which are one embodiment of quantum programs and weigh sub-logic circuits as well, are the most commonly used general quantum computing models, representing circuits that operate on qubits under an abstract concept, and their composition includes qubits, circuits (timelines), and various quantum logic gates, and finally the result often needs to be read out through quantum measurement operations.
Unlike conventional circuits, which are connected by metal lines to carry voltage or current signals, in a quantum circuit, the circuit can be seen as being connected by time, i.e., the state of the qubit naturally evolves over time, as indicated by the hamiltonian operator, during which it is operated until a logic gate is encountered.
One quantum program is corresponding to one total quantum circuit, and the quantum program refers to the total quantum circuit, wherein the total number of quantum bits in the total quantum circuit is the same as the total number of quantum bits of the quantum program. It can be understood that: one quantum program may consist of a quantum circuit, a measurement operation for the quantum bits in the quantum circuit, a register to hold the measurement results, and a control flow node (jump instruction), and one quantum circuit may contain several tens of hundreds or even thousands of quantum logic gate operations. The execution process of the quantum program is a process of executing all quantum logic gates according to a certain time sequence. Note that the timing is the time sequence in which a single quantum logic gate is executed.
It should be noted that, in a common computing device based on a silicon chip, the unit of the processing chip is a CMOS tube, and such a computing unit is not limited by time and coherence, i.e., such a computing unit is not limited by the time of use, and is available at any time. Furthermore, currently, the number of such calculation units in a silicon chip is sufficient, i.e. the number of calculation units in one chip is thousands of at present. The number of computational cells is sufficient and the CMOS transistor selectable computational logic is fixed, for example: and AND logic. When the CMOS tube is used for operation, a large number of CMOS tubes are combined with limited logic functions, so that the operation effect is realized.
Unlike such logic units in conventional computing devices, in current quantum computers the basic computing unit is a qubit, the input of which is limited by coherence and also by coherence time, i.e. the qubit is limited in terms of time of use and is not readily available. Full use of qubits within the usable lifetime of the qubits is a critical challenge for quantum computing. Furthermore, the number of qubits in a quantum computer is one of the representative indicators of the performance of the quantum computer, each of the qubits realizes a calculation function by a logic function configured as needed, whereas the logic function in the field of quantum calculation is diversified in view of the limited number of qubits, for example: hadamard gates (Hadamard gates, H gates), brix-gates (X gates), brix-Y gates (Y gates), brix-Z gates (Z gates), RX gates, RY gates, RZ gates, CNOT gates, CR gates, issnap gates, toffoli gates, and the like. Quantum logic gates are typically represented using unitary matrices, which are not only in matrix form, but also an operation and transformation. The effect of a general quantum logic gate on a quantum state is calculated by multiplying the unitary matrix by a matrix corresponding to the right vector of the quantum state. During quantum computation, the operation effect is realized by combining limited quantum bits with various logic function combinations.
Based on these differences of the quantum computer, the design of the logic function on the quantum bits (including the design of whether the quantum bits are used or not and the design of the use efficiency of each quantum bit) is a key for improving the operation performance of the quantum computer, and special design is required. The above design for qubits is a technical problem that is not considered nor faced by common computing devices.
Referring to fig. 2, fig. 2 is a flow chart of a method for constructing an amplitude amplifying circuit according to an embodiment of the present invention. The method comprises the following steps:
step 201: acquiring an evolution operator corresponding to a first quantum circuit, wherein the first quantum circuit is used for obtaining a target quantum state, and the target quantum state is represented by a linear combination of two orthogonal ground states corresponding to target data and noise data;
any data set may be represented as data that is desired by the user and data that is not desired by the user. Thus in a quantum search algorithm, a data set may be encoded into quantum states, which is then divided by a first quantum wire into data that is needed by the user and data that is not needed by the user, i.e. target data and noise data. The probability of obtaining the target data by searching can be increased only by increasing the probability of obtaining the target state corresponding to the target data by measuring.
By way of example, example 1: if the data set includes 0 and 1, the target data is 0, the noise data is 1, and when no optimization is performed, the data set may need to be searched twice in the database through a classical search algorithm to obtain 0; if the probability of 0 measurement can be increased, the closer the probability of 0 measurement is to 1, the fewer the number of searches, the closer to 1.
Likewise, example 2: if the data set includes 0, 1, 2, and 3, the noise data is 1, 2, and 3. In this case, the classical search algorithm may divide 0, 1, 2, and 3 into equal parts, determine which part includes 0, and then determine which data in the part including 0 is 0. In the quantum search algorithm, 0 is represented by one ground state, and 1, 2, 3 are represented by another orthogonal ground state. The probability of obtaining 0 by the measurement is increased, so that the searching times are reduced.
Wherein the first quantum circuit and the second quantum circuit each comprise n data bits and 1 auxiliary bit, and the linear expression corresponding to the first quantum circuit is that
A is the evolution operator, ++>
The base states corresponding to the noise data and the target data are respectively, and cos theta and sin theta are respectively measured as |0 by the auxiliary bit>、|1>Amplitude at that time.
For example 1: only 1 data bit and 1 auxiliary bit are needed, and the data bit and the auxiliary bit can be respectively used0 of the data bits<And |1<Representing classical data 0 and 1, i.e
If 0 and 1 occur the same number of times in the dataset, i.e
Then the evolution operator a may be H 1 The H is 1 The corresponding H-gate only acts on the data bits.
For example 2: then 2 data bits and 1 auxiliary bit are required, and the |00 of the data bits can be used separately>、|01>、|10>、|11>Representing classical data 0, 1, 2, 3, then
If 0, 1, 2, 3 occur in the dataset the same number of times, i.e. +.>
sin θ=1/2, then the evolution operator a may be
H 1 The corresponding H gate acts on the first data bit, H 2 The corresponding H-gate acts on the first data bit.
Wherein the first quantum circuit and the second quantum circuit each comprise n data bits and m auxiliary bits, and the linear expression corresponding to the first quantum circuit is that
A is the evolution operator, ++>
The base states corresponding to the noise data and the target data are respectively, and cos theta and sin theta are respectively measured as +.>
|1> m Amplitude at time, said->
And |1> m Orthogonal, m is an integer greater than 1.
Wherein, the liquid crystal display device comprises a liquid crystal display device,
to divide by |1> m Other states than this. For the case where the auxiliary bits are plural, the structure of the first quantum wire is similar to that of the case where the auxiliary bits are 1, and reference can be made to the first quantum wire of the case where the auxiliary bits are 1.
Step 202: and determining an amplitude amplification operator based on the evolution operator, and constructing a second quantum circuit based on the amplitude amplification operator, wherein when auxiliary bits in the second quantum circuit are measured, the probability of obtaining a ground state corresponding to the target data is larger than the probability of obtaining a ground state corresponding to the noise data.
In one embodiment of the present invention, the amplitude amplification operator when the number of auxiliary bits is 1
Wherein: s is S 0 ＝I-2|0> n+1 <0| n+1 ，/>
Specifically, the constructing a second quantum wire based on the amplitude amplification operator includes:
construction based on Z-gate
Corresponding first sub-line, build +.>
Corresponding second sub-line based on first virtual control-Z gateConstruction S 0 The corresponding third sub-line and the corresponding fourth sub-line of A are constructed, and the virtual control bit of the first virtual control-Z gate is n data bits;
and cascading the first sub-circuit, the second sub-circuit, the third sub-circuit and the fourth sub-circuit in sequence to obtain a second quantum circuit.
Further, the Z-gate based construction
A corresponding first sub-line comprising: and applying the Z gate to the auxiliary bit to obtain a first sub-line. />
Further, the construction
A corresponding second sub-line comprising: said->
The corresponding quantum logic gate acts on n of said data bits and 1 of said auxiliary bits, resulting in a second sub-line.
Further, the construction S based on the first virtual control-Z gate 0 A corresponding third sub-line comprising: and applying a first virtual control-Z gate to the n data bits and 1 auxiliary bit to obtain a third sub-line, wherein the virtual control bit of the first virtual control-Z gate is the n data bits, and the controlled bit is the 1 auxiliary bit.
Further, the constructing a fourth sub-line corresponding to a includes: and acting the quantum logic gate corresponding to the A on n data bits and 1 auxiliary bit to obtain a fourth sub-line.
It should be noted that, since:
the calculation and verification can be obtained:
wherein S is 0 The matrix of (a) is represented as follows:
thus, the third sub-line may be built based on the first virtual control-Z gate.
Due to
And->
Unknown (I)>
The matrix of (2) cannot be given directly, even +.>
And->
It is also known that its construction is cumbersome. However, as can be seen from the above formula (1), there is +.>
Will only act on
By acting on the quantum state of->
The following equation can be obtained:
thus, the construction of the first quantum wire may be achieved by acting a-Z gate on the auxiliary bit.
Fig. 3 is a schematic structural diagram of a second quantum circuit according to an embodiment of the present invention, as shown in fig. 3.
In another embodiment of the present invention, when the number of auxiliary bits is m, the amplitude amplification operator
Wherein: />
Wherein, due to:
so that:
it can be seen that Q is virtually identical to that inside the amplitude amplification.
In this case, the qubit to be estimated in FIG. 3 is not the last bit, so the active position of the Quantum logic gate in FIG. 3 needs to be changed, only |1 needs to be considered> m Amplitude estimation conditions of (a).
Specifically, the constructing a second quantum wire based on the amplitude amplification operator includes:
construction based on real control-Z gate and-I gate
Corresponding fifth sub-line, build +.>
Corresponding sixth sub-line constructs S based on the second virtual control-Z gate 0 A seventh sub-line corresponding to the first virtual control-Z gate, and an eighth sub-line corresponding to the first sub-line A, wherein the virtual control bits of the second virtual control-Z gate are n data bits and m-1 auxiliary bits;
and cascading the fifth sub-line, the sixth sub-line, the seventh sub-line and the eighth sub-line in sequence to obtain a second quantum line.
Further, the real control-Z gate and-I gate based construction
A corresponding fifth sub-line comprising:
applying a real control-Z gate to m of the auxiliary bits and applying an-I gate to another of the auxiliary bits to obtain
And a corresponding fifth sub-line, wherein the real control bit of the real control-Z gate is m-1 auxiliary bits, and the controlled bit of the real control-Z gate is another auxiliary bit.
Further, the construction
A corresponding sixth sub-line comprising: will->
The corresponding quantum logic gate acts on n of said data bits and m of said auxiliary bits, resulting in a sixth sub-line.
Further, the construction S based on the second virtual control-Z gate 0 A corresponding seventh sub-line comprising:
and a second virtual control-Z gate is acted on the n data bits and the m auxiliary bits to obtain a seventh sub-line, wherein the virtual control bits of the second virtual control-Z gate are the n data bits and the m-1 auxiliary bits, and the controlled bits of the second virtual control-Z gate are the other auxiliary bits.
Further, the constructing an eighth sub-line corresponding to a includes: and acting the quantum logic gate corresponding to the A on n data bits and m auxiliary bits.
Wherein the-Z gate can be constructed based on the Z gate and the RX gate with a rotation angle of 2pi. The I gate is constructed based on the I gate, the matrix to which the I gate corresponds being the identity matrix.
Wherein, virtual control refers to that when the quantum state of the control bit is |0>, the corresponding quantum logic gate is executed. For example, the first virtually controlled-Z gate indicates that the-Z gate acting on the auxiliary bit is only implemented when all of the quantum states of the n data bits are |0 >. Likewise, real control refers to the execution of the corresponding quantum logic gate when the quantum state of the control bit is |0 >. For example, the above-mentioned real control-Z indicates that the-Z gate acting on another of the auxiliary bits is performed when the quantum state of m-1 auxiliary bits is |1 >.
Fig. 4 is a schematic structural diagram of another second quantum circuit according to an embodiment of the present invention, as shown in fig. 4.
Compared with the prior art, the method for constructing the amplitude amplification circuit is characterized in that an evolution operator corresponding to a first quantum circuit is obtained, the first quantum circuit is used for obtaining a target quantum state, and the target quantum state is represented by a linear combination of two orthogonal ground states corresponding to target data and noise data; and determining an amplitude amplification operator based on the evolution operator, and constructing a second quantum circuit based on the amplitude amplification operator, wherein when auxiliary bits in the second quantum circuit are measured, the probability of obtaining a ground state corresponding to the target data is larger than the probability of obtaining a ground state corresponding to the noise data, so that the construction of the amplitude amplification circuit in a quantum search algorithm can be realized, and further the search efficiency of the target data can be improved through the quantum search algorithm.
The embodiment of the invention also provides a target data searching method, which comprises the following steps:
receiving a target data searching task, wherein the target data searching task is used for searching target data and carries a first quantum circuit;
acquiring an evolution operator corresponding to a first quantum circuit, wherein the first quantum circuit is used for obtaining a target quantum state, and the target quantum state is represented by a linear combination of two orthogonal ground states corresponding to target data and noise data;
determining an amplitude amplification operator based on the evolution operator, and constructing a second quantum circuit based on the amplitude amplification operator, wherein when auxiliary bits in the second quantum circuit are measured, the probability of obtaining a ground state corresponding to the target data is larger than the probability of obtaining a ground state corresponding to the noise data;
creating a quantum search circuit based on the second quantum circuit, and sending the quantum search circuit to a quantum computing module;
and receiving a measurement result returned by the quantum computing module, and determining a search result based on the measurement result.
In practice, rough measurement is generally performed first, statistics are made
Then the number of iterations is adjusted according to p.
Specifically, the number of iterations of the second quantum wire in the quantum search wire is
Wherein p is a small number of statistical measures
CI represents a downward value.
The quantum computing module can generate a logic signal according to the quantum search circuit, send the logic signal to the quantum bit and excite the quantum bit from an initial state to a target state; the quantum computing module can also generate and send a measuring signal, and the measuring signal is used for measuring the quantum bit after excitation to the target state, so as to obtain a measuring result.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a construction apparatus of an amplitude amplifying circuit according to an embodiment of the present invention. The device comprises:
an information obtaining unit 501, configured to obtain an evolution operator corresponding to a first quantum circuit, where the first quantum circuit is configured to obtain a target quantum state, and the target quantum state is represented by a linear combination of two orthogonal ground states corresponding to target data and noise data;
the circuit construction unit 502 is configured to determine an amplitude amplification operator based on the evolution operator, and construct a second quantum circuit based on the amplitude amplification operator, where when the auxiliary bit in the second quantum circuit is measured, a probability of obtaining a ground state corresponding to the target data is greater than a probability of obtaining a ground state corresponding to the noise data.
Optionally, the first quantum circuit and the second quantum circuit each include n data bits and 1 auxiliary bit, and the linear expression corresponding to the first quantum circuit is that
A is the evolution operator, ++>
The base states corresponding to the noise data and the target data are respectively, and cos theta and sin theta are respectively measured as |0 by the auxiliary bit>、|1>Amplitude at that time.
Optionally, the amplitude amplification operator
Wherein: s is S 0 ＝I-2|0> n+1 <0| n+1 ，
Optionally, the constructing a second quantum circuit based on the amplitude amplification operator, where the circuit constructing unit 502 is specifically configured to:
construction based on Z-gate
Corresponding first sub-line, build +.>
Corresponding second sub-line, based on the first virtual control-Z gate to construct S 0 The corresponding third sub-line and the corresponding fourth sub-line of A are constructed, and the virtual control bit of the first virtual control-Z gate is n data bits;
and cascading the first sub-circuit, the second sub-circuit, the third sub-circuit and the fourth sub-circuit in sequence to obtain a second quantum circuit.
Optionally, the first quantum circuit and the second quantum circuit each include n data bits and m auxiliary bits, and the linear expression corresponding to the first quantum circuit is that
A is the evolution operator, ++>
The base states corresponding to the noise data and the target data are respectively, and cos theta and sin theta are respectively measured as +.>
|1> m Amplitude at time, said->
And |1> m Orthogonal, m is an integer greater than 1.
Optionally, the first quantum circuit and the second quantum circuit each include n data bits and m auxiliary bits, and the linear expression corresponding to the first quantum circuit is that
A is the evolution operator, ++>
The base states corresponding to the noise data and the target data are respectively, and cos theta and sin theta are respectively measured as +.>
|1> m Amplitude at time, said->
And |1> m Orthogonal, m is an integer greater than 1.
Optionally, the amplitude amplification operator
Wherein:
optionally, the constructing a second quantum circuit based on the amplitude amplification operator includes:
construction based on real control-Z gate and-I gate
Corresponding fifth sub-line, build +.>
Corresponding sixth sub-line constructs S based on the second virtual control-Z gate 0 A seventh sub-line corresponding to the first virtual control-Z gate, and an eighth sub-line corresponding to the first sub-line A, wherein the virtual control bits of the second virtual control-Z gate are n data bits and m-1 auxiliary bits;
and cascading the fifth sub-line, the sixth sub-line, the seventh sub-line and the eighth sub-line in sequence to obtain a second quantum line.
The embodiment of the invention also provides a storage medium, in which a computer program is stored, wherein the computer program is configured to perform the steps of any of the method embodiments described above when run.
Specifically, in the present embodiment, the above-described storage medium may be configured to store a computer program for executing the steps of:
acquiring an evolution operator corresponding to a first quantum circuit, wherein the first quantum circuit is used for obtaining a target quantum state, and the target quantum state is represented by a linear combination of two orthogonal ground states corresponding to target data and noise data;
and determining an amplitude amplification operator based on the evolution operator, and constructing a second quantum circuit based on the amplitude amplification operator, wherein when auxiliary bits in the second quantum circuit are measured, the probability of obtaining a ground state corresponding to the target data is larger than the probability of obtaining a ground state corresponding to the noise data.
Specifically, in the present embodiment, the storage medium may include, but is not limited to: a usb disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing a computer program.
Still another embodiment of the present invention provides an electronic device comprising a memory having a computer program stored therein and a processor configured to run the computer program to perform the steps of the method embodiment of any of the above.
Specifically, the electronic apparatus may further include a transmission device and an input/output device, where the transmission device is connected to the processor, and the input/output device is connected to the processor.
Specifically, in the present embodiment, the above-described processor may be configured to execute the following steps by a computer program:
acquiring an evolution operator corresponding to a first quantum circuit, wherein the first quantum circuit is used for obtaining a target quantum state, and the target quantum state is represented by a linear combination of two orthogonal ground states corresponding to target data and noise data;
and determining an amplitude amplification operator based on the evolution operator, and constructing a second quantum circuit based on the amplitude amplification operator, wherein when auxiliary bits in the second quantum circuit are measured, the probability of obtaining a ground state corresponding to the target data is larger than the probability of obtaining a ground state corresponding to the noise data.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims (10)
1. A method of constructing an amplitude amplifying circuit, the method comprising:
acquiring an evolution operator corresponding to a first quantum circuit, wherein the first quantum circuit is used for obtaining a target quantum state, and the target quantum state is represented by a linear combination of two orthogonal ground states corresponding to target data and noise data;
and determining an amplitude amplification operator based on the evolution operator, and constructing a second quantum circuit based on the amplitude amplification operator, wherein when auxiliary bits in the second quantum circuit are measured, the probability of obtaining a ground state corresponding to the target data is larger than the probability of obtaining a ground state corresponding to the noise data.
2. The method of claim 1, wherein the first quantum wire and the second quantum wire each comprise n data bits and 1 auxiliary bit, and the first quantum wire corresponds to a linear expression of
A is the evolution operator, ++>
The base states corresponding to the noise data and the target data are respectively, and cos theta and sin theta are respectively measured as |0 by the auxiliary bit>、|1>Amplitude at that time.
3. The method of claim 2, wherein the amplitude amplification operator
Wherein: s is S 0 ＝I-2|0> n+1 <0| n+1 ，/>
4. The method of claim 3, wherein the constructing a second quantum wire based on the amplitude amplification operator comprises:
construction based on Z-gate
Corresponding first sub-line, build +.>
Corresponding second sub-line, based on the first virtual control-Z gate to construct S 0 The corresponding third sub-line and the corresponding fourth sub-line of A are constructed, and the virtual control bit of the first virtual control-Z gate is n data bits;
and cascading the first sub-circuit, the second sub-circuit, the third sub-circuit and the fourth sub-circuit in sequence to obtain a second quantum circuit.
5. The method of claim 1, wherein the first quantum wire and the second quantum wire each comprise n data bits and m auxiliary bits, and the linear expression corresponding to the first quantum wire is
A is the evolution operator, ++>
The base states corresponding to the noise data and the target data are respectively, and cos theta and sin theta are respectively the auxiliary bits measured as
Amplitude at time, said->
And |1> m Orthogonal, m is an integer greater than 1.
6. The method of claim 5, wherein the amplitude amplification operator
Wherein:
7. the method of claim 6, wherein the constructing a second quantum wire based on the amplitude amplification operator comprises:
construction based on real control-Z gate and-I gate
Corresponding fifth sub-line, build +.>
Corresponding sixth sub-line constructs S based on the second virtual control-Z gate 0 A seventh sub-line corresponding to the first virtual control-Z gate, and an eighth sub-line corresponding to the first sub-line A, wherein the virtual control bits of the second virtual control-Z gate are n data bits and m-1 auxiliary bits;
and cascading the fifth sub-line, the sixth sub-line, the seventh sub-line and the eighth sub-line in sequence to obtain a second quantum line.
8. An apparatus for constructing an amplitude amplifying circuit, comprising:
the information acquisition unit is used for acquiring an evolution operator corresponding to a first quantum circuit, wherein the first quantum circuit is used for obtaining a target quantum state, and the target quantum state is represented by a linear combination of two orthogonal ground states corresponding to target data and noise data;
and the circuit construction unit is used for determining an amplitude amplification operator based on the evolution operator and constructing a second quantum circuit based on the amplitude amplification operator, wherein when auxiliary bits in the second quantum circuit are measured, the probability of obtaining the ground state corresponding to the target data is larger than the probability of obtaining the ground state corresponding to the noise data.
9. A storage medium having a computer program stored therein, wherein the computer program is arranged to perform the method of any of claims 1 to 7 when run.
10. An electronic device comprising a memory and a processor, characterized in that the memory has stored therein a computer program, the processor being arranged to run the computer program to perform the method of any of the claims 1 to 7.
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